74HCT534D,653 [NXP]
74HCT534 - 5 V octal D-type flip-flop; positive-edge trigger; 3-state; inverting SOP 20-Pin;
| 型号： | 74HCT534D,653 |
| 厂家： | 
NXP |
| 描述： | 74HCT534 - 5 V octal D-type flip-flop; positive-edge trigger; 3-state; inverting SOP 20-Pin 驱动 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总15页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HCT534
5 V octal D-type flip-flop; positive-edge trigger; inverting;
3-state
Rev. 03 — 18 October 2004
Product data sheet
1. General description
The 74HCT534 is a high-speed Si-gate CMOS device and is pin compatible with low
power Schottky TTL (LSTTL). The 74HCT534 is specified in compliance with JEDEC
standard no. 7A.
The 74HCT534 is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an
output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold
times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of
the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
flip-flops.
The 74HCT534 is functionally identical to the 74HCT374, but has inverted outputs.
2. Features
■ 3-state inverting outputs for bus oriented applications
■ 8-bit positive-edge triggered register
■ Common 3-state output enable input.
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
Conditions
Min
Typ
Max Unit
tPHL, tPLH propagation delay
CP to Qn
CL = 15 pF; VCC = 5 V
-
13
-
ns
fmax
maximum clock
frequency
CL = 15 pF; VCC = 5 V
CL = 50 pF; VCC = 4.5 V
-
40
-
MHz
CI
input capacitance
-
-
3.5
19
-
-
pF
pF
[1] [2]
CPD
power dissipation
capacitance per flip-flop
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC − 1.5 V.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HCT534N
74HCT534D
−40 °C t0 +125 °C
−40 °C t0 +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
plastic small outline package; 20 leads; body
width 7.5 mm
5. Functional diagram
3
4
7
8
Q0
Q1
Q2
Q3
2
5
6
9
D0
D1
D2
D3
FF1
to
FF8
3-STATE
OUTPUTS
13 D4
14 D5
17 D6
18 D7
Q4 12
Q5 15
Q6 16
Q7 19
11
1
CP
OE
mgm957
Fig 1. Functional diagram.
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
2 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
1
EN
11
11
C1
CP
3
2
5
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
7
8
2
5
6
9
4
7
1D
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
OE
1
mgm955
mgm956
Fig 2. Logic symbol.
Fig 3. IEC logic symbol.
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
FF
CP
CP
CP
CP
CP
CP
FF
FF
FF
FF
FF
FF
FF
1
2
3
4
5
6
7
8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mgm958
Fig 4. Logic diagram.
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
3 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
6. Pinning information
6.1 Pinning
1
2
20
19
18
17
16
15
14
13
12
11
OE
Q0
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
3
D0
4
D1
5
Q1
534
6
Q2
7
D2
8
D3
9
Q3
10
GND
001aab843
Fig 5. Pin configuration.
6.2 Pin description
Table 3:
Symbol
OE
Pin description
Pin
1
Description
3-state output enable input (active LOW)
3-state output
data input
Q0
2
D0
3
D1
4
data input
Q1
5
3-state output
3-state output
data input
Q2
6
D2
7
D3
8
data input
Q3
9
3-state output
ground (0 V)
GND
CP
10
11
12
13
14
15
16
17
18
19
20
clock input (LOW-to-HIGH, edge-triggered)
3-state output
data input
Q4
D4
D5
data input
Q5
3-state output
3-state output
data input
Q6
D6
D7
data input
Q7
3-state output
supply voltage
VCC
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
4 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
7. Functional description
7.1 Function table
[1]
Table 4:
Function table
Operating mode
Input
OE
L
Internal
flip-flops
Output Qn
CP
↑
Dn
Load and read
register
l
L
H
L
L
↑
h
l
H
L
Load register and
disable outputs
H
↑
Z
Z
H
↑
h
H
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max Unit
VCC
IIK
supply voltage
−0.5 +7
V
input diode current
output diode current
VI < −0.5 V or VI > VCC + 0.5 V
-
-
±20
mA
mA
IOK
VO < −0.5 V or
VO > VCC + 0.5 V
±20
±35
±70
IO
output source or sink
current
VO = −0.5 V to VCC + 0.5 V
-
mA
ICC, IGND VCC or GND current
-
mA
Tstg
Ptot
storage temperature
power dissipation
DIP20 package
−65
+150 °C
[1]
[2]
-
-
750
500
mW
SO20 package
mW
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 6:
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
4.5
0
Typ
5.0
-
Max
Unit
V
supply voltage
input voltage
5.5
VI
VCC
V
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
5 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
Table 6:
Symbol
VO
Recommended operating conditions …continued
Parameter
Conditions
Min
Typ
-
Max
VCC
500
Unit
V
output voltage
0
-
tr, tf
input rise and fall
times
VCC = 4.5 V
6.0
ns
Tamb
ambient
see Section 10 and 11
−40
-
+125
°C
temperature
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 °C
VIH
Parameter
Conditions
Min
Typ
Max
Unit
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
2.0
-
1.6
1.2
-
V
V
VIL
0.8
VOH
4.4
4.5
-
-
V
V
IO = −6 mA
3.98
4.32
VOL
LOW-level output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
-
0
0.1
V
IO = 6.0 mA
0.16
0.26
±0.1
±0.5
V
ILI
input leakage current
3-state OFF current
VI = VCC or GND; VCC = 5.5 V
-
-
µA
µA
IOZ
VI = VIH or VIL; other inputs
VCC or GND; VO = VCC or GND;
IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
8.0
µA
VCC = 5.5 V
∆ICC
additional quiescent supply
current per input pin
VI = VCC − 2.1 V; other inputs
VI = VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
pin OE
pin CP
pins Dn
-
-
-
-
125
90
450
325
125
-
µA
µA
µA
pF
35
CI
input capacitance
3.5
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
2.0
-
-
-
-
V
V
LOW-level input voltage
HIGH-level output voltage
0.8
VOH
4.4
-
-
-
-
V
V
IO = −6 mA
3.84
VOL
LOW-level output voltage
input leakage current
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
-
-
-
0.1
V
IO = 6.0 mA
0.33
±1.0
V
ILI
VI = VCC or GND; VCC = 5.5 V
µA
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
6 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOZ
3-state OFF current
VI = VIH or VIL; other inputs
-
-
±5
µA
VCC or GND; VO = VCC or GND;
IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
80
µA
VCC = 5.5 V
∆ICC
additional quiescent supply
current per input pin
VI = VCC − 2.1 V; other inputs
VI = VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
pin OE
pin CP
pins Dn
-
-
-
-
-
-
560
405
155
µA
µA
µA
Tamb = −40 °C to +125 °C
VIH
VIL
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
2.0
-
-
-
-
V
V
LOW-level input voltage
HIGH-level output voltage
0.8
VOH
4.4
3.7
-
-
-
-
V
V
IO = −6 mA
VOL
LOW-level output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
-
-
-
-
-
0.1
V
IO = 6.0 mA
0.4
V
ILI
input leakage current
3-state OFF current
VI = VCC or GND; VCC = 5.5 V
±1.0
±10
µA
µA
IOZ
VI = VIH or VIL; other inputs
VCC or GND; VO = VCC or GND;
IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
160
µA
VCC = 5.5 V
∆ICC
additional quiescent supply
current per input pin
VI = VCC − 2.1 V; other inputs
VI = VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
pin OE
pin CP
pins Dn
-
-
-
-
-
-
610
440
170
µA
µA
µA
11. Dynamic characteristics
Table 8:
Dynamic characteristics
GND = 0 V; VCC = 4.5 V; tr = tf = 6 ns; CL = 50 pF; see Figure 9
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Tamb = 25 °C
tPHL, tPLH
propagation delay CP to Qn
see Figure 6
CL = 50 pF; VCC = 4.5 V
CL = 15 pF; VCC = 5 V
see Figure 7
-
-
-
16
13
16
30
-
ns
ns
tPZH, tPZL
3-state output enable time OE to Qn
30
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
7 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
Table 8:
Dynamic characteristics …continued
GND = 0 V; VCC = 4.5 V; tr = tf = 6 ns; CL = 50 pF; see Figure 9
Symbol
tPHZ, tPLZ
tTHL, tTLH
tW
Parameter
Conditions
Min
-
Typ
18
5
Max Unit
3-state output disable time OE to Qn
output transition time
see Figure 7
30
12
-
ns
ns
ns
ns
ns
see Figure 6
-
clock pulse width HIGH or LOW
set-up time Dn to CP
see Figure 6
23
12
5
14
4
tsu
see Figure 8
-
th
hold time Dn to CP
see Figure 8
−1
-
fmax
maximum clock pulse frequency
see Figure 6
CL = 50 pF; VCC = 4.5 V
CL = 15 pF; VCC = 5 V
22
-
36
40
19
-
-
-
MHz
MHz
pF
[1] [2]
CPD
power dissipation capacitance per
flip-flop
-
Tamb = −40 °C to +85 °C
tPHL, tPLH
tPZH, tPZL
tPHZ, tPLZ
tTHL, tTLH
tW
propagation delay CP to Qn
see Figure 6
see Figure 7
see Figure 7
see Figure 6
see Figure 6
see Figure 8
see Figure 8
see Figure 6
-
-
-
-
-
-
-
-
-
38
38
38
15
-
ns
3-state output enable time OE to Qn
3-state output disable time OE to Qn
output transition time
-
ns
-
ns
-
ns
clock pulse width HIGH or LOW
set-up time Dn to CP
29
15
5
ns
tsu
-
ns
th
hold time Dn to CP
-
ns
fmax
maximum clock pulse frequency
18
-
MHz
Tamb = −40 °C to +125 °C
tPHL, tPLH
tPZH, tPZL
tPHZ, tPLZ
tTHL, tTLH
tW
propagation delay CP to Qn
see Figure 6
see Figure 7
see Figure 7
see Figure 6
see Figure 6
see Figure 8
see Figure 8
see Figure 6
-
-
-
-
-
-
-
-
-
45
45
45
18
-
ns
3-state output enable time OE to Qn
3-state output disable time OE to Qn
output transition time
-
ns
-
ns
-
ns
clock pulse width HIGH or LOW
set-up time Dn to CP
35
18
5
ns
tsu
-
ns
th
hold time Dn to CP
-
ns
fmax
maximum clock pulse frequency
15
-
MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC − 1.5 V.
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
8 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
12. Waveforms
1/f
max
V
CP input
M
t
W
t
t
PLH
PHL
V
M
Qn output
t
t
TLH
THL
mgm959
VM = 1.3 V; VI = GND to 3 V.
Fig 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock
pulse width, output transition times and the maximum clock pulse frequency.
t
t
r
f
90 %
V
OE input
M
10 %
t
t
PZL
PLZ
Qn output
V
M
LOW-to-OFF
OFF-to-LOW
10 %
t
t
PHZ
PZH
90 %
Qn output
V
M
HIGH-to-OFF
OFF-to-HIGH
outputs
enabled
outputs
enabled
outputs
disabled
mgm961
VM = 1.3 V; VI = GND to 3 V.
Fig 7. Waveforms showing the 3-state enable and disable times.
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
9 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
V
M
CP input
t
t
su
su
t
t
h
h
Dn input
V
M
Qn output
V
M
mgm960
VM = 1.3 V; VI = GND to 3 V.
Fig 8. Waveforms showing the data set-up and hold times for Dn input.
V
CC
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
L
R
T
mna101
Definitions test circuits:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance (See Section 11 for the value).
Fig 9. Load circuitry for switching times.
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
10 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
13. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
(1)
(1)
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 10. Package outline SOT146 (DIP20).
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
11 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 11. Package outline SOT163 (SO20).
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
12 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
14. Revision history
Table 9:
Revision history
Document ID
Release date Data sheet status
20041018 Product data sheet
Change notice Doc. number
Supersedes
74HCT534_3
-
9397 750 13817 74HC_HCT534_
CNV_2
Modifications:
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors
• Information related to 74HC534 type is deleted
• Reference to family specifications is replaced by the actual information.
74HC_HCT534_
CNV_2
19980410
Product specification
-
-
74HC_HCT534_1
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
13 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13817
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 18 October 2004
14 of 15
74HCT534
Philips Semiconductors
5 V octal D-type flip-flop; positive-edge trigger; inverting; 3-state
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information . . . . . . . . . . . . . . . . . . . . 14
9
10
11
12
13
14
15
16
17
18
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 18 October 2004
Document number: 9397 750 13817
Published in The Netherlands
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