74HCT534DB [NXP]
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| 型号： | 74HCT534DB |
| 厂家： | 
NXP |
| 描述： | 暂无描述 触发器 |
| 文件： | 总13页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT534
Octal D-type flip-flop; positive
edge-trigger; 3-state; inverting
1998 Apr 10
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
The 74HC/HCT534 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive, edge-triggered register
• Common 3-state output enable input
• Output capability: bus driver
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the
contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
• ICC category: MSI.
GENERAL DESCRIPTION
The 74HC/HCT534 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “534” is functionally identical to the “374”, but has
inverted outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
HC
HCT
13
t
PHL/ tPLH
propagation delay CP to Qn
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V 12
61
fmax
CI
40
3.5
19
MHz
pF
3.5
19
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
pF
Notes
1.
CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz.
fo = output frequency in MHz.
∑ (CL × VCC2 × fo) = sum of outputs.
CL = output load capacitance in pF.
VCC = supply voltage in V.
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V.
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
74HC534
74HC534
74HCT534
74HCT534
SO20
DIP20
SO20
DIP20
plastic small outline package; 20 leads; body width 7.5 mm
plastic dual in-line package; 20 leads (300 mil)
SOT163-1
SOT146-1
SOT163-1
SOT146-1
plastic small outline package; 20 leads; body width 7.5 mm
plastic dual in-line package; 20 leads (300 mil)
1998 Apr 10
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
3-state output enable input (active LOW)
1
OE
2, 5, 6, 9, 12, 15, 16, 19
Q0 to Q7
D0 to D7
GND
3-state outputs
3, 4, 7, 8, 13, 14, 17, 18
data inputs
10
11
20
ground (0 V)
CP
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
VCC
page
page
1
V
OE
1
2
20
19
18
17
16
15
14
13
12
11
CC
EN
C1
11
CP
page
11
Q
0
Q
D
7
3
4
2
5
D
0
3
7
6
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
3
4
7
8
2
1D
D
D
1
4
5
6
9
7
6
Q
Q
D
5
Q
1
8
9
6
5
534
13
14
17
18
12
15
16
19
6
Q
2
D
2
13
14
17
18
12
15
16
19
7
5
4
D
D
3
8
OE
9
Q
4
Q
3
1
MGM955
CP
GND
10
MGM956
MGM954
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Apr 10
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
handbook, halfpage
D
Q
Q
Q
Q
Q
Q
Q
Q
3
4
2
5
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
7
6
FF1
to
FF8
8
9
3-STATE
OUTPUTS
13
14
17
18
12
15
16
19
CP
OE
11
1
MGM957
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
Q0 to Q7
INTERNAL FLIP-FLOPS
OE
CP
Dn
load and read register
L
L
↑
↑
↑
↑
l
L
H
L
H
L
h
l
load register and disable outputs
H
H
Z
Z
h
H
Note
1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high impedance OFF-state; ↑ = LOW-to-HIGH clock transition.
1998 Apr 10
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
D
D
D
D
D
D
D
6
D
7
0
1
2
3
4
5
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
FF
1
FF
2
FF
3
FF
4
FF
5
FF
6
FF
7
FF
8
CP
OE
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
MGM958
Fig.5 Logic diagram.
1998 Apr 10
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver ICC category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQn
41
15
12
33
12
10
41
15
12
14
5
165
33
205
41
250
50
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
28
35
43
6.0
t
t
t
PZH/ tPZL 3-state output enable
150
30
190
38
225
45
2.0 Fig.7
4.5
time
OE to Qn
26
33
38
6.0
PHZ/ tPLZ 3-state output disable
150
30
190
38
225
45
2.0 Fig.7
4.5
time
OE to Qn
26
33
38
6.0
THL/ tTLH output transition time
60
75
90
2.0 Fig.6
4.5
12
15
18
4
10
13
15
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
60
12
10
5
19
7
100
20
17
75
15
13
5
120
24
20
90
18
15
5
2.0 Fig.6
4.5
6
6.0
tsu
set-up time
Dn to CP
6
2.0 Fig.8
4.5
2
2
6.0
th
hold time
Dn to CP
−3
−1
−1
18
55
66
2.0 Fig.8
4.5
5
5
5
5
5
5
6.0
fmax
maximum clock pulse
frequency
6.0
30
35
4.8
24
28
4.0
20
24
MHz 2.0 Fig.6
4.5
6.0
1998 Apr 10
6
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver ICC category: MSI.
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
1.25
OE
CP
Dn
0.90
0.35
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max min. max. min. max.
t
PHL/ tPLH propagation delay
CP to Qn
16
16
18
5
30
30
30
12
38
38
38
15
45
45
45
18
ns
ns
ns
ns
ns
ns
ns
4.5
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
Fig.8
Fig.8
Fig.6
tPZH/ tPZL 3-state output enable time
OE to Qn
4.5
4.5
4.5
4.5
4.5
4.5
tPHZ/ tPLZ 3-state output disable
time OE to Qn
tTHL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
23
12
5
14
4
29
15
5
35
18
5
tsu
th
set-up time
Dn to CP
hold time
Dn to CP
−1
36
fmax
maximum clock pulse
frequency
22
18
15
MHz 4.5
1998 Apr 10
7
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
AC WAVEFORMS
1/f
d
max
(1)
V
CP INPUT
M
t
t
W
t
PHL
PLH
(1)
t
V
Q
OUTPUT
M
n
t
MGM959
TLH
THL
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output
transition times and the maximum clock pulse frequency.
t
t
a
r
f
90%
(1)
V
OE INPUT
M
10%
t
t
PZL
PLZ
Q
OUTPUT
n
(1)
V
LOW-to-OFF
OFF-to-LOW
M
10%
t
t
PHZ
PZH
90%
Q
OUTPUT
n
(1)
V
HIGH-to-OFF
OFF-to-HIGH
M
outputs
enabled
outputs
enabled
outputs
disabled
MGM961
(1) HC: VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
8
1998 Apr 10
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
(1)
V
CP INPUT
M
t
t
su
su
t
t
h
h
(1)
D
INPUT
V
n
M
(1)
Q
OUTPUT
V
M
n
MGM960
The shaded areas indicate when the input is permitted to change for predictable output performance.
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
.
Fig.8 Waveforms showing the data set-up and hold times for Dn input.
1998 Apr 10
9
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
PACKAGE OUTLINES
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
2.0
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-05-24
SOT146-1
SC603
1998 Apr 10
10
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT163-1
075E04
MS-013AC
1998 Apr 10
11
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
Several techniques exist for reflowing; for example,
SOLDERING
Introduction
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1998 Apr 10
12
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Apr 10
13
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