74AUP1G79GF [NXP]
Low-power D-type flip-flop; positive-edge trigger; 低功耗D类IP- FL FL运算;正边沿触发
| 型号： | 74AUP1G79GF |
| 厂家： | 
NXP |
| 描述： | Low-power D-type flip-flop; positive-edge trigger |
| 文件： | 总20页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G79
Low-power D-type flip-flop; positive-edge trigger
Rev. 03 — 3 August 2009
Product data sheet
1. General description
The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information
on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D input must be stable one setup time prior to the LOW-to-HIGH clock
transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101-C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
SOT753
SOT353-1
74AUP1G79GV
74AUP1G79GW
−40 °C to +125 °C
−40 °C to +125 °C
SC-74A
plastic surface-mounted package; 5 leads
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
74AUP1G79GM
74AUP1G79GF
−40 °C to +125 °C
−40 °C to +125 °C
XSON6
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1G79GV
74AUP1G79GW
74AUP1G79GM
74AUP1G79GF
p79
pP
pP
pP
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
2
D
Q
4
1
2
4
D
Q
CP
CP
mna441
mna440
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
2 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
C
TG
C
mna442
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
74AUP1G79
74AUP1G79
D
1
2
3
6
5
4
V
CC
74AUP1G79
1
2
3
5
4
D
CP
V
CC
D
CP
1
2
3
6
5
4
V
CC
CP
n.c.
Q
n.c.
Q
GND
GND
GND
Q
001aac524
001aaf179
001aac562
Transparent top view
Transparent top view
Fig 4. Pin configuration
SOT353-1 and SOT753
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT353-1/SOT753 SOT886/SOT891
D
1
2
3
4
-
1
2
3
4
5
6
data input D
CP
GND
Q
clock pulse input CP
ground (0 V)
data output Q
not connected
supply voltage
n.c.
VCC
5
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
3 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
7. Functional description
Table 4.
Function table[1]
Input
Output
CP
↑
D
L
Q
L
↑
H
X
H
q
L
[1] H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one setup time prior to the LOW-to-HIGH CP transition.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
−50
−0.5
-
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
VO
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
±20
50
IO
output current
mA
mA
mA
°C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−50
−65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
0.8
0
Max
Unit
V
supply voltage
input voltage
output voltage
3.6
VI
3.6
V
VO
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
−40
0
+125
200
°C
ns/V
∆t/∆V
input transition rise and fall rate VCC = 0.8 V to 3.6 V
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
4 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.5
40
µA
µA
V
[1]
∆ICC
additional supply current
per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
CI
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
0.8
1.7
-
-
pF
pF
CO
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
5 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
µA
µA
V
[1]
∆ICC
additional supply current
per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
6 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.75 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.70 × VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage
-
-
-
-
0.25 × VCC
0.30 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
±0.75
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
µA
µA
V
[1]
∆ICC
additional supply current
per pin; VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
[1] One input at VCC − 0.6 V, other input at VCC or GND.
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
7 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions
25 °C
Min Typ[1] Max
−40 °C to +125 °C
Max Min
(85 °C) (85 °C) (125 °C) (125 °C)
Unit
Min
Max
CL = 5 pF
[2]
tpd
propagation CP to Q; see Figure 7
delay
VCC = 0.8 V
-
19.7
5.5
3.8
3.1
2.3
2.0
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CP; see Figure 8
2.6
2.0
1.7
1.4
1.2
11.0
7.0
5.4
4.0
3.4
2.4
1.8
1.5
1.1
0.9
12.9
8.1
6.4
4.7
4.0
2.4
1.8
1.5
1.1
0.9
14.2
9.0
7.1
5.2
4.4
fmax
maximum
frequency
VCC = 0.8 V
-
-
-
-
-
-
53
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
203
347
435
550
619
170
310
400
490
550
170
300
390
480
510
CL = 10 pF
[2]
tpd
propagation CP to Q; see Figure 7
delay
VCC = 0.8 V
-
23.1
6.3
4.4
3.6
2.8
2.5
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.1
2.5
2.1
1.8
1.7
12.3
8.1
6.3
4.7
4.1
2.8
2.2
1.9
1.5
1.3
14.4
9.5
7.5
5.6
4.5
2.8
2.2
1.9
1.5
1.3
15.9
10.5
8.3
6.2
5.0
fmax
maximum
frequency
CP; see Figure 8
VCC = 0.8 V
-
-
-
-
-
-
52
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
192
324
421
486
550
150
280
310
370
410
150
230
250
360
360
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
8 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions
25 °C
Min Typ[1] Max
−40 °C to +125 °C
Max Min
(85 °C) (85 °C) (125 °C) (125 °C)
Unit
Min
Max
CL = 15 pF
[2]
tpd
propagation CP to Q; see Figure 7
delay
VCC = 0.8 V
-
26.6
7.1
5.0
4.1
3.2
2.9
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CP; see Figure 8
3.5
2.8
2.4
2.2
2.0
13.6
9.2
7.1
5.4
4.5
3.2
2.5
2.2
1.9
1.6
15.6
10.7
8.5
3.2
2.5
2.2
1.9
1.6
17.2
11.8
9.4
6.3
7.0
5.0
5.5
fmax
maximum
frequency
VCC = 0.8 V
-
-
-
-
-
-
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
181
301
407
422
481
120
190
240
300
320
120
160
190
270
300
CL = 30 pF
[2]
tpd
propagation CP to Q; see Figure 7
delay
VCC = 0.8 V
-
36.8
9.3
6.4
5.3
4.3
3.9
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.7
3.8
3.3
3.0
2.8
17.3
11.8
9.4
4.2
3.3
3.0
2.7
2.6
23.3
14.3
11.3
8.5
4.2
3.3
3.0
2.7
2.6
25.6
15.7
12.4
9.4
7.0
5.8
7.2
7.9
fmax
maximum
frequency
CP; see Figure 8
VCC = 0.8 V
-
-
-
-
-
-
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
128
206
262
269
309
70
70
120
150
190
200
110
120
170
190
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
9 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions
25 °C
Min Typ[1] Max
−40 °C to +125 °C
Max Min
(85 °C) (85 °C) (125 °C) (125 °C)
Unit
Min
Max
CL = 5 pF, 10 pF, 15 pF and 30 pF
tsu
set-up time HIGH; D to CP;
see Figure 8
VCC = 0.8 V
-
-
-
-
-
-
3.4
0.8
0.5
0.5
0.4
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
1.6
1.0
0.9
0.7
0.6
1.4
1.0
0.9
0.7
0.6
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
LOW; D to CP; see Figure 8
VCC = 0.8 V
-
-
-
-
-
-
3.0
0.9
0.6
0.5
0.5
0.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
D to CP; see Figure 8
VCC = 0.8 V
1.4
1.0
0.9
0.8
1.0
1.4
1.0
0.9
0.8
1.0
th
hold time
-
-
-
-
-
-
-1.9
-0.6
-0.4
-0.4
-0.4
-0.3
-
-
-
-
-
-
-
0.2
0
-
-
-
-
-
-
-
0.2
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0
0
0
0
0
0
tW
pulse width HIGH or LOW; CP;
see Figure 8
VCC = 0.8 V
-
-
-
-
-
-
5.6
2.4
1.3
0.9
0.7
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.5
2.0
1.9
2.0
2.2
3.5
2.0
1.9
2.0
2.2
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
10 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions
25 °C
Min Typ[1] Max
−40 °C to +125 °C
Max Min
(85 °C) (85 °C) (125 °C) (125 °C)
Unit
Min
Max
[3]
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
VCC = 0.8 V
-
-
-
-
-
-
1.6
1.7
1.8
1.9
2.3
2.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
V
I
D input
GND
V
I
CP input
V
V
M
M
GND
t
t
PHL
PLH
V
OH
V
V
Q output
M
M
V
OL
mna443
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7. The clock input (CP) to output (Q) propagation delays
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
11 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
V
I
V
D input
M
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Q output
M
V
mna647
OL
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage drops that occur with the output load.
Fig 8. The clock input (CP) to output (Q) propagation delays, CP clock pulse width, D to CP setup times, CP to D
hold times and the CP maximum frequency
Table 9.
Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
12 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
13 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 10. Package outline SOT353-1 (TSSOP5)
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
14 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
02-04-16
06-03-16
SOT753
SC-74A
Fig 11. Package outline SOT753 (SC-74A)
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
15 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 12. Package outline SOT886 (XSON6)
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
16 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
(1)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 13. Package outline SOT891 (XSON6)
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
17 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
14. Abbreviations
Table 11. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
15. Revision history
Table 12. Revision history
Document ID
74AUP1G79_3
Modifications:
74AUP1G79_2
74AUP1G79_1
Release date
Data sheet status
Change notice
Supersedes
20090803
Product data sheet
-
74AUP1G79_2
• Added type number 74AUP1G79GV (SC-74A) package.
20061017
Product data sheet
-
74AUP1G79_1
-
20050912
Product data sheet
-
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
18 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AUP1G79_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 3 August 2009
19 of 20
74AUP1G79
NXP Semiconductors
Low-power D-type flip-flop; positive-edge trigger
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 August 2009
Document identifier: 74AUP1G79_3
相关型号：
74AUP1G79GM-H
IC AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, FF/Latch
NXP
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