74AUP1G79GM [NXP]
Low-power D-type flip-flop; positive-edge trigger; 低功耗D类IP- FL FL运算;正边沿触发
| 型号： | 74AUP1G79GM |
| 厂家： | 
NXP |
| 描述： | Low-power D-type flip-flop; positive-edge trigger |
| 文件： | 总20页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G79
Low-power D-type flip-flop; positive-edge trigger
Rev. 01 — 12 September 2005
Product data sheet
1. General description
The 74AUP1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information
on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock
transition for predictable operation.
2. Features
■ Wide supply voltage range from 0.8 V to 3.6 V
■ High noise immunity
■ Complies with JEDEC standards:
◆ JESD8-12 (0.8 V to 1.3 V)
◆ JESD8-11 (0.9 V to 1.65 V)
◆ JESD8-7 (1.2 V to 1.95 V)
◆ JESD8-5 (1.8 V to 2.7 V)
◆ JESD8-B (2.7 V to 3.6 V)
■ ESD protection:
◆ HBM JESD22-A114-C exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Low static power consumption; ICC = 0.9 µA (maximum)
■ Latch-up performance exceeds 100 mA per JESD 78 Class II
■ Inputs accept voltages up to 3.6 V
■ Low noise overshoot and undershoot < 10 % of VCC
■ IOFF circuitry provides partial Power-down mode operation
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3 ns.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tPHL, tPLH propagation delay
CP to Q
CL = 5 pF; RL = 1 MΩ
VCC = 0.8 V
-
19.7
5.5
3.8
3.1
2.3
2.0
309
-
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 30 pF;
2.6
2.0
1.7
1.4
1.2
-
11.0
7.0
5.4
4.0
3.4
-
ns
ns
ns
ns
ns
fclk(max)
maximum clock
frequency
MHz
VCC = 3.0 V to 3.6 V
Ci
input capacitance
-
0.8
-
pF
[1]
CPD
power dissipation
capacitance
f = 10 MHz;
VI = GND to VCC
VCC = 1.8 V
VCC = 3.3 V
-
-
2.3
3.0
-
-
pF
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
SOT353-1
74AUP1G79GW
74AUP1G79GM
−40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
5. Marking
Table 3:
Marking
Type number
74AUP1G79GW
74AUP1G79GM
Marking code
pP
pP
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
2 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
6. Functional diagram
1
2
D
Q
4
1
2
4
D
CP
CP
mna441
mna440
Fig 1. Logic symbol
Fig 2. IEC logic symbol
CP
C
C
C
C
D
TG
C
TG
Q
C
C
C
TG
C
TG
C
mna442
Fig 3. Logic diagram
7. Pinning information
7.1 Pinning
79
D
CP
1
2
3
6
5
4
V
CC
1
2
3
5
4
D
CP
V
CC
n.c.
Q
79
GND
GND
Q
001aac524
Transparent top view
001aac562
Fig 4. Pin configuration SOT353-1
(TSSOP5)
Fig 5. Pin configuration SOT886 (XSON6)
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
3 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
7.2 Pin description
Table 4:
Symbol
Pin description
Pin
Description
TSSOP5
XSON6
D
1
2
3
4
-
1
2
3
4
5
6
data input D
CP
GND
Q
clock pulse input CP
ground (0 V)
data output Q
not connected
supply voltage
n.c.
VCC
5
8. Functional description
8.1 Function table
Table 5:
Function table[1]
Input
Output
CP
↑
D
Q
L
L
↑
H
X
H
q
L
[1] H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH
CP transition.
9. Limiting values
Table 6:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
-
Max
+4.6
−50
Unit
V
VCC
IIK
supply voltage
input clamping
current
VI < 0 V
mA
[1]
VI
input voltage
−0.5
+4.6
V
IOK
output clamping
current
VO > VCC or VO < 0 V
-
±50
mA
[1]
[1]
VO
output voltage
active mode
−0.5
VCC + 0.5 V
Power-down mode
VO = 0 V to VCC
−0.5
+4.6
±20
+50
V
IO
output current
-
-
mA
mA
ICC
quiescent supply
current
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
4 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 6:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
−50
Unit
mA
°C
IGND
Tstg
Ptot
ground current
-
storage temperature
−65
+150
250
[2]
total power
dissipation
Tamb = −40 °C to +125 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
10. Recommended operating conditions
Table 7:
Recommended operating conditions
Symbol Parameter
Conditions
Min
0.8
0
Max Unit
VCC
VI
supply voltage
input voltage
output voltage
3.6
3.6
VCC
3.6
V
V
V
V
VO
active mode
0
Power-down mode; VCC = 0 V
0
Tamb
tr, tf
ambient temperature
−40
0
+125 °C
200 ns/V
input rise and fall times
VCC = 0.8 V to 3.6 V
11. Static characteristics
Table 8:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-state input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
5 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min
VOH HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
Typ
Max
Unit
VCC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
VOL
LOW-state output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
ILI
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.5
40
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current (per pin)
input capacitance
output capacitance
VCC = 3.3 V
Ci
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
0.8
1.7
-
-
pF
pF
Co
Tamb = −40 °C to +85 °C
VIH HIGH-state input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
6 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min
VOH HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
Typ
Max
Unit
VCC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
VOL
LOW-state output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
ILI
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current (per pin) CC = 3.3 V
V
Tamb = −40 °C to +125 °C
VIH HIGH-state input voltage
VCC = 0.8 V
0.75 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.70 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.25 × VCC
0.30 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
7 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min
VOH HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
Typ
Max
Unit
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
VOL
LOW-state output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
ILI
input leakage current
±0.75
±0.75
±0.75
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current (per pin) CC = 3.3 V
V
[1] One input at VCC − 0.6 V, other input at VCC or GND.
12. Dynamic characteristics
Table 9:
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C; CL = 5 pF
tPHL, tPLH
propagation delay CP to Q
see Figure 6
VCC = 0.8 V
-
19.7
5.5
3.8
3.1
2.3
2.0
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.6
2.0
1.7
1.4
1.2
11.0
7.0
5.4
4.0
3.4
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
8 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 9:
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk(max)
maximum clock frequency
see Figure 6
VCC = 0.8 V
-
-
-
-
-
-
53
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
203
347
435
550
619
Tamb = 25 °C; CL = 10 pF
tPHL, tPLH propagation delay CP to Q
see Figure 6
VCC = 0.8 V
-
23.1
6.3
4.4
3.6
2.8
2.5
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
3.1
2.5
2.1
1.8
1.7
12.3
8.1
6.3
4.7
4.1
fclk(max)
maximum clock frequency
VCC = 0.8 V
-
-
-
-
-
-
52
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
192
324
421
486
550
Tamb = 25 °C; CL = 15 pF
tPHL, tPLH propagation delay CP to Q
see Figure 6
VCC = 0.8 V
-
26.6
7.1
5.0
4.1
3.2
2.9
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
3.5
2.8
2.4
2.2
2.0
13.6
9.2
7.1
5.4
4.5
fclk(max)
maximum clock frequency
VCC = 0.8 V
-
-
-
-
-
-
50
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
181
301
407
422
481
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
9 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 9:
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
[1]
Symbol
Tamb = 25 °C; CL = 30 pF
tPHL, tPLH propagation delay CP to Q
Parameter
Conditions
Min
Typ
Max
Unit
see Figure 6
VCC = 0.8 V
-
36.8
9.3
6.4
5.3
4.3
3.9
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
4.7
3.8
3.3
3.0
2.8
17.3
11.8
9.4
7.0
5.8
fclk(max)
maximum clock frequency
VCC = 0.8 V
-
-
-
-
-
-
28
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
128
206
262
269
309
Tamb = 25 °C
tsu(H)
set-up time HIGH D to CP
set-up time LOW D to CP
hold time D to CP
see Figure 6
VCC = 0.8 V
-
-
-
-
-
-
3.4
0.8
0.5
0.5
0.4
0.4
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
tsu(L)
VCC = 0.8 V
-
-
-
-
-
-
3.0
0.9
0.6
0.5
0.5
0.7
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
th
VCC = 0.8 V
-
-
-
-
-
-
-1.9
-0.6
-0.4
-0.4
-0.4
-0.3
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
10 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 9:
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tW
CP pulse width HIGH or LOW
see Figure 6
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
f = 10 MHz
2.4
1.3
0.9
0.7
0.6
[2] [3]
CPD
power dissipation capacitance
VCC = 0.8 V
-
-
-
-
-
-
2.2
2.2
2.2
2.3
2.6
3.0
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[3] The condition is VI = GND to VCC
.
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Product data sheet
Rev. 01 — 12 September 2005
11 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 10: Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol
Parameter
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
CL = 5 pF
tPHL, tPLH
propagation delay
CP to Q
see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
2.4
1.8
1.5
1.1
0.9
12.9
8.1
6.4
4.7
4.0
2.4
1.8
1.5
1.1
0.9
14.2
9.0
7.1
5.2
4.4
ns
ns
ns
ns
ns
fclk(max)
maximum clock
frequency
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
170
310
400
490
550
-
-
-
-
-
170
300
390
480
510
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
CL = 10 pF
tPHL, tPLH
propagation delay
CP to Q
see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
2.8
2.2
1.9
1.5
1.3
14.4
9.5
7.5
5.6
4.5
2.8
2.2
1.9
1.5
1.3
15.9
10.5
8.3
ns
ns
ns
ns
ns
6.2
5.0
fclk(max)
maximum clock
frequency
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
150
280
310
370
410
-
-
-
-
-
150
230
250
360
360
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
CL = 15 pF
tPHL, tPLH
propagation delay
CP to Q
see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
3.2
2.5
2.2
1.9
1.6
15.6
10.7
8.5
3.2
2.5
2.2
1.9
1.6
17.2
11.8
9.4
ns
ns
ns
ns
ns
6.3
7.0
5.0
5.5
fclk(max)
maximum clock
frequency
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
120
190
240
300
320
-
-
-
-
-
120
160
190
270
300
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
12 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 10: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7
Symbol
Parameter
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
CL = 30 pF
tPHL, tPLH
propagation delay
CP to Q
see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
4.2
3.3
3.0
2.7
2.6
23.3
14.3
11.3
8.5
4.2
3.3
3.0
2.7
2.6
25.6
15.7
12.4
9.4
ns
ns
ns
ns
ns
7.2
7.9
fclk(max)
maximum clock
frequency
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
70
-
-
-
-
-
70
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
120
150
190
200
110
120
170
190
CL = 5 pF, 10 pF, 15 pF and 30 pF
tsu(H)
tsu(L)
th
set-up time HIGH
D to CP
see Figure 6
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
1.6
1.0
0.9
0.7
0.6
-
-
-
-
-
1.6
1.0
0.9
0.7
0.6
-
-
-
-
-
ns
ns
ns
ns
ns
set-up time LOW
D to CP
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
1.6
1.0
0.9
0.8
1.0
-
-
-
-
-
1.6
1.0
0.9
0.8
1.0
-
-
-
-
-
ns
ns
ns
ns
ns
hold time D to CP
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 6
0
0
0
0
0
-
-
-
-
-
0
0
0
0
0
-
-
-
-
-
ns
ns
ns
ns
ns
tW
CP pulse width
HIGH or LOW
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.5
2.0
1.9
2.0
2.2
-
-
-
-
-
3.5
2.0
1.9
2.0
2.2
-
-
-
-
-
ns
ns
ns
ns
ns
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
13 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
13. Waveforms
V
I
V
D input
M
t
GND
t
t
h
h
t
su(H)
su(L)
1/f
clk
V
I
CP input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Q output
M
V
001aad498
OL
Measurement points are given in Table 11.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 6. The clock input (CP) to output (Q) propagation delays, clock input (CP) pulse
width, data input (D) to clock input (CP) set-up times, clock input (CP) to data input
(D) hold times and the maximum input clock (CP) frequency
Table 11: Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
V
V
EXT
CC
5 kΩ
V
V
O
I
PULSE
GENERATOR
DUT
R
C
R
L
T
L
001aac521
Test data is given in Table 12.
Definitions for test circuit:
RL = Load resistor
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator
Fig 7. Load circuitry for switching times
9397 750 14682
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Product data sheet
Rev. 01 — 12 September 2005
14 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
Table 12: Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF,
5 kΩ or 1 MΩ open
GND
2 × VCC
15 pF and 30 pF
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times
and pulse width RL = 1 MΩ.
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
15 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
14. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 8. Package outline SOT353-1 (TSSOP5)
9397 750 14682
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 September 2005
16 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 9. Package outline SOT886 (XSON6)
9397 750 14682
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Product data sheet
Rev. 01 — 12 September 2005
17 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
15. Abbreviations
Table 13: Abbreviations
Acronym
CMOS
TTL
Description
Complementary Metal Oxide Semiconductor
Transistor Transistor Logic
Human Body Model
HBM
ESD
ElectroStatic Discharge
Machine Model
MM
CDM
Charged Device Model
16. Revision history
Table 14: Revision history
Document ID
Release date Data sheet status
20050912 Product data sheet
Change notice
Doc. number
Supersedes
74AUP1G79_1
-
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-
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Product data sheet
Rev. 01 — 12 September 2005
18 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
17. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
18. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
20. Trademarks
Notice — All referenced brands, product names, service names and
19. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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Product data sheet
Rev. 01 — 12 September 2005
19 of 20
74AUP1G79
Philips Semiconductors
Low-power D-type flip-flop; positive-edge trigger
22. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
9
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information . . . . . . . . . . . . . . . . . . . . 19
10
11
12
13
14
15
16
17
18
19
20
21
© Koninklijke Philips Electronics N.V. 2005
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Date of release: 12 September 2005
Document number: 9397 750 14682
Published in The Netherlands
相关型号：
74AUP1G79GM-H
IC AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, FF/Latch
NXP
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