74ALVCH16373 [NXP]
2.5V/3.3V 16-bit D-type transparent latch 3-State; 2.5V / 3.3V 16位D型透明锁存器三态
| 型号： | 74ALVCH16373 |
| 厂家： | 
NXP |
| 描述： | 2.5V/3.3V 16-bit D-type transparent latch 3-State |
| 文件： | 总12页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALVCH16373
2.5V/3.3V 16-bit D-type transparent latch
(3-State)
Product specification
1999 Sep 20
Supersedes data of 1998 Jun 29
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
FEATURES
PIN CONFIGURATION
• Wide supply voltage range of 1.2V to 3.6V
48 1LE
1OE
1Q0
1Q1
1
2
3
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
47
46
45
44
1D0
1D1
GND
1D2
TM
• MULTIBYTE flow-through standard pin-out architecture
GND
1Q2
4
5
• Low inductance multiple V and ground pins for minimum noise
CC
and ground bounce
43 1D3
1Q3
6
7
8
9
• Direct interface with TTL levels
• All data inputs have bus hold
42
41
40
V
CC
V
CC
1Q4
1Q5
1D4
1D5
• Output drive capability 50Ω transmission lines @ 85°C
• Current drive ±24 mA at 3.0 V
39 GND
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
DESCRIPTION
The 74ALVCH16373 is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. Incorporates bus hold data inputs which
eliminate the need for external pull-up or pull-down resistors to hold
unused inputs. One latch enable (LE) input and one output enable
(OE) are provided per 8-bit section.
33 2D2
32 2D3
The 74ALVCH16373 consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
31
30
V
CC
V
18
CC
2D4
2D5
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
29
28 GND
27 2D6
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
26
25
2D7
2LE
SW00066
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t ≤ 2.5ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
= 2.5V, C = 30pF
TYPICAL
2.1
UNIT
V
CC
V
CC
V
CC
V
CC
L
Propagation delay
Dn to Qn
= 3.3V, C = 50pF
2.1
L
t
/t
ns
PHL PLH
= 2.5V, C = 30pF
2.2
L
Propagation delay
LE to Qn
= 3.3V, C = 50pF
2.2
L
C
C
Input capacitance
5.0
pF
pF
I
Outputs enabled
Outputs disabled
16
1
Power dissipation capacitance per latch
V = GND to V
I CC
PD
10
NOTE:
1. C is used to determine the dynamic power dissipation (P in µW):
PD
D
2
2
P
= C × V
× f + S (C × V
× f ) where: f = input frequency in MHz; C = output load capacitance in pF;
CC o i L
D
PD
CC
i
L
2
f = output frequency in MHz; V = supply voltage in V; S (C × V
o
× f ) = sum of outputs.
o
CC
L
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
ACH16373 DL
DWG NUMBER
SOT370-1
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
74ALVCH16373 DL
74ALVCH16373 DGG
ACH16373 DGG
SOT362-1
2
1999 Sep 20
853-2086 22418
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
PIN DESCRIPTION
LOGIC SYMBOL
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
24
Output enable input
(active LOW)
1
1OE
1OE
2OE
2, 3, 5, 6, 8, 9,
11, 12
47
2
1D0
1Q0
1Q0 to 1Q7
GND
Data inputs/outputs
46
44
1D1
1D2
1Q1
1Q2
3
5
4, 10, 15, 21,
28, 34, 39, 45
Ground (0V)
43
41
1D3
1D4
1Q3
1Q4
6
8
7, 18, 31, 42
V
CC
Positive supply voltage
Data inputs/outputs
13, 14, 16, 17,
19, 20, 22, 23
40
38
37
1D5
1D6
1D7
1Q5
1Q6
1Q7
9
2Q0 to 2Q7
2OE
11
12
Output enable input
(active LOW)
24
25
36
35
2D0
2D1
2Q0
2Q1
13
14
Latch enable input (active
HIGH)
2LE
33
32
2D2
2D3
2Q2
2Q3
16
17
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7
1D0 to 1D7
1LE
Data inputs
Data inputs
30
29
2D4
2D5
2Q4
2Q5
19
20
47, 46, 44, 43,
41, 40, 38, 37
27
26
2D6
2D7
2Q6
2Q7
22
23
Latch enable input (active
HIGH)
48
1LE
48
2LE
25
SW00067
LOGIC DIAGRAM
1D0
D
Q
1Q0
2D0
D
Q
2Q0
LATCH
1
LATCH
9
LE LE
LE LE
1LE
2LE
1OE
2OE
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
SW00068
FUNCTION TABLE (per section of eight bits)
INPUTS
nLE
OUTPUTS
nQn
INTERNAL
LATCHES
OPERATING MODES
nOE
nDn
Enable and read register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
Latch and read register
(hold mode)
L
L
L
L
l
h
L
H
L
H
Latch register and disable outputs
H
H
L
L
l
h
L
H
Z
Z
H
= HIGH voltage level
h
L
l
= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
= LOW voltage level
= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X
Z
= don’t care
= high impedance OFF-state
3
1999 Sep 20
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
LOGIC SYMBOL (IEEE/IEC)
BUS HOLD CIRCUIT
V
CC
1
1EN
C3
1OE
48
24
25
1LE
2OE
2EN
C4
2LE
47
46
2
3
5
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
3D
1
Data Input
To internal circuit
44
43
41
6
8
9
40
38
11
12
37
SW00044
36
35
13
4D
2
14
16
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
33
32
17
19
30
29
20
22
23
27
26
SW00524
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
MIN
MAX
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
2.3
2.7
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
3.0
3.6
For data input pins
For control pins
0
0
V
CC
V
I
DC Input voltage range
V
5.5
V
O
DC output voltage range
0
V
CC
V
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 2.3 to 3.0V
= 3.0 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
4
1999 Sep 20
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +4.6
–50
UNIT
V
V
CC
I
IK
DC input diode current
V t0
I
mA
2
For control pins
–0.5 to +4.6
V
I
DC input voltage
V
2
For data inputs
–0.5 to V +0.5
CC
I
DC output diode current
DC output voltage
V
uV or V t 0
"50
mA
V
OK
O
CC
O
V
Note 2
= 0 to V
CC
–0.5 to V +0.5
O
CC
I
DC output source or sink current
V
O
"50
"100
mA
mA
°C
O
I
, I
DC V or GND current
GND CC
CC
T
Storage temperature range
–65 to +150
stg
Power dissipation per package
–plastic medium-shrink (SSOP)
–plastic thin-medium-shrink (TSSOP) above +55°C derate linearly with 8 mW/K
For temperature range: –40 to +125 °C
above +55°C derate linearly with 11.3 mW/K
850
600
P
TOT
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
= 1.8V
V
CC
0.7*V
0.9
1.2
1.5
CC
V
HIGH level Input voltage
V
IH
= 2.3 to 2.7V
= 2.7 to 3.6V
= 1.2V
1.7
2.0
GND
0.2*V
= 1.8V
0.9
1.2
1.5
CC
V
LOW level Input voltage
V
IL
= 2.3 to 2.7V
= 2.7 to 3.6V
0.7
0.8
= 1.8 to 3.6V; V = V or V ; I = –100µA
V
*0.2
V
CC
I
IH
IL
O
CC
= 1.8V; V = V or V ; I = –6mA
V
V
V
V
V
V
0.4
0.3
0.5
0.6
0.5
V
V
V
V
V
V
0.10
*
*
*
*
*
*
*
*
*
*
*
I
IH
IL
O
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 2.3V; V = V or V ; I = –6mA
0.08
0.17
0.26
0.14
0.28
I
IH
IL
O
= 2.3V; V = V or V ; I = –12mA
V
OH
HIGH level output voltage
V
I
IH
IL
O
= 2.3V; V = V or V ; I = –18mA
I
IH
IL
O
= 2.7V; V = V or V ; I = –12mA
I
IH
IL
O
= 3.0V; V = V or V
I
= –24mA
*1.0
CC
I
IH
IL; O
5
1999 Sep 20
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
V
V
V
V
V
V
V
V
= 1.8 to 3.6V; V = V or V ; I = 100µA
GND
0.09
0.07
0.15
0.23
0.14
0.27
0.20
0.30
0.20
0.40
0.60
0.40
0.55
CC
CC
CC
CC
CC
CC
CC
CC
I
IH
IL
O
= 1.8V; V = V or V ; I = 6mA
I
IH
IL
O
= 2.3V; V = V or V ; I = 6mA
I
IH
IL
O
= 2.3V; V = V or V ; I = 12mA
V
LOW level output voltage
V
I
IH
IL
O
OL
= 2.3V; V = V or V ; I = 12mA
I
IH
IL
O
= 2.7V; V = V or V ; I = 12mA
I
IH
IL
O
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
Input leakage current per
control pin
= 1.8 to 3.6V;
0.1
0.1
5
5
V = 5.5V or GND
I
I
µA
I
Input leakage current per data
pin
V
CC
= 1.8 to 3.6V;
CC
V = V or GND
I
V
V
= 1.8 to 2.7V; V = V or GND
0.1
0.1
10
15
CC
CC
CC
I
CC
Input current for common I/O
pins
I
/I
µA
µA
µA
IHZ ILZ
= 3.6V; V = V or GND
I
CC
3-State output OFF-state
current
V
V
= 2.7 to 3.6V; V = V or V ;
I IH IL
I
0.1
10
OZ
= V or GND
O
CC
V
= 1.8 to 2.7V; V = V or GND; I = 0
0.2
0.2
40
40
CC
CC
I
CC
O
I
Quiescent supply current
CC
V
= 2.7 to 3.6V; V = V or GND; I = 0
I
CC
O
Additional quiescent supply
current given per control pin
V
V
= 2.7V to 3.6V; V = V – 0.6V; I = 0
150
150
750
750
CC
I
CC
O
∆I
CC
µA
Additional quiescent supply
current given per data I/O pin
= 2.7V to 3.6V; V = V – 0.6V; I = 0
CC
I
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3V; V = 0.7V
45
75
–
I
Bus hold LOW sustaining
current
2
2
I
µA
µA
µA
µA
BHL
= 3.0V; V = 0.8V
150
I
= 2.3V; V = 1.7V
–45
–75
300
450
–300
–450
I
Bus hold HIGH sustaining
current
I
BHH
= 3.0V; V = 2.0V
–175
I
= 2.7V
= 3.6V
= 2.7V
= 3.6V
Bus hold LOW overdrive
current
2
I
BHLO
Bus hold HIGH overdrive
current
2
I
BHHO
NOTES:
1. All typical values are at T
= 25°C.
amb
2. Valid for data inputs of bus hold parts.
6
1999 Sep 20
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
AC CHARACTERISTICS FOR V = 2.3V TO 2.7V RANGE AND V < 2.3V
CC
CC
GND = 0V; t = t ≤ 2.0ns; C = 30pF
r
f
L
LIMITS
V
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 2.3 to 2.7V
= 1.8V
V
CC
= 1.2V UNIT
CC
1, 2
MIN
TYP
MAX
MIN
TYP1
MAX
TYP
8.8
Propagation delay
nDn to nYn
t
t
/t
1, 5
2, 5
1.0
1.0
2.1
3.9
3.9
1.5
1.5
3.2
3.4
5.7
ns
ns
PHL PLH
Propagation delay
nLE to nYn
/t
2.2
2.6
5.9
7.3
7.4
8.9
PHL PLH
3-State output enable
time
nOE to nYn
t
/t
4, 5
4, 5
1.0
1.0
5.2
4.1
1.5
1.5
4.0
ns
ns
PZH PZL
3-State output disable
time
t
/t
2.2
3.2
1.0
5.6
8.9
PHZ PLZ
nOE to nYn
t
nLE pulse width HIGH
Set-up time nDn to nLE
Hold time nDn to nLE
2
3
3
3.0
1.0
1.5
1.0
–0.1
0.2
–
–
–
3.5
1.0
1.2
–
–
–
–
–
–
ns
ns
ns
W
t
–0.1
0.1
SU
t
h
NOTES:
1. All typical values are measured at T
= 25°C.
amb
2. Typical value is measured at V = 2.5V.
CC
AC CHARACTERISTICS FOR V = 3.0V TO 3.6V RANGE AND V = 2.7V
CC
CC
GND = 0V; t = t ≤ 2.5ns; C = 50pF
r
f
L
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
UNIT
1, 2
1
MIN
TYP
MAX
MIN
TYP
MAX
Propagation delay
nDn to nYn
t
t
/t
1, 5
2, 5
4, 5
4, 5
1.0
1.0
1.0
1.0
2.1
3.3
3.2
4.2
4.1
1.0
1.0
1.0
1.0
2.3
2.2
2.9
3.7
ns
ns
ns
ns
PHL PLH
Propagation delay
nLE to nYn
/t
2.2
2.3
2.8
3.5
4.9
4.7
PHL PLH
3-State output enable time
nOE to nYn
t
/t
PZH PZL
3-State output disable time
nOE to nYn
t
/t
3.1
1.0
PHZ PLZ
t
nLE pulse width HIGH
Set-up time nDn to nLE
Hold time nDn to nLE
2
3
3
2.5
1.0
1.2
1.0
0.0
0.2
–
–
–
3.0
1.0
1.5
–
–
–
ns
ns
ns
W
t
–0.1
0.4
SU
t
h
NOTES:
1. All typical values are measured at T
= 25°C.
amb
2. Typical value is measured at V = 3.3V.
CC
7
1999 Sep 20
Philips Semiconductors
Product specification
16-bit D-type transparent latch (3-State)
74ALVCH16373
V
AC WAVEFORMS FOR V = 2.3V TO 2.7V AND
I
CC
V
< 2.3V RANGE
CC
V
OE INPUT
GND
V
M
M
V
V
V
V
= 0.5 V
M
CC
= V + 0.15V
X
Y
OL
OL
= V –0.15V
OH
and V are the typical output voltage drop that occur with the
OH
output load.
t
t
PZL
PLZ
V
= V
I
CC
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
AC WAVEFORMS FOR V = 3.0V TO 3.6V AND
M
CC
V
V
= 2.7V RANGE
X
CC
V
OL
V
M
V
X
V
Y
V
= 1.5 V
= V + 0.3V
OL
t
t
PZH
PHZ
= V –0.3V
OH
and V are the typical output voltage drop that occur with the
V
OL
OH
OH
output load.
V
Y
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
= 2.7V
V
I
M
GND
V
I
outputs
enabled
outputs
disabled
outputs
enabled
Dn INPUT
GND
V
V
M
M
t
SW00072
Waveform 4. 3-State enable and disable times
t
PHL
PLH
V
OH
TEST CIRCUIT
Qn OUTPUT
V
M
S
1
2 * V
CC
V
CC
Open
GND
V
OL
SW00070
R
R
= 500 Ω
= 500 Ω
L
L
V
V
O
Waveform 1. Input (Dn) to output (Qn) propagation delays
I
PULSE
GENERATOR
D.U.T.
R
T
C
L
V
I
LE INPUT
GND
V
V
V
M
M
M
Test Circuit for switching times
t
DEFINITIONS
w
t
t
PLH
R
C
R
= Load resistor
L
L
T
PHL
V
= Load capacitance includes jig and probe capacitance
= Termination resistance should be equal to Z of pulse generators.
OH
OUT
V
V
Qn OUTPUT
M
M
SWITCH POSITION
V
OL
TEST
S
V
V
I
1
CC
SW00071
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Qn) propagation delays
t
t
Open
< 2.7V
V
CC
PLH/ PHL
t
t
t
2.7–3.6V
2.7V
PLZ/ PZL
2 < V
CC
t
GND
PHZ/ PZH
V
I
SV00906
Dn
INPUT
V
M
t
Waveform 5. Load circuitry for switching times
GND
th
th
t
SU
SU
V
I
LE
INPUT
V
M
GND
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SW00073
Waveform 3. Data set-up and hold times for the Dn input to the
LE input
8
1999 Sep 20
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit D-type transparent latch (3-State)
74ALVCH16373
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
9
1999 Sep 20
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit D-type transparent latch (3-State)
74ALVCH16373
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
10
1999 Sep 20
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit D-type transparent latch (3-State)
74ALVCH16373
NOTES
11
1999 Sep 20
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit D-type transparent latch (3-State)
74ALVCH16373
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 10-99
Document order number:
9397-750-06515
Philips
Semiconductors
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