74AHC377D [NXP]
Octal D-type flip-flop with data enable; positive-edge trigger; 八路D - FL型IP- FL运算与数据使能;正边沿触发型号: | 74AHC377D |
厂家: | NXP |
描述: | Octal D-type flip-flop with data enable; positive-edge trigger |
文件: | 总20页 (文件大小:103K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC377; 74AHCT377
Octal D-type flip-flop with data
enable; positive-edge trigger
Product specification
2000 Aug 15
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
FEATURES
DESCRIPTION
• ESD protection:
The 74AHC/AHCT377 D-type flip-flops are high-speed
silicon-gate CMOS devices and are pin compatible with
low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
The 74AHC/AHCT377 devices have eight edge-triggered,
D-type flip-flops with individual D inputs and Q outputs.
A common clock (CP) input loads all flip-flops
simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than VCC
• Ideal for addressable register applications
• Data enable for address and data synchronization
• Eight positive-edge triggered D-type flip-flops
• See “273” for master reset version
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
• See “373” for transparent latch version
• See “374” for 3-state version
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 and from −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
tPHL/tPLH
PARAMETER
CONDITIONS
CL = 15 pF; VCC = 5 V
UNIT
AHC
AHCT
propagation delay;
CP to Qn
3.9
4.0
ns
fmax
CI
maximum clock frequency CL = 15 pF; VCC = 5 V
175
3.0
20
140
3.0
23
MHz
pF
input capacitance
VI = VCC or GND
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
.
2000 Aug 15
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
FUNCTION TABLE
See note 1.
INPUTS
CP
OUTPUTS
OPERATING MODES
E
Dn
Qn
load “1”
l
l
↑
↑
↑
X
h
l
H
load “0”
L
hold (do nothing)
h
H
X
X
no change
no change
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
X = don’t care;
↑ = LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS
PACKAGE
MATERIAL
CODE
74AHC377D
20
20
20
20
SO
plastic
plastic
plastic
plastic
SOT163-1
SOT360-1
SOT163-1
SOT360-1
74AHC377PW
74AHCT377D
74AHCT377PW
TSSOP
SO
TSSOP
PINNING
PIN
SYMBOL
DESCRIPTION
1
E
data enable input (active LOW)
flip-flop outputs
2, 5, 6, 9, 12, 15, 16 and 19
Q0 to Q7
D0 to D7
GND
3, 4, 7, 8, 13, 14, 17 and 18
data inputs
10
11
20
ground (0 V)
CP
clock input (LOW-to-HIGH, edge triggered)
DC supply voltage
VCC
2000 Aug 15
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
handbook, halfpage
V
E
1
2
20
19
18
17
16
15
14
13
12
11
CC
Q
Q
D
handbook, halfpage
11
0
0
1
1
2
2
3
3
7
CP
D
D
Q
Q
D
D
Q
3
7
6
3
4
2
5
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
D
4
7
6
Q
Q
D
5
6
5
8
9
377
6
13
14
17
18
12
15
16
19
7
5
4
D
8
Q
E
9
4
1
MNA605
GND
CP
10
MNA604
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
11
handbook, halfpage
1C2
1
G1
D
Q
Q
Q
Q
Q
Q
Q
Q
3
4
2
5
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
3
2
7
6
2D
8
FF1
to
FF8
9
4
7
8
5
6
9
OUTPUTS
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
1
E
11 CP
MNA606
MNA607
Fig.3 IEC logic symbol
Fig.4 Functional diagram.
2000 Aug 15
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
bnok,lfuapgedwith
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
E
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
MNA610
Fig.5 Logic diagram.
2000 Aug 15
5
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
RECOMMENDED OPERATING CONDITIONS
74AHC
74AHCT
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
VCC
VI
2.0
0
5.0
−
5.5
4.5
0
5.0
−
5.5
V
input voltage
5.5
5.5
V
VO
output voltage
0
−
VCC
+85
0
−
VCC
+85
V
Tamb
operating ambient temperature
see DC and AC
characteristics per
device
−40
−40
+25
+25
−40
+25
+25
°C
+125 −40
+125 °C
tr,tf (∆t/∆f) input rise and fall rates
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
−
−
−
−
100
20
−
−
−
−
−
ns/V
20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
VI
−0.5 +7.0
−0.5 +7.0
V
input voltage range
V
IIK
DC input diode current
DC output diode current
VI < −0.5 V; note 1
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−
−20
±20
±25
±75
mA
mA
mA
mA
IOK
IO
−
DC output source or sink current −0.5 V < VO < VCC + 0.5 V
DC VCC or GND current
−
ICC
Tstg
PD
−
storage temperature range
−65
−
+150 °C
500 mW
power dissipation per package
for temperature range: −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly by 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly by 5.5 mW/K.
2000 Aug 15
6
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
DC CHARACTERISTICS
74AHC family
With regard to recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
OTHER
VCC (V)
VIH
HIGH-level input
voltage
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
1.5
2.1
3.85
−
−
−
1.5
2.1
3.85
−
−
1.5
2.1
3.85
−
−
V
V
V
V
−
−
−
−
−
−
−
−
VIL
LOW-level input
voltage
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
−
−
−
−
−
−
−
−
VOH
HIGH-level output VI = VIH or VIL;
voltage; all
outputs
1.9
2.9
4.4
2.58
2.0
3.0
4.5
−
1.9
2.9
4.4
2.48
1.9
2.9
4.4
2.40
IO = −50 µA
−
−
−
−
−
−
HIGH-level output VI = VIH or VIL;
−
−
−
voltage
IO = −4.0 mA
VI = VIH or VIL;
4.5
3.94
−
−
3.8
−
3.70
−
IO = −8.0 mA
VOL
LOW-level output VI = VIH or VIL;
2.0
3.0
4.5
3.0
−
−
−
−
0
0
0
−
0.1
0.1
0.1
0.36
−
−
−
−
0.1
0.1
0.1
0.44
−
−
−
−
0.1
0.1
0.1
0.55
V
V
voltage; all
outputs
IO = 50 µA
LOW-level output VI = VIH or VIL;
voltage
IO = 4 mA
VI = VIH or VIL;
IO = 8 mA
4.5
−
−
−
−
−
−
−
−
−
3
0.36
0.1
−
−
0.44
1.0
±2.5
40
−
−
−
−
−
0.55
2.0
II
input leakage
current
VI = VCC or GND 5.5
µA
IOZ
ICC
CI
3-state output
OFF current
VI = VIH or VIL;
VO = VCC or GND
5.5
±0.25 −
±10.0 µA
quiescent supply VI = VCC or GND; 5.5
4.0
10
−
−
80
10
µA
current
IO = 0
input capacitance
−
10
pF
2000 Aug 15
7
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
74AHCT family
With regard to recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
OTHER VCC (V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
VIL
HIGH-level input
voltage
4.5 to 5.5 2.0
−
−
2.0
−
2.0
−
V
V
V
LOW-level input
voltage
4.5 to 5.5 −
−
0.8
−
−
0.8
−
−
0.8
−
VOH
HIGH-level output VI = VIH or VIL;
4.5
4.4 4.5
4.4
4.4
voltage; all
outputs
IO = −50 µA
HIGH-level output VI = VIH or VIL;
voltage IO = −8.0 mA
LOW-level output VI = VIH or VIL;
4.5
4.5
3.94
−
−
3.8
−
3.70
−
V
V
VOL
−
0
0.1
−
0.1
−
0.1
voltage; all
outputs
IO = 50 µA
LOW-level output VI = VIH or VIL;
4.5
5.5
5.5
−
−
−
−
−
−
0.36
0.1
−
−
0.44
1.0
−
−
−
0.55
2.0
V
voltage
IO = 8 mA
II
input leakage
current
VI = VIH or VIL
µA
IOZ
3-state output
OFF current
VI = VIH or VIL;
VO = VCC or GND
per input pin;
±0.25 −
±2.5
±10.0 µA
other inputs at
VCC or GND;
IO = 0
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
−
4.0
−
−
40
−
−
80
µA
∆ICC
additional
VI = VCC − 2.1 V 4.5 to 5.5 −
1.35
1.5
1.5
mA
quiescent supply
current per input
pin
other inputs at
VCC or GND;
IO = 0
CI
input capacitance
−
−
3
10
−
10
−
10
pF
2000 Aug 15
8
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
AC CHARACTERISTICS
Type 74AHC377
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
V
CC = 3.0 to 3.6 V; typical values at VCC = 3.3 V
tPHL/tPLH propagation delay
CP to Qn
see Figs 6 and 8 15 pF −
5.6
125
8.0
−
12.8 1.0
70
16.0 1.0
15.0 1.0
70
18.0 1.0
16.0 ns
fmax
maximum clock pulse see Figs 6 and 8
frequency
PHL/tPLH propagation delay
80
−
−
−
MHz
t
see Figs 6 and 8 50 pF −
20.0 ns
CP to Qn
tW
tsu
clock pulse width
HIGH or LOW
see Figs 6 and 8
see Figs 7 and 8
5.0
−
5.0
−
5.0
−
ns
set-up time Dn to CP
set-up time E to CP
hold time Dn to CP
hold time E to CP
5.0
5.0
1.5
1.5
50
−
−
−
−
−
−
5.0
5.0
1.5
1.5
45
−
−
−
−
−
5.0
5.0
1.5
1.5
45
−
−
−
−
−
ns
−
ns
th
−
ns
−
ns
fmax
maximum clock pulse see Figs 6 and 8
frequency
75
MHz
VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V
tPHL/tPLH propagation delay
CP to Qn
see Figs 6 and 8 15 pF −
3.9
9.0
1.0
10.5 1.0
110
12.0 1.0
11.5 ns
fmax
maximum clock pulse see Figs 6 and 8
frequency
125 175
−
110
−
−
MHz
tPHL/tPLH propagation delay
CP to Qn
see Figs 6 and 8 50 pF −
5.6
10.5 1.0
13.5 ns
tW
clock pulse width
HIGH or LOW
see Figs 6 and 8
see Figs 7 and 8
5.0
−
−
5.0
−
5.0
−
ns
tsu
tsu
th
set-up time Dn to CP
set-up time E to CP
hold time Dn to CP
hold time E to CP
4.5
4.5
2.0
2.0
85
−
−
−
−
−
−
4.5
4.5
2.0
2.0
75
−
−
−
−
−
4.5
4.5
2.0
2.0
75
−
−
−
−
−
ns
−
ns
−
ns
th
−
ns
fmax
maximum clock pulse see Figs 6 and 8
frequency
120
MHz
2000 Aug 15
9
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
Type 74AHCT377
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
T
amb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V
tPHL/tPLH propagation delay see Figs 6 and 8 15 pF
CP to Qn
−
4.0
140
5.7
−
9.0
−
1.0
80
10.5
1.0
80
11.5
ns
fmax
maximum clock
pulse frequency
see Figs 6 and 8
90
−
−
−
MHz
ns
tPHL/tPLH propagation delay see Figs 6 and 8 50 pF
10.5
−
1.0
5.0
4.5
4.5
2.0
2.0
75
12.0
−
1.0
5.0
4.5
4.5
2.0
2.0
75
13.5
−
CP to Qn
tW
tsu
clock pulse width see Figs 6 and 8
HIGH or LOW
5.0
4.5
4.5
2.0
2.0
85
ns
set-up time
Dn to CP
see Figs 7 and 8
−
−
−
−
ns
set-up time
E to CP
−
−
−
−
ns
th
hold time
Dn to CP
−
−
−
−
ns
hold time
E to CP
−
−
−
−
ns
fmax
maximum clock
pulse frequency
see Figs 6 and 8
130
−
−
−
MHz
2000 Aug 15
10
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
AC WAVEFORMS
1/f
max
V
I
(1)
V
CP input
GND
M
t
W
t
t
PHL
PLH
V
OH
(2)
M
V
Q
output
n
V
OL
MNA608
(1)
(2)
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
FAMILY
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT
GND to 3.0 V
Fig.6 The clock (CP) to output (Qn) propagation delays.
V
CC
(1)
E input
V
M
GND
t
t
h
h
t
t
su
su
V
CC
stable
(1)
D
input
V
n
M
GND
t
su
t
t
h
W
V
CC
(1)
CP input
V
M
GND
MNA609
(1)
VI INPUT
REQUIREMENTS
VM
INPUT
FAMILY
AHC
GND to VCC
50% VCC
1.5 V
The shaded areas indicate when the input is permitted to change for predicable
output performance.
AHCT
GND to 3.0 V
Fig.7 The data set-up and hold times for Dn input
11
2000 Aug 15
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
S1
V
CC
open
GND
V
CC
1000 Ω
V
I
V
O
PULSE
D.U.T.
GENERATOR
C
R
T
L
MNA183
TEST
tPLH/tPHL
PLZ/tPZL
S1
open
VCC
t
tPHZ/tPZH
GND
Fig.8 Load circuit for switching times.
2000 Aug 15
12
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
PACKAGE OUTLINES
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-05-22
99-12-27
SOT163-1
075E04
MS-013
2000 Aug 15
13
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT360-1
MO-153
2000 Aug 15
14
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Aug 15
15
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
REFLOW(1)
PACKAGE
WAVE
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Aug 15
16
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
STATUS
DEFINITIONS (1)
Objective specification
Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 Aug 15
17
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
NOTES
2000 Aug 15
18
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
NOTES
2000 Aug 15
19
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70
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613507/01/pp20
Date of release: 2000 Aug 15
Document order number: 9397 750 07331
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