RC28F640J3F75_技术文档

Numonyx™ Embedded Flash Memory (J3 65

nm) Single Bit per Cell (SBC)

32, 64, and 128 Mbit

Datasheet

Product Features

Architecture

Security

— Symmetrical 128-KB blocks

— 128 Mbit (128 blocks)

— 64 Mbit (64 blocks)

— 32 Mbit (32 blocks)

Performance

— Enhanced security options for code

protection

— 128-bit Protection Register:

64 unique device identification bits

64 user-programmable OTP bits

— Absolute protection with V_PEN= Vss

— Individual block locking

— Block erase/program lockout during power

transitions

— 75 ns Initial Access Speed

— 25 ns 8-word Asynchronous page-mode

reads

— 256-Word write buffer for x16 mode, 256-

Byte write buffer for x8 mode;

Software

— Program and erase suspend support

4 µs per Byte Effective programming time

— Flash Data Integrator (FDI), Common Flash

Interface (CFI) Compatible

— Scalable Command Set

System Voltage

— V_CC= 2.7 V to 3.6 V

— V_CCQ= 2.7 V to 3.6 V

Packaging

Quality and Reliability

— Operating temperature:

-40 °C to +85 °C

— 100K Minimum erase cycles per block

— 65 nm ETOX™ X Flash Technology

— 56-Lead TSOP

— 64-Ball Numonyx^™Easy BGA package

208032-01

May 2009

Legal Lines and Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND

CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A

PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx

products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.

Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented

subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or

otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the

Numonyx website at http://www.numonyx.com.

Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

2

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Contents

1.0 Introduction..............................................................................................................6

1.1

1.2

1.3

Nomenclature.....................................................................................................6

Acronyms...........................................................................................................7

Conventions .......................................................................................................7

2.0 Functional Overview..................................................................................................9

2.1

2.2

Block Diagram .................................................................................................. 11

Memory Map..................................................................................................... 12

3.0 Package Information............................................................................................... 13

3.1

3.2

56-Lead TSOP Package for 32-, 64-, 128-Mbit....................................................... 13

64-Ball Numonyx™ Easy BGA Package for 32-, 64-, 128-Mbit.................................. 14

4.0 Ballouts/Pinouts and Signal Descriptions ................................................................ 16

4.1

4.2

4.3

Numonyx™ Easy BGA Ballout for 32-, 64-, 128-Mbit .............................................. 16

56-Lead TSOP Package Pinout for 32-, 64-,128-Mbit .............................................. 17

Signal Descriptions............................................................................................ 18

5.0 Maximum Ratings and Operating Conditions............................................................ 19

5.1

5.2

5.3

Absolute Maximum Ratings................................................................................. 19

Operating Conditions ......................................................................................... 19

Power-Up/Down................................................................................................ 19

5.3.1 Power-Up/Down Sequence....................................................................... 19

5.3.2 Power Supply Decoupling ........................................................................ 20

Reset............................................................................................................... 20

5.4

6.0 Electrical Characteristics ......................................................................................... 21

6.1

6.2

6.3

DC Current Specifications................................................................................... 21

DC Voltage specifications.................................................................................... 22

Capacitance...................................................................................................... 22

7.0 AC Characteristics ................................................................................................... 23

7.1

7.2

7.3

7.4

Read Specifications............................................................................................ 23

Program, Erase, Block-Lock Specifications ............................................................ 28

Reset Specifications........................................................................................... 28

AC Test Conditions ............................................................................................ 29

8.0 Bus Interface........................................................................................................... 30

8.1

Bus Reads........................................................................................................ 31

8.1.1 Asynchronous Page Mode Read ................................................................ 31

8.1.2 Output Disable....................................................................................... 32

Bus Writes........................................................................................................ 32

Standby........................................................................................................... 33

8.3.1 Reset/Power-Down................................................................................. 33

Device Commands............................................................................................. 33

8.2

8.3

8.4

9.0 Flash Operations ..................................................................................................... 34

9.1

Status Register ................................................................................................. 34

9.1.1 Clearing the Status Register .................................................................... 35

Read Operations ............................................................................................... 35

9.2.1 Read Array............................................................................................ 35

9.2.2 Read Status Register .............................................................................. 36

9.2.3 Read Device Information......................................................................... 36

9.2.4 CFI Query ............................................................................................. 36

Programming Operations.................................................................................... 36

9.2

9.3

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Datasheet

3

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

9.3.1 Single-Word/Byte Programming................................................................36

9.3.2 Buffered Programming ............................................................................37

Block Erase Operations.......................................................................................38

Suspend and Resume.........................................................................................39

Status Signal ....................................................................................................40

Security and Protection.......................................................................................41

9.7.1 Normal Block Locking..............................................................................41

9.7.2 Configurable Block Locking.......................................................................42

9.7.3 Password Access.....................................................................................42

9.7.4 128-bit Protection Register.......................................................................42

9.7.5 Reading the 128-bit Protection Register.....................................................42

9.7.6 Programming the 128-bit Protection Register..............................................42

9.7.7 Locking the 128-bit Protection Register......................................................43

9.7.8 VPEN Protection......................................................................................44

9.4

9.5

9.6

9.7

10.0 ID Codes..................................................................................................................46

11.0 Device Command Codes ...........................................................................................47

12.0 Flow Charts..............................................................................................................48

13.0 Common Flash Interface..........................................................................................57

13.1 Query Structure Output......................................................................................57

13.2 Query Structure Overview...................................................................................58

13.3 Block Status Register .........................................................................................59

13.4 CFI Query Identification String ............................................................................59

13.5 System Interface Information..............................................................................60

13.6 Device Geometry Definition.................................................................................60

13.7 Primary-Vendor Specific Extended Query Table......................................................61

A

B

Additional Information.............................................................................................64

Ordering Information...............................................................................................65

Datasheet

4

May 2009

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Revision History

Date

Revision Description

01 Initial release

May 2009

208032-01

Datasheet

5

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

1.0

Introduction

This document contains information pertaining to the Numonyx™ Embedded Flash

Memory (J3 65 nm) Single Bit per Cell (SBC) device features, operation, and

specifications.

Unless otherwise indicated throughout the rest of this document, the Numonyx™

Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) device is referred to as

J3 65 nm SBC.

The J3 65 nm SBC device provides improved mainstream performance with enhanced

security features, taking advantage of the high quality and reliability of the NOR-based

65 nm technology. Offered in 128-Mbit, 64-Mbit, and 32-Mbit densities, the J3 65 nm

SBC device brings reliable, low-voltage capability (3 V read, program, and erase) with

high speed, low-power operation. The J3 65 nm SBC device takes advantage of proven

manufacturing experience and is ideal for code and data applications where high

density and low cost are required, such as in networking, telecommunications, digital

set top boxes, audio recording, and digital imaging. Numonyx Flash Memory

components also deliver a new generation of forward-compatible software support. By

using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers

can take advantage of density upgrades and optimized write capabilities of future

Numonyx Flash Memory devices.

1.1

Nomenclature

J3 65 nm SBC Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

All Densities

32 Mbit

AMIN = A0 for x8

AMIN = A1 for x16

AMAX = A21

AMIN

AMAX

64 Mbit

AMAX = A22

128 Mbit

AMAX = A23

Block

Clear

Program

Set

A group of flash cells that share common erase circuitry and erase simultaneously.

Indicates a logic zero (0)

Writes data to the flash array

Indicates a logic one (1)

VPEN

Refers to a signal or package connection name

Refers to timing or voltage levels

V

PEN

Datasheet

6

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

1.2

Acronyms

SBC

FDI

CFI

Single Bit per Cell

Flash Data Integrator

Common Flash Interface

Scalable Command Set

Command User Interface

One Time Programmable

Protection Lock Register

Protection Register

SCS

CUI

OTP

PLR

PR

PRD

RFU

SR

Protection Register Data

Reserved for Future Use

Status Register

SRD

WSM

ECR

ECD

Status Register Data

Write State Machine

Enhanced Configuration Register

Enhanced Configuration Register Data

1.3

Conventions

h

Hexadecimal Suffix

1,000

K(noun)

M (noun)

Nibble

Byte

Word

Kb

1,000,000

4 bits

8 bits

16 bits

1,024 bits

KB

1,024 bytes

1,024 words

1,048,576 bits

1,048,576 bytes

1,048,576 words

1,024 bits

KW

Mb

MB

MW

Kbit

Mbit

1,048,576 bits

May 2009

208032-01

Datasheet

7

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Brackets

Square brackets ([]) will be used to designate group membership or to

define a group of signals with similar function (i.e. A[21:1], SR[4,1]

and D[15:0]).

00FFh

Denotes 16-bit hexadecimal numbers

Denotes 32-bit hexadecimal numbers

Data I/O signals

00FF 00FFh

DQ[15:0]

Datasheet

8

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

2.0

Functional Overview

The J3 65 nm SBC family contains high-density memory organized in any of the

following configurations:

• 16-MB or 8-MW (128-Mbit), organized as one-hundred-twenty-eight 128-KB erase

blocks.

• 8-MB or 4-MW (64-Mbit), organized as sixty-four 128-KB erase blocks.

• 4-MB or 2-MW (32-Mbit), organized as thirty-two 128-KB erase blocks.

These devices can be accessed as 8- or 16-bit words. See Figure 1, “Memory Block

Diagram for 32-, 64-, 128-Mbit” on page 11 for further details.

A 128-bit Protection Register has multiple uses, including unique flash device

identification.

The J3 65 nm SBC device includes new security features that were not available on the

(previous) 0.13µm versions of the J3 family. These new security features prevent

altering of code through different protection schemes that can be implemented, based

on user requirements.

The J3 65 nm SBC optimized architecture and interface dramatically increases read

performance by supporting page-mode reads. This read mode is ideal for non-clock

memory systems.

Its Common Flash Interface (CFI) permits software algorithms to be used for entire

families of devices. This allows device-independent, JEDEC ID-independent, and

forward- and backward-compatible software support for the specified flash device

families. Flash vendors can standardize their existing interfaces for long-term

compatibility.

The Scalable Command Set (SCS) allows a single, simple software driver in all host

systems to work with all SCS-compliant flash memory devices, independent of system-

level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally,

SCS provides the highest system/device data transfer rates and minimizes device and

system-level implementation costs.

A Command User Interface (CUI) serves as the interface between the system processor

and internal operation of the device. A valid command sequence written to the CUI

initiates device automation. An internal Write State Machine (WSM) automatically

executes the algorithms and timings necessary for block erase, program, and lock-bit

configuration operations.

A block erase operation erases one of the device’s 128-KB blocks typically within one

second, independent of other blocks. Each block can be independently erased 100,000

times. Block erase suspend mode allows system software to suspend block erase to

read or program data from any other block. Similarly, program suspend allows system

software to suspend programming (byte/word program and write-to-buffer operations)

to read data or execute code from any other block that is not being suspended.

Each device incorporates a Write Buffer of 256-Byte (x8 mode) or 256-Word (x16

mode) to allow optimum programming performance. By using the Write Buffer data is

programmed more efficiently in buffer increments.

Memory Blocks are selectively and individually lockable in-system. Individual block

locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase

and program operations. Lock-bit configuration operations set and clear lock-bits (using

the Set Block Lock-Bit and Clear Block Lock-Bits commands).

May 2009

208032-01

Datasheet

9

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

The Status Register indicates when the WSM’s block erase, program, or lock-bit

configuration operation completes.

The STS (status) output gives an additional indicator of WSM activity by providing both

a hardware signal of status (versus software polling) and status masking (interrupt

masking for background block erase, for example). Status indication using STS

minimizes both CPU overhead and system power consumption. When configured in

level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the

WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates

that the WSM is ready for a new command, block erase is suspended (and

programming is inactive), program is suspended, or the device is in reset/power-down

mode. Additionally, the configuration command allows the STS signal to be configured

to pulse on completion of programming and/or block erases.

Three CE signals are used to enable and disable the device. A unique CE logic design

(see Table 17, “Chip Enable Truth Table for 32-, 64-, 128-Mb” on page 30) reduces

decoder logic typically required for multi-chip designs. External logic is not required

when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module.

The BYTE# signal allows either x8 or x16 read/writes to the device:

• BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high

byte.

• BYTE#-high enables16-bit operation; address A1 becomes the lowest order

address and address A0 is not used (don’t care).

Figure 1, “Memory Block Diagram for 32-, 64-, 128-Mbit” on page 11 shows a device

block diagram.

When the device is disabled (see Table 17, “Chip Enable Truth Table for 32-, 64-, 128-

Mb” on page 30), with CEx at V_IHand RP# at V_IH, the standby mode is enabled. When

RP# is at V_IL, a further power-down mode is enabled which minimizes power

consumption and provides write protection during reset. A reset time (t_PHQV) is

required from RP# going high until data outputs are valid. Likewise, the device has a

wake time (t_PHWL) from RP#-high until writes to the CUI are recognized. With RP# at

V_IL, the WSM is reset and the Status Register is cleared.

Datasheet

10

May 2009

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

2.1

Block Diagram

Figure 1: Memory Block Diagram for 32-, 64-, 128-Mbit

May 2009

208032-01

Datasheet

11

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

2.2

Memory Map

Figure 2: J3 65 nm SBC Memory Map

A [23:0]:128 Mbit

A [22:0]: 64Mbit

A [21:0]: 32Mbit

A [23:1]:128 Mbit

A [22:1]: 64Mbit

A [21:1]: 32Mbit

FFFFFFh

7FFFFFh

7F0000h

-

128 KB Block 127

-

64 KW Block

127

63

FE0000h

7FFFFFh

7E0000h

3FFFFFh

3F0000h

-

128 KB Block

63

31

-

64 KW Block

3FFFFFh

3E0000h

1FFFFFh

1F0000h

-

128 KB Block

-

64 KW Block

31

03FFFFh

01FFFFh

-

128 KB Block

1

0

-

64 KW Block

1

0

020000h

01FFFFh

000000h

010000h

00FFFFh

000000h

128-KB Block

64- KW Block

Byte-Wide (x 8 ) Mode

Word-Wide (x16) Mode

Datasheet

12

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

3.0

Package Information

3.1

56-Lead TSOP Package for 32-, 64-, 128-Mbit

Figure 3: 56-Lead TSOP Package Mechanical

Z

A

2

See Note 2

See Notes 1 and 3

Pin 1

e

See Detail B

E

Y

D

1

A

1

D

Seating

Plane

See Detail A

A

Detail A

Detail B

C

0

b

L

Notes:

1.

2.

3.

One dimple on package denotes Pin 1.

If two dimples, then the larger dimple denotes Pin 1.

Pin 1 will always be in the upper left corner of the package, in reference to the product mark.

Table 1:

56-Lead TSOP Dimension Table

Millimeters

Nom

Inches

Nom

Parameter

Symbol

Min

Max

Min

Max

Package Height

Standoff

A

—

1.200

—

0.047

—

A

0.050

0.965

0.100

18.200

13.800

—

0.002

0.038

0.004

0.717

0.543

—

1

2

Package Body Thickness

Lead Width

A

0.995

0.150

18.400

14.000

0.500

20.00

0.600

1.025

0.200

18.600

14.200

—

0.039

0.006

0.724

0.551

0.0197

0.787

0.024

0.040

0.008

0.732

0.559

—

b

Lead Thickness

Package Body Length

Package Body Width

Lead Pitch

c

D

1

E

e

D

L

Terminal Dimension

Lead Tip Length

19.800

0.500

20.200

0.700

0.780

0.020

0.795

0.028

May 2009

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Datasheet

13

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 1:

56-Lead TSOP Dimension Table

Millimeters

Nom

Inches

Nom

Parameter

Symbol

Min

Max

Min

Max

Lead Count

N

θ

—

0°

56

3°

—

0°

56

3°

—

Lead Tip Angle

5°

Seating Plane Coplanarity

Lead to Package Offset

Y

Z

—

0.100

0.350

—

0.004

0.014

0.150

0.250

0.006

0.010

3.2

64-Ball Numonyx™ Easy BGA Package for 32-, 64-, 128-

Mbit

Figure 4: 64-Ball Numonyx™ Easy BGA Mechanical Specifications

Ball A1

Corner

Ball A1

D

S₁

Corner

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

S₂

A

B

C

D

E

F

A

B

C

D

E

F

E

G

H

G

H

e

b

Bottom View - Ball Side Up

Top View - Plastic Backside

Complete Ink Mark Not Shown

A1

A2

A

Seating

Plane

Y

Table 2:

Easy BGA Package Dimensions Table (Sheet 1 of 2)

Millimeters

Inches

Nom

Parameter

Symbol

Min

Nom

Max

Min

Max

Package Height

Ball Height

A

—

1.200

—

0.0098

—

0.0472

—

A1

A2

b

0.250

—

Package Body Thickness

Ball (Lead) Width

0.780

0.410

—

0.0307

0.016

—

0.310

0.510

0.012

0.020

Datasheet

14

May 2009

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 2:

Easy BGA Package Dimensions Table (Sheet 2 of 2)

Millimeters

Inches

Nom

Parameter

Symbol

Min

Nom

Max

Min

Max

Package Body Width

D

9.900

10.000 10.100 0.3898 0.3937 0.3976

Package Body Length

Pitch

E

12.900 13.000 13.100 0.5079 0.5118 0.5157

e

—

1.000

64

—

0.0394

64

—

Ball (Lead) Count

N

—

Seating Plane Coplanarity

Corner to Ball A1 Distance Along D

Corner to Ball A1 Distance Along E

Y

—

0.100

1.600

3.100

—

0.0039

S1

S2

1.400

2.900

1.500

3.000

0.0551 0.0591 0.0630

0.1142 0.1181 0.1220

May 2009

208032-01

Datasheet

15

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

4.0

Ballouts/Pinouts and Signal Descriptions

J3 65 nm SBC is available in two package types. All densities of the J3 65 nm SBC

devices are supported on both 64-ball Numonyx™ Easy BGA and 56-lead Thin Small

Outline Package (TSOP) packages. The figures below show the ballouts/Pinouts.

4.1

Numonyx™ Easy BGA Ballout for 32-, 64-, 128-Mbit

Figure 5: Numonyx™ Easy BGA Ballout (32/64/128 Mbit)

1

2

3

4

5

6

7

8

7

6

5

2

4

3

1

A

B

A

B

(2)

A1

A2

A3

A4

A6

VSS

A7

A8

A9

VPEN A13

VCC A18

RFU A19

RFU A20

A22

CE1

A21

A17

A22

CE1

A21

A17

A18

A19

A20

A16

VCC

RFU

A13

A14

A6

VPEN

CE0

A12

A8

A9

A1

A2

CE0

A12

A14

A15

VSS

A7

C

D

E

F

C

D

E

F

A10

A11

DQ9

A15

A10

A11

DQ9

A3

A5

RP#

DQ3

RFU RFU A16

RFU

DQ4

A5

RP#

DQ3

A4

DQ8 DQ1

DQ4

RFU DQ15 STS

STS DQ15 RFU

DQ1

DQ0

DQ8

BYTE#

BYTE# DQ0 DQ10 DQ11 DQ12 RFU

RFU OE#

OE#

RFU RFU DQ12

DQ11 DQ10

VCCQ DQ2

G

H

G

H

(3)

A23

A0⁽¹⁾DQ2 VCCQ DQ5

DQ6 DQ14 WE#

WE# DQ14 DQ6

DQ5

A0

(1)

(3)

A23

(4)

A24

CE2

RFU VCC

VSS DQ13 VSS

DQ7 A24

DQ7 VSS DQ13

RFU

VSS

VCC

CE2

Easy BGA

Top View– Ball Side Down

Bottom View– Ball Side Up

Notes:

1.

2.

3.

4.

A0 is the least significant address bit.

A22 is valid on 64-Mbit densities and above, otherwise, it is a no connect (NC).

A23 is valid on 128-Mbit; otherwise, it is a no connect (NC).

A24 is a no connect (NC) on 128-, 64-, 32- Mbit, and reserved for 256-Mbit.

Datasheet

16

May 2009

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

4.2

56-Lead TSOP Package Pinout for 32-, 64-,128-Mbit

Figure 6: 56-Lead TSOP Package Pinout (32/64/128 Mbit)

(3)

(5)

A₂₂

CE1

A₂₁

A₂₀

A₁₉

A₁₈

A₁₇

A₁₆

VCC⁽¹⁾

A₁₅

A₁₄

A₁₃

A₁₂

CE0

VPEN

RP#

A₁₁

A₁₀

A₉

56

55

54

1

2

A₂₄

WE#

OE#

STS

DQ₁₅

DQ₇

3

53

52

4

5

51

6

50

49

48

47

46

7

DQ₁₄

DQ₆

8

9

VSS

DQ₁₃

DQ₅

10

Numonyx^TMEmbedded Flash Memory J3

11

12

13

45

44

43

DQ₁₂

DQ₄

14

VCCQ

VSS

DQ₁₁

DQ₃

56-Lead TSOP Package

42

41

40

39

15

16

17

18

14 mm x 20 mm

Top View

DQ₁₀

DQ₂

38

19

A₈

37

36

20

21

22

VCC

DQ₉

VSS

A₇

35

DQ₁

A₆

34

33

32

31

23

24

25

26

DQ₈

A₅

DQ₀

A₀⁽²⁾

A₄

A₃

BYTE#

(4)

A₂

30

29

27

28

A₂₃

A₁

CE2

Notes:

1.

2.

3.

4.

5.

No internal connection for pin 9; it may be driven or floated. For legacy designs, the pin can be tied to V

A0 is the least significant address bit.

A22 exists on 64- and 128- densities. On 32-Mbit density this signal is a no-connect (NC).

A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC).

A24 is a no connect (NC) on 128-, 64-, 32- Mbit, reserved for 256-Mbit.

.

CC

May 2009

208032-01

Datasheet

17

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

4.3

Signal Descriptions

Table 3 lists the active signals used on J3 65 nm SBC and provides a description of

each.

Table 3:

Signal Descriptions for J3 65 nm SBC

Symbol

Type

Name and Function

BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This

address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is

turned off when BYTE# is high).

A0

Input

ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are

internally latched during a program cycle:

32-Mbit — A[21:1]

64-Mbit— A[22:1]

128-Mbit — A[23:1]

A[MAX:1]

Input

LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands

during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data

is internally latched during write operations.

Input/

Output

DQ[7:0]

HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.

Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register

reads. Data is internally latched during write operations in x16 mode. D[15:8] float in x8 mode.

Input/

Output

DQ[15:8]

CHIP ENABLE: Activates the 32-, 64-, 128-Mbit devices’ control logic, input buffers, decoders, and

sense amplifiers. When the device is de-selected (see Table 17, “Chip Enable Truth Table

for 32-, 64-, 128-Mb” on page 30), power reduces to standby levels.

All timing specifications are the same for these three signals. Device selection occurs with the first

edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of

CE0, CE1, or CE2 that disables the device (see Table 17, “Chip Enable Truth Table for

32-, 64-, 128-Mb” on page 30).

CE[2:0]

RP#

Input

RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high

enables normal operation. Exit from reset sets the device to read array mode. When driven low,

RP# inhibits write operations which provides data protection during power transitions.

Input

OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.

OE#

WE#

Input

OE# is active low.

WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.

Addresses and data are latched on the rising edge of WE#.

STATUS: Indicates the status of the internal state machine. When configured in level mode

(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to

indicate program and/or erase completion. For alternate configurations of the Status signal, see the

Configurations command and Section 9.6, “Status Signal” on page 40. STS is to be tied

to VCCQ with a pull-up resistor.

Open Drain

Output

STS

BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while

D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high places

the device in x16 mode, and turns off the A0 input buffer, the address A1 becomes the lowest-order

address bit.

BYTE#

Input

ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or

configuring lock-bits.

VPEN

VCC

Input

With V

≤ V

, memory contents cannot be altered.

PEN

PENLK

CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when V

CC

≤ V

.

Power

Lko

Caution: Device operation at invalid Vcc voltages should not be attempted.

I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to V

GROUND: Ground reference for device logic voltages. Connect to system ground.

No Connect: Lead is not internally connected; it may be driven or floated.

VCCQ

VSS

NC

Power

Supply

—

.

CC

Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device

functionality and enhancement.

RFU

—

Datasheet

18

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

5.0

Maximum Ratings and Operating Conditions

5.1

Absolute Maximum Ratings

Warning:

Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent

damage. These are stress ratings only.

NOTICE: This document contains information available at the time of its release. The specifications are subject to change without

notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design.

Table 4:

Absolute Maximum Ratings

Parameter

Min

Max

Unit

Notes

Temperature under Bias Expanded (T , Ambient)

A

–40

–65

–2.0

—

+85

°C

V

—

2

Storage Temperature

+125

VCC Voltage

+5.6

VCCQ Voltage

+5.6

V

2

Voltage on any input/output signal (except VCC, VCCQ)

V

(max) + 2.0

100

V

1

CCQ

I

Output Short Circuit Current

mA

3

SH

Notes:

1.

Voltage is referenced to V . During infrequent non-periodic transitions, the voltage potential between V and input/

SS SS

output pins may undershoot to –2.0 V for periods < 20 ns or overshoot to V

(max) + 2.0 V for periods < 20 ns.

CCQ

2.

3.

During infrequent non-periodic transitions, the voltage potential between V and the supplies may undershoot to –2.0

CC

V for periods < 20 ns or V

(max) + 2.0 V for periods < 20 ns.

SUPPLY

Output shorted for less than one second. One output pin/ball shorted at a time

5.2

Operating Conditions

Warning:

Operations beyond the “Operating Conditions” is not recommended and extended

exposure beyond the “Operating Conditions” may affect device reliability.

Table 5:

Temperature and V_CCOperating Condition

Symbol

Parameter

Min

-40.0

Max

Unit

Test Condition

T

Operating Temperature

VCC Supply Voltage

VCCQ Supply Voltage

+85

3.6

°C

V

Ambient Temperature

A

V

2.70

—

CC

V

CCQ

5.3

Power-Up/Down

This section provides an overview of system level considerations with regards to the

flash device. It includes a brief description of power-up/down sequence and decoupling

design considerations.

5.3.1

Power-Up/Down Sequence

To prevent conditions that could result in spurious program or erase operations, the

power-up/power-down sequence shown in Table 6 is recommended. For DC voltage

characteristics refer to Table 8. Note that each power supply must reach its minimum

voltage range before applying/removing the next supply voltage.

May 2009

208032-01

Datasheet

19

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 6:

Power-Up/Down Sequence

Power Supply

Voltage

Power-Up Sequence

Power-Down Sequence

V

1st

2nd

3rd

1st

3rd

2nd

1st

2nd

CC(min)

(1)

1st

2nd

Sequencingnot

required

Sequencingnot

V

(1)

CCQ(min)

required

(1)

2nd

1st

V

2nd

1st

PEN(min)

Note:

1.

Power supplies connected or sequenced together.

Device inputs must not be driven until all supply voltages reach their minimum range.

RP# should be low during power transitions.

5.3.2

Power Supply Decoupling

When the device is enabled, many internal conditions change. Circuits are energized,

charge pumps are switched on, and internal voltage nodes are ramped. All of this

internal activities produce transient signals. The magnitude of the transient signals

depends on the device and system loading. To minimize the effect of these transient

signals, a 0.1 µF ceramic capacitor is required across each VCC/VSS and VCCQ signal.

Capacitors should be placed as close as possible to device connections.

Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be

placed between VCC and VSS at the power supply connection. This 4.7 µF capacitor

should help overcome voltage slumps caused by PCB trace inductance.

5.4

Reset

By holding the flash device in reset during power-up and power-down transitions,

invalid bus conditions may be masked. The flash device enters reset mode when RP# is

driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-

impedance state. After return from reset, a certain amount of time is required before

the flash device is able to perform normal operations. After return from reset, the flash

device defaults to asynchronous page mode. If RP# is driven low during a program or

erase operation, the program or erase operation will be aborted and the memory

contents at the aborted block or address are no longer valid. See Figure 12, “AC

Waveform for Reset Operation” on page 28 for detailed information regarding reset

timings.

Datasheet

20

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

6.0

Electrical Characteristics

6.1

DC Current Specifications

Table 7:

DC Current Characteristics

V

2.7 - 3.6V

CCQ

V

Test Conditions

Notes

CC

Symbol

Parameter

Typ

Max Unit

V

= V Max; V

= V

Max

CC

IN

CC

CCQ

I

Input and V

Load Current

—

±1

µA

1

LI

PEN

= V

or V

CCQ

SS

V

= V Max; V

= V

CC

IN

CC

CCQ

I

Output Leakage Current

—

±10

LO

= V

or V

CCQ

SS

CMOS Inputs, V = V Max; Vccq =

CC

VccqMax

Device is disabled (see Table 17, “Chip

Enable Truth Table for 32-, 64-,

128-Mb” on page 30),

50

120

µA

RP# = V

± 0.2 V

CCQ

I

V

Standby Current

1,2,3

CCS

CC

TTL Inputs, V = V Max,

Vccq = VccqMax

CC

0.71

50

2

mA

Device is disabled (see Table 17, “Chip

Enable Truth Table for 32-, 64-,

128-Mb” on page 30), RP# = V

IH

I

Power-Down Current

120

µA

RP# = V ± 0.2 V, I

(STS) = 0 mA

—

CCD

SS

OUT

CMOS Inputs, V = V Max, V

= V

CCQ

CC

CCQ

Max using standard 8 word page mode

reads.

10

30

15

54

mA

Device is enabled (see Table 17, “Chip

Enable Truth Table for 32-, 64-,

128-Mb” on page 30)

I

CCR

V

CC

Page

Mode

Read

Current

f = 5 MHz, I

= 0 mA

OUT

8-Word Page

1,3

CMOS Inputs,V = V Max, V

= V

CCQ

CC

CCQ

Max using standard 8 word page mode

reads.

Device is enabled (see Table 17, “Chip

Enable Truth Table for 32-, 64-,

128-Mb” on page 30)

f = 33 MHz, I

= 0 mA

OUT

35

40

35

40

60

70

80

mA

CMOS Inputs, V

= V

PEN

CC

I

V

Program or Set Lock-Bit Current

1,4

1,5

CCW

CC

TTL Inputs, V

= V

PEN

CC

CMOS Inputs, V

TTL Inputs, V

= V

PEN

CC

Block Erase or Clear Block Lock-Bits

Current

I

CCE

= V

PEN

CC

Device is enabled (see Table 17, “Chip

I

V

Program Suspend or Block Erase

CC

CCWS

CCES

—

10

mA Enable Truth Table for 32-, 64-,

128-Mb” on page 30)

Suspend Current

Notes:

1.

All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).

Contact Numonyx or your local sales office for information about typical specifications.

Includes STS.

2.

3.

4.

5.

CMOS inputs are either V ± 0.2 V or V ± 0.2 V. TTL inputs are either V or V .

CC

SS

IL

IH

Sampled, not 100% tested.

I

and I

are specified with the device selected. If the device is read or written while in erase suspend mode, the

CCWS

CCES

device’s current draw is I

and I

.

CCWS

CCR

May 2009

208032-01

Datasheet

21

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

6.2

DC Voltage specifications

Table 8:

DC Voltage Characteristics

V

2.7 - 3.6 V

CCQ

V

Test Conditions

Notes

CC

Symbol

Parameter

Min

Max

Unit

V

Input Low Voltage

Input High Voltage

–0.5

2.0

0.8

V

—

2, 5, 6

IL

V

+ 0.5

IH

CCQ

V

= V Min

CC

—

0.4

V

= V

Min

CCQ

I

= 2 mA

OL

V

Output Low Voltage

Output High Voltage

1, 2

OL

V

= V Min

CC

0.2

—

= V

CCQ

I

= 100 µA

OL

V

= V

CC

CCMIN

0.85 × V

= V

CCQ

I

= –2.5 mA

OH

V

1, 2

2, 3

OH

V

= V

CC

CCMIN

V

– 0.2

—

V

= V

Min

CCQ

I

= –100 µA

OH

V

Lockout during Program,

PEN

V

—

2.2

—

PENLK

Erase and Lock-Bit Operations

V

during Block Erase, Program,

PEN

V

2.7

—

3.6

2.0

V

—

3

4

PENH

or Lock-Bit Operations

V

CC

Lockout Voltage

LKO

Notes:

1.

2.

3.

Includes STS.

Sampled, not 100% tested.

Block erases, programming, and lock-bit configurations are inhibited when V

≤ V

, and not guaranteed in the

PEN

PENLK

range between V

(max) and V

(min), and above V

(max).

PENLK

PENH

4.

Block erases, programming, and lock-bit configurations are inhibited when V < V

, and not guaranteed in the range

CC

LKO

between V

(min) and V (min), and above V (max).

LKO

CC CC

5.

6.

Includes all operational modes of the device.

Input/Output signals can undershoot to -1.0V referenced to V and can overshoot to V

+ 1.0V for duration of 2ns or

CCQ

SS

less, the V

valid range is referenced to V

.

CCQ

SS

6.3

Capacitance

Table 9:

Capacitance

1

2

Symbol

Parameter

Type

Max

Unit

Condition

C

Input Capacitance

Output Capacitance

V

= 0.0 V

6

4

7

5

pF

IN

C

V

OUT

Notes:

1.

2.

Sampled, not 100% tested.

= -40 °C to +85 °C, V = V = 0 to 3.6 V.

CCQ

T

A

CC

Datasheet

22

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

7.0

AC Characteristics

Timing symbols used in the timing diagrams within this document conform to the

following convention.

Figure 7: Timing Signal Naming Convention

E L Q V

t

Source Signal

Source State

Target State

Target Signal

Table 10: Timing Signal Name Decoder

Signal

Code

State

Code

Address

A

Q

D

E

High

H

L

Data - Read

Data - Write

Low

High-Z

Low-Z

Valid

Z

X

V

I

Chip Enable (CE)

Output Enable (OE#)

Write Enable (WE#)

Status (STS)

G

W

R

P

Invalid

Reset (RP#)

Byte Enable (BYTE#)

F

Erase/Program/Block Lock

V

Enable (V

)

PEN

Note:

Exceptions to this convention include t_ACCand t_APA. t_ACCis a generic timing symbol that

refers to the aggregate initial-access delay as determined by tAVQV, t_ELQV, and t_GLQV

(whichever is satisfied last) of the flash device. t_APAis specified in the flash device’s

data sheet, and is the address-to-data delay for subsequent page-mode reads.

7.1

Read Specifications

Table 11: Read Operations (Sheet 1 of 2)

(3)

Asynchronous Specifications V

Parameter

= 2.7 V–3.6 V

and V

= 2.7 V–3.6 V

Max

CC

CCQ

#

Sym

Density

Min

Unit

Notes

32 Mbit

64 Mbit

128 Mbit

75

—

1,2

R1

t

Read/Write Cycle Time

ns

AVAV

May 2009

208032-01

Datasheet

23

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 11: Read Operations (Sheet 2 of 2)

(3)

Asynchronous Specifications V

Parameter

= 2.7 V–3.6 V

and V

= 2.7 V–3.6 V

Max

CC

CCQ

#

Sym

Density

Min

Unit

Notes

32 Mbit

64 Mbit

128 Mbit

32 Mbit

64 Mbit

128 Mbit

All

—

0

75

25

150

180

210

—

1,2

R2

t

Address to Output Delay

CEX to Output Delay

ns

AVQV

1,2

R3

ELQV

ns

1,2

R4

R5

t

OE# to Non-Array Output Delay

RP# High to Output Delay

1,2,4

1,2

GLQV

PHQV

32 Mbit

64 Mbit

128 Mbit

1,2

R6

R7

R8

R9

t

CEX to Output in Low Z

ns

1,2,5

ELQX

GLQX

EHQZ

GHQZ

OE# to Output in Low Z

0

—

CEX High to Output in High Z

OE# High to Output in High Z

—

25

15

Output Hold from Address, CEX, or OE#

Change, Whichever Occurs First

R10

t

0

—

ns

1,2,5

OH

All

R11

R12

R13

R14

R15

R16

t

CEX Low to BYTE# High or Low

BYTE# to Output Delay

—

0

10

1

ns

µs

ns

1,2,5

1,2

ELFL/ ELFH

t

FLQV/ FHQV

BYTE# to Output in High Z

CEx High to CEx Low

1

1,2,5

5, 6

FLQZ

EHEL

APA

—

25

Page Address Access Time

OE# to Array Output Delay

—

1,2,4

GLQV

Notes:

1.

CE low is defined as the combination of pins CE0, CE1 and CE2 that enable the device. CE high is defined as the

X X

combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-

, 64-, 128-Mb” on page 30).

2.

3.

See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.

OE# may be delayed up to t

-t

after the falling edge of CE (see note 1 and Table 17, “Chip Enable Truth

ELQV GLQV

X

Table for 32-, 64-, 128-Mb” on page 30) without impact on t

.

4.

See Figure 13, “AC Input/Output Reference Waveform” o^En^LQp^Vage 29 and Figure 14, “Transient

Equivalent Testing Load Circuit” on page 29 for testing characteristics.

Sampled, not 100% tested.

5.

6.

For devices configured to standard word/byte read mode, R15 (t

) will equal R2 (t

).

APA

AVQV

Datasheet

24

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Figure 8: Single-Word Asynchronous Read Waveform

R1

R2

Address [A]

R8

R3

CEx [E]

R9

R4

OE# [G]

WE# [W]

R7

R10

R6

DQ[15:0] [Q]

R13

R11

R5

R12

BYTE# [F]

RP# [P]

Notes:

1.

CE low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CE high is defined as the

X X

combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-

, 64-, 128-Mb” on page 30).

2.

When reading the flash array a faster t

(R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,

GLQV

query reads, or device identifier reads).

Figure 9: 8-Word Asynchronous Page Mode Read

R1

R2

A[MAX:4] [A]

000

R3

001

110

111

A[3:1] [A]

CEx [E]

OE# [G]

R4

R8

WE# [W]

R7

R10

R15

R10

R6

R9

1

2

7

8

DQ[15:0] [Q]

RP# [P]

R5

BYTE# [F]

Notes:

1.

CE low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CE high is defined as the

X X

combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32-

, 64-, 128-Mb” on page 30).

2.

In this diagram, BYTE# is asserted high.

May 2009

208032-01

Datasheet

25

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 12: Write Operations

Valid for All

Speeds

#

Symbol

Parameter

Density

Unit

Notes

Min

Max

32 Mbit

64 Mbit

128 Mbit

150

180

210

0

—

500

W1

t

(t

)

RP# High Recovery to WE# (CE ) Going Low

1,2,3,4

PHWL PHEL

X

W2

W3

t

(t

)

CE (WE#) Low to WE# (CE ) Going Low

1,2,3,5

1,2,3,6

1,2,3

ELWL

WLEL

X

t

Write Pulse Width

60

50

55

0

WP

W4

t

(t

)

Data Setup to WE# (CE ) Going High

X

DVWH DVEH

W5

t

(t

Address Setup to WE# (CE ) Going High

X

AVWH AVEH

W6

t

(t

)

CE (WE#) Hold from WE# (CE ) High

X X

WHEH EHWH

ns

W7

t

(t

Data Hold from WE# (CE ) High

0

1,2,3

WHDX

EHDX

X

All

W8

t

(t

)

Address Hold from WE# (CE ) High

X

0

1,2,3

WHAX EHAX

W9

t

Write Pulse Width High

30

0

1,2,3,7

1,2,3,4

1,2,3,8

1,2,3,9

WPH

W11

W12

W13

t

(t

)

V

Setup to WE# (CE ) Going High

PEN X

VPWH

VPEH

t

(t

Write Recovery before Read

WE# (CE ) High to STS Going Low

35

—

WHGL EHGL

t

(t

)

WHRL EHRL

X

1,2,3,4,

9,10

W15

t

V

Hold from Valid SRD, STS Going High

PEN

0

—

QVVL

Notes:

1.

CE low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CE high is defined as the

X X

combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for

32-, 64-, 128-Mb” on page 30).

2.

Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during

read-only operations. Refer to AC Characteristics–Read-Only Operations.

3.

4.

5.

A write operation can be initiated and terminated with either CE or WE#.

X

Sampled, not 100% tested.

Write pulse width (t ) is defined from CE or WE# going low (whichever goes low last) to CE or WE# going high

WP

X

(whichever goes high first). Hence, t

= t

.

WP

WLWH

ELEH

WLEH

ELWH

6.

7.

Refer to Table 18, “Enhanced Configuration Register” on page 32 for valid A and D for block erase,

IN IN

program, or lock-bit configuration.

Write pulse width high (t

) is defined from CE or WE# going high (whichever goes high first) to CE or WE# going

WPH

X

low (whichever goes low first). Hence, t

= t

.

WPH

WHWL

WHGL

EHEL

WHEL

EHWL

8.

9.

10.

For array access, t

is required in addition to t

for any accesses after a write.

AVQV

STS timings are based on STS configured in its RY/BY# default mode.

V

should be held at V

until determination of block erase, program, or lock-bit configuration success (SR[5:3,1] =

PEN

PENH

0).

Datasheet

26

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Figure 10: Asynchronous Write Waveform

W5

W8

W6

Address [A]

CEx (WE#) [E (W)]

W2

W3

W9

WE# (CEx) [W (E)]

OE# [G]

W4

W7

D

DATA [D/Q]

W13

STS [R]

RP# [P]

W1

W11

VPEN [V]

Figure 11: Asynchronous Write to Read Waveform

W5

W8

Address [A]

W6

CEx [E]

W2

W3

WE# [W]

W12

OE# [G]

W4

W7

D

DATA [D/Q]

W1

RP# [P]

W11

VPEN [V]

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

7.2

Program, Erase, Block-Lock Specifications

Table 13: Configuration Performance

(8)

#

Symbol

Parameter

Typ

Max

Unit

Notes

Aligned 16 Words / 32 Bytes

Aligned 256 Words

128

TBD

654

µs

us

1,2,3,4,5,6,7

t

WHQV7

EHQV7

W16

Buffer Program Time

Block Program Time

t

TBD

175

Byte Program Time (Using Word/Byte

Program Command

40

µs

1,2,3,4

t

WHQV3

EHQV3

W16

Aligned 16 Words / 32 Bytes

Aligned 256 Words

0.53

TBD

2.4

sec

1,2,3,4

TBD

t

WHQV4

EHQV4

W16

Block Erase Time

1.0

50

4.0

60

sec

µs

1,2,3,4

1,2,3,4,9

1,2,3,9

t

WHQV5

Set Lock-Bit Time

t

EHQV5

WHQV6

Clear Block Lock-Bits Time

0.5

15

0.70

20

sec

µs

t

EHQV6

WHRH1

Program Suspend Latency Time to Read

t

EHRH1

t

WHRH

EHRH

W16

W17

Erase Suspend Latency Time to Read

STS Pulse Width Low Time

15

20

—

µs

ns

1,2,3,9

1

t

500

STS

Notes:

1.

Typical values measured at T = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change

A

based on device characterization.

2.

3.

4.

5.

6.

7.

8.

9.

These performance numbers are valid for all speed versions.

Sampled but not 100% tested.

Excludes system-level overhead.

These values are valid when the buffer is full, and the start address is aligned.

Effective per-byte program time (t

Effective per-word program time (t

, t

) is 4µs/byte (256-Byte buffer, typical).

) is 8µs/word (256-Word buffer, typical).

WHQV1 EHQV1

, t

WHQV2 EHQV2

Max values are measured at worst case temperature, data pattern and V corner after 100k cycles (except as noted).

Max values are expressed at +25 °C or -40 °C.

CC

7.3

Reset Specifications

Figure 12: AC Waveform for Reset Operation

STS (R)

P1

P2

RP# (P)

P3

Vcc

Note: STS is shown in its default mode (RY/BY#).

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Table 14: Reset Specifications

#

Symbol

Parameter

Min

Max

Unit

Notes

RP# is asserted during block erase,

program or lock-bit configuration

operation

RP# Pulse Low Time

25

—

µs

1

(If RP# is tied to V , this

CC

P1

t

PLPH

specification is not

applicable)

RP# is asserted during read

100

—

100

—

ns

µs

1

RP# High to Reset during Block Erase, Program, or Lock-Bit

Configuration

P2

P3

t

1,2

—

PHRH

t

Vcc Power Valid to RP# de-assertion (high)

60

VCCPH

Notes:

1.

2.

These specifications are valid for all product versions (packages and speeds).

A reset time, t , is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.

PHQV

7.4

AC Test Conditions

Figure 13: AC Input/Output Reference Waveform

V_CCQ

Input V_CCQ/2

0.0

Test Points

V_CCQ/2 Output

Note: AC test inputs are driven at V

for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at

CCQ

V

/2 V (50% of V

). Input rise and fall times (10% to 90%) < 5 ns.

CCQ

Figure 14: Transient Equivalent Testing Load Circuit

Device

Under Test

Out

C_L

Note: C Includes Jig Capacitance

L

Table 15: Test Configuration

Test Configuration

C

(pF)

L

V

= V

CCQMIN

30

CCQ

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

8.0

Bus Interface

This section provides an overview of Bus operations. The on-chip Write State Machine

(WSM) manages all erase and program algorithms. The system CPU provides control of

all in-system read, write, and erase operations through the system bus. All bus cycles

to or from the flash memory conform to standard microprocessor bus cycles. Table 16

summarizes the necessary states of each control signal for different modes of

operations.

Table 16: Bus Operations

STS

(Default

Mode)

(1)

(2)

(3)

15:0

Mode

RP#

CE

OE#

WE#

V

DQ

Notes

x

PEN

Async., Status, Query and

Identifier Reads

V

Enabled

V

X

D

OUT

High Z

4,6

IH

IL

IH

Output Disable

Standby

V

Enabled

Disabled

X

V

X

High Z

—

IH

X

Reset/Power-down

Command Writes

Array Writes

V

X

—

IL

IH

V

Enabled

V

D

IN

6,7

5,8

IH

IL

V

X

V

IL

PENH

Notes:

1.

2.

3.

4.

5.

6.

See Table 17 for valid CE configurations.

x

OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.

DQ refers to DQ[7:0] when BYTE# is low and DQ[15:0] if BYTE# is high.

Refer to DC characteristics. When V_PEN≤ V

, memory contents can be read but not altered.

PENLK

X should be V or V for the control pins and V

or V

for V

. For outputs, X should be V or V

.

OH

IL

IH

PENLK

PENH

PEN

OL

In default mode, STS is V when the WSM is executing internal block erase, program, or a lock-bit configuration

OL

algorithm. It is V

(pulled up by an external pull up resistance ≈ 10k) when the WSM is not busy, in block erase suspend

OH

mode (with programming inactive), program suspend mode, or reset power-down mode.

See Section 11.0, “Device Command Codes” on page 47 for valid DIN (user commands) during a Write

operation.

7.

8.

Array writes are either program or erase operations.

Table 17: Chip Enable Truth Table for 32-, 64-, 128-Mb

CE2

CE1

CE0

DEVICE

V

Enabled

Disabled

Enabled

Disabled

IL

V

IL

IH

V

IL

IH

IL

V

IL

IH

V

IH

IL

V

IL

IH

V

IH

IL

V

IH

Note: For single-chip applications, CE2 and CE1 can be connected to VSS.

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

8.1

Bus Reads

Reading from flash memory outputs stored information to the processor or chipset, and

does not change any contents. Reading can be performed an unlimited number of

times. Besides array data, other types of data such as device information and device

status is available from the flash.

To perform a bus read operation, CEx (refer to Table 17 on page 30) and OE# must be

asserted. CEx is the device-select control; when active, it enables the flash memory

device. OE# is the data-output control; when active, the addressed flash memory data

is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See

Section 9.2, “Read Operations” on page 35.

8.1.1

Asynchronous Page Mode Read

Unlike backward devices, J3 65 nm SBC device provides Eight-Word Asynchronous Page

mode only. Array data can be sensed up to eight words (16 Bytes) at a time. This is the

default mode on power-up or reset.

On backward devices, the Set Enhanced Configuration Register command is used to

enable Eight-Word Page mode upon power-up or reset, however this has no effect on J3

65 nm SBC device anymore.

After the initial access delay, the first word out of the page buffer corresponds to the

initial address. Address bits A[3:1] determine which word is output from the page

buffer for a x16 bus width, and A[3:0] determine which byte is output from the page

buffer for a x8 bus width. Subsequent reads from the device come from the page

buffer. These reads are output on DQ[15:0] for a x16 bus width and DQ[7:0] for a x8

bus width after a minimum delay as long as A[3:0].

Data can be read from the page buffer multiple times, and in any order.If address bits

A[MAX:4] change at any time, or if CEx# is toggled, the device will sense and load new

data into the page buffer. Asynchronous Page mode is the default read mode on power-

up or reset.

To perform a Page mode read after any other operation, the Read Array command must

be issued to read from the flash array. Asynchronous Page mode reads are permitted in

all blocks and are used to access register information. During register access, only one

word is loaded into the page buffer.

8.1.1.1

Enhanced Configuration Register

The Enhanced Configuration Register (ECR) is a volatile storage register that when

addressed by the Set ECR command can select between Four-Word Page mode and

Eight-Word Page mode on backward devices, however this has no effect on J3 65 nm

SBC device anymore.

The ECR is volatile; all bits will be reset to default values when RP# is deasserted or

power is removed from the device. To modify ECR settings, use the Set ECR command.

The Set ECR command is written along with the configuration register value, which is

placed on the lower 16 bits of the address bus A[15:0]. This is followed by a second

write that confirms the operation and again presents the ECR data on the address bus.

After executing this command, the device returns to Read Array mode.

The ECR is shown in Table 18. 8-word page mode Command Bus-Cycle is captured in

Table 19 for backward compatibility reasons.

Note:

If the 8-word Asynchronous Page mode is used on J3 65 nm SBC, a Clear Status

Register command must be executed after issuing the Set ECR command.

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 18: Enhanced Configuration Register

Page

Length

Reserved

ECR

15

ECR

14

ECR

13

ECR

12

ECR

11

ECR

10

ECR

9

ECR

8

ECR

7

ECR

6

ECR

5

ECR

4

ECR

3

ECR

2

ECR

1

ECR

0

BITS

DESCRIPTION

NOTES

ECR[15:14]

ECR.13

RFU

All bits should be set to 0.

•

“1” = 8-Word Page mode for backward devices

“0” = 4-Word Page mode for backward devices

ECR[12:0]

RFU

Table 19: Asynchronous 8-Word Page Mode Command Bus-Cycle Definition for Backward

Devices

First Bus Cycle

Second Bus Cycle

Bus

Command

Cycles

Required

(1)

Oper

Addr

Data

Oper

Addr

Data

Set Enhanced Configuration

Register (Set ECR)

2

Write

ECD

0060h

Write

ECD

0004h

1. ECD = Enhanced Configuration Register Data

8.1.2

Output Disable

With CEx asserted, and OE# at a logic-high level (V_IH), the device outputs are disabled.

Output signals DQ[15:0] are placed in a high-impedance state.

8.2

Bus Writes

Writing or Programming to the device, is where the host writes information or data into

the flash device for non-volatile storage. When the flash device is programmed, ‘ones’

are changed to ‘zeros’. ‘Zeros’ cannot be programed back to ‘ones’. To do so, an erase

operation must be performed. Writing commands to the Command User Interface (CUI)

enables various modes of operation, including the following:

• Reading of array data

• Common Flash Interface (CFI) data

• Identifier codes, inspection, and clearing of the Status Register

• Block Erasure, Program, and Lock-bit Configuration (when V_PEN= V_PENH

)

Erasing is performed on a block basis – all flash cells within a block are erased together.

Any information or data previously stored in the block will be lost. Erasing is typically

done prior to programming. The Block Erase command requires appropriate command

data and an address within the block to be erased. The Byte/Word Program command

requires the command and address of the location to be written. Set Block Lock-Bit

commands require the command and block within the device to be locked. The Clear

Block Lock-Bits command requires the command and address within the device to be

cleared.

The CUI does not occupy an addressable memory location. It is written when the device

is enabled and WE# is active. The address and data needed to execute a command are

latched on the rising edge of WE# or CE_X(CE_Xlow is defined as the combination of pins

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

CE0, CE1, and CE2 that enable the device. CE_Xhigh is defined as the combination of

pins CE0, CE1, and CE2 that disable the device. See Table 17 on page 30). Standard

microprocessor write timings are used.

8.3

Standby

CE0, CE1, and CE2 can disable the device (see Table 17 on page 30) and place it in

standby mode. This manipulation of CEx substantially reduces device power

consumption. DQ[15:0] outputs are placed in a high-impedance state independent of

OE#. If deselected during block erase, program, or lock-bit configuration, the WSM

continues functioning, and consuming active power until the operation completes.

8.3.1

Reset/Power-Down

RP# at V_ILinitiates the reset/power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-

impedance state, and turns off numerous internal circuits. RP# must be held low for a

minimum of t_PLPH. Time t_PHQVis required after return from reset mode until initial

memory access outputs are valid. After this wake-up interval, normal operation is

restored. The CUI is reset to read array mode and Status Register is set to 0080h.

During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the

operation. In default mode, STS transitions low and remains low for a maximum time

of t_PLPH+ t_PHRHuntil the reset operation is complete. Memory contents being altered

are no longer valid; the data may be partially corrupted after a program or partially

altered after an erase or lock-bit configuration. Time t_PHWLis required after RP# goes to

logic-high (V_IH) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When

the system comes out of reset, it expects to read from the flash memory. Automated

flash memories provide status information when accessed during Block Erase, Program,

or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset,

proper initialization may not occur because the flash memory may be providing status

information instead of array data. Numonyx Flash memories allow proper initialization

following a system reset through the use of the RP# input. In this application, RP# is

controlled by the same RESET# signal that resets the system CPU.

8.4

Device Commands

When V_PEN≤ V_PENLK, only read operations from the Status Register, CFI, identifier

codes, or blocks are enabled. Placing V_PENHon V_PENadditionally enables block erase,

program, and lock-bit configuration operations. Device operations are selected by

writing specific commands to the Command User Interface (CUI). The CUI does not

occupy an addressable memory location. It is the mechanism through which the flash

device is controlled.

A command sequence is issued in two consecutive write cycles - a Setup command

followed by a Confirm command. However, some commands are single-cycle

commands consisting of a setup command only. Generally, commands that alter the

contents of the flash device, such as Program or Erase, require at least two write cycles

to guard against inadvertent changes to the flash device. Flash commands fall into two

categories: Basic Commands and Extended Commands. Basic commands are

recognized by all Numonyx Flash devices, and are used to perform common flash

operations such as selecting the read mode, programming the array, or erasing blocks.

Extended commands are product-dependant; they are used to perform additional

features such as software block locking. Section 11.0, “Device Command Codes” on

page 47 describes all applicable commands on J3 65 nm SBC device.

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

9.0

Flash Operations

This section describes the operational features of flash memory. Operations are

command-based, wherein command codes are first issued to the device, then the

device performs the desired operation. All command codes are issued to the device

using bus-write cycles (see Chapter 8.0, “Bus Interface”). A complete list of available

command codes can be found in Section 11.0, “Device Command Codes” on page 47.

9.1

Status Register

The Status Register (SR) is an 8-bit, read-only register that indicates device status and

operation errors. To read the Status Register, issue the Read Status Register command.

Subsequent reads output Status Register information on DQ[7:0], and 00h on

DQ[15:8].

SR status bits are set and cleared by the device. SR error bits are set by the device, but

must be cleared using the Clear Status Register command. Upon power-up or exit from

reset, the Status Register defaults to 80h. Page-mode reads are not supported in this

read mode. Status Register contents are latched on the falling edge of OE# or CE_X(CE_X

low is defined as the combination of pins CE0, CE1, and CE2 that enable the device.

CE_Xhigh is defined as the combination of pins CE0, CE1, and CE2 that disable the

device). OE# must toggle to V_IHor the device must be disabled before further reads to

update the Status Register latch. The Read Status Register command functions

independently of V_PENvoltage.

Table 20 shows Status Register bit definitions.

Table 20: Status Register Bit Definitions

Status Register (SR)

Default Value = 80h

Program/

Erase

Voltage

Error

Erase

Suspend

Status

Program

Suspend

Status

Ready

Status

Erase

Error

Program

Error

Block-Locked

Reserved

0

Error

7

6

5

4

3

2

1

Bit

Name

Ready Status

Description

0 = Device is busy; SR[6:0] are invalid (Not driven);

1 = Device is ready; SR[6:0] are valid.

7

6

5

0 = Erase suspend not in effect.

1 = Erase suspend in effect.

Erase Suspend Status

SR.5 SR.4

Erase Error

0

1

0

1

0

1

= Program or erase operation successful.

= Program error - operation aborted.

= Erase error - operation aborted.

Command

Sequence

Error

Program

Error

4

= Command sequence error - command aborted.

0 = Within acceptable limits during program or erase operation.

3

2

Program/Erase Voltage Error

Program Suspend Status

1 = Not within acceptable limits during program or erase operation - Operation

aborted.

0 = Program suspend not in effect.

1 = Program suspend in effect.

0 = Block NOT locked during program or erase - operation successful.

1 = Block locked during program or erase - operation aborted.

1

0

Block-Locked Error

Reserved

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

9.1.1

Clearing the Status Register

The Status Register (SR) contain Status and error bits which are set by the device. SR

status bits are cleared by the device, however SR error bits are cleared by issuing the

Clear SR command (see Table 21). Resetting the device also clears the SR.

Table 21: Clear Status Register Command Bus-Cycles

Setup Write Cycle

Command

Confirm Write Cycle

Address Bus Data Bus

Address Bus

Data Bus

0050h

Clear Status Register

Device Address

—

Issuing the Clear SR command places the device in Read SR mode.

Note:

Care should be taken to avoid SR ambiguity. If a command sequence error occurs while

in an Erase Suspend condition, the SR will indicate a Command Sequence error by

setting SR.4 and SR.5. When the erase operation is resumed (and finishes), any errors

that may have occurred during the erase operation will be masked by the Command

Sequence error. To avoid this situation, clear the Status Register prior to resuming a

suspended erase operation. The Clear SR command functions independent of the

voltage level on VPEN.

9.2

Read Operations

Four types of data can be read from the device: array data, device information, CFI

data, and device status. Upon power-up or return from reset, the device defaults to

Read Array mode. To change the device’s read mode, the appropriate command must

be issued to the device. Table 22 shows the command codes used to configure the

device for the desired read mode. The following sections describe each read mode.

Table 22: Read Mode Command Bus-Cycles

Setup Write Cycle

Address Bus Data Bus

Confirm Write Cycle

Address Bus Data Bus

Command

Read Array

Device Address

00FFh

0070h

0090h

0098h

—

Read Status Register

Read Device Information

CFI Query

—

9.2.1

Read Array

Upon power-up or return from reset, the device defaults to Read Array mode. Issuing

the Read Array command places the device in Read Array mode. Subsequent reads

output array data on DQ[15:0]. The device remains in Read Array mode until a

different read command is issued, or a program or erase operation is performed, in

which case, the read mode is automatically changed to Read Status.

To change the device to Read Array mode while it is programming or erasing, first issue

the Suspend command. After the operation has been suspended, issue the Read Array

command. When the program or erase operation is subsequently resumed, the device

will automatically revert back to Read Status mode.

Note:

Issuing the Read Array command to the device while it is actively programming or

erasing causes subsequent reads from the device to output invalid data. Valid array

data is output only after the program or erase operation has finished.

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

The Read Array command functions independent of the voltage level on VPEN.

9.2.2

Read Status Register

Issuing the Read Status Register command places the device in Read Status Register

mode. Subsequent reads output Status Register information on DQ[7:0], and 00h on

DQ[15:8]. The device remains in Read Status Register mode until a different read-

mode command is issued. Performing a program, erase, or block-lock operation also

changes the device’s read mode to Read Status Register mode.

The Status Register is updated on the falling edge of OE# or CEx, whichever occurs

last. Status Register contents are valid only when SR.7 = 1. When WSM is active, SR.7

indicates the WSM’s state and SR[6:0] are in high-Z state.

The Read Status Register command functions independent of the voltage level on

VPEN.

9.2.3

Read Device Information

Issuing the Read Device Information command places the device in Read Device

Information mode. Subsequent reads output device information on DQ[15:0].

The device remains in Read Device Information mode until a different read command is

issued. Also, performing a program, erase, or block-lock operation changes the device

to Read Status Register mode.

The Read Device Information command functions independent of the voltage level on

VPEN.

9.2.4

CFI Query

The CFI query table contains an assortment of flash product information such as block

size, density, allowable command sets, electrical specifications, and other product

information. The data contained in this table conforms to the CFI protocol.

Issuing the CFI Query command places the device in CFI Query mode. Subsequent

reads output CFI information on DQ[15:0]. The device remains in CFI Query mode until

a different read command is issued, or a program or erase operation is performed,

which changes the read mode to Read Status Register mode.

The CFI Query command functions independent of the voltage level on VPEN.

9.3

Programming Operations

All programming operations require the addressed block to be unlocked, and a valid

VPEN voltage applied throughout the programming operation. Otherwise, the

programming operation will abort, setting the appropriate Status Register error bit(s).

The following sections describe each programming method.

9.3.1

Single-Word/Byte Programming

Array programming is performed by first issuing the Single-Word/Byte Program

command. This is followed by writing the desired data at the desired array address. The

read mode of the device is automatically changed to Read Status Register mode, which

remains in effect until another read-mode command is issued.

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

During programming, STS and the Status Register indicate a busy status (SR.7 = 0).

Upon completion, STS and the Status Register indicate a ready status (SR.7 = 1). The

Status Register should be checked for any errors (SR.4), then cleared.

Note:

Issuing the Read Array command to the device while it is actively programming causes

subsequent reads from the device to output invalid data. Valid array data is output only

after the program operation has finished.

Standby power levels are not be realized until the programming operation has finished.

Also, asserting RP# aborts the programming operation, and array contents at the

addressed location are indeterminate. The addressed block should be erased, and the

data re-programmed. If a Single-Word/Byte program is attempted when the

corresponding block lock-bit is set, SR.1 and SR.4 will be set.

9.3.2

Buffered Programming

Buffered programming operations simultaneously program multiple words/bytes into

the flash memory array, significantly reducing effective word-write/byte-write times.

User-data is first written to a write buffer, then programmed into the flash memory

array in buffer-size increments. For additional details, see the flow chart of the

buffered-programming operation.

Note:

Optimal performance and power consumption is realized by aligning the start address

on 256-Word boundaries (i.e., A[8:0] = 000000000b). Crossing a 256-Word boundary

during a buffered programming operation can cause programming time to double.

To perform a buffered programming operation, first issue the Buffered Program setup

command at the desired starting address. The read mode of the device/addressed

partition is automatically changed to Read Status Register mode.

Polling SR.7 determines write-buffer availability (0 = not available, 1 = available). If

the write buffer is not available, re-issue the setup command and check SR.7; repeat

until SR.7 = 1.

Next, issue the word count at the desired starting address. The word count represents

the total number of words to be written into the write buffer, minus one. This value can

range from 00h (one) to a maximum of FFh (256). Exceeding the allowable range

causes an abort.

Note:

The maximum number of bytes in write buffer on CFI region (offset 2Ah, refer Table 41,

“Device Geometry Definition” on page 60) is set to 05h (32 bytes) for backward

compatible reasons. No software change is required on existing applications for both x8

and x16 mode. Applications can optimize the system performance using the maximum

of 256 buffer size, contact your sales representives for questions.

Following the word count, the write buffer is filled with user-data. Subsequent bus-

write cycles provide addresses and data, up to the word count. All user-data addresses

must lie between <starting address> and <starting address + word count>, otherwise

the WSM continues to run as normal but, user may advertently change the content in

unexpected address locations.

Note:

User-data is programmed into the flash array at the address issued when filling the

write buffer.

After all user-data is written into the write buffer, issue the confirm command. If a

command other than the confirm command is issued to the device, a command

sequence error occurs and the operation aborts.

After issuing the confirm command, write-buffer contents are programmed into the

flash memory array. The Status Register indicates a busy status (SR.7 = 0) during

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

array programming.Issuing the Read Array command to the device while it is actively

programming or erasing causes subsequent reads from the device to output invalid

data. Valid array data is output only after the program or erase operation has finished.

Upon completion of array programming, the Status Register indicates ready (SR.7 = 1).

A full Status Register check should be performed to check for any programming errors,

then cleared by using the Clear Status Register command.

Additional buffered programming operations can be initiated by issuing another setup

command, and repeating the buffered programming bus-cycle sequence. However, any

errors in the Status Register must first be cleared before another buffered

programming operation can be initiated.

9.4

Block Erase Operations

Erasing a block changes ‘zeros’ to ‘ones’. To change ones to zeros, a program operation

must be performed (See Section 9.3, “Programming Operations”). Erasing is performed

on a block basis - an entire block is erased each time an erase command sequence is

issued. Once a block is fully erased, all addressable locations within that block read as

logical ones (FFFFh for x16 mode, FFh for x8 mode). Only one block-erase operation

can occur at a time, and is not permitted during a program suspend.

To perform a block-erase operation, issue the Block Erase command sequence at the

desired block address. Table 23 shows the two-cycle Block Erase command sequence.

Table 23: Block-Erase Command Bus-Cycles

Setup Write Cycle

Address Bus Data Bus

Device Address 0020h

Confirm Write Cycle

Command

Address Bus

Data Bus

00D0h

Block Erase

Block Address

Note:

A block-erase operation requires the addressed block to be unlocked, and a valid

voltage applied to VPEN throughout the block-erase operation. Otherwise, the

operation will abort, setting the appropriate Status Register error bit(s).

The Erase Confirm command latches the address of the block to be erased. The

addressed block is preconditioned (programmed to all zeros), erased, and then verified.

The read mode of the device is automatically changed to Read Status Register mode,

and remains in effect until another read-mode command is issued.

During a block-erase operation, STS and the Status Register indicates a busy status

(SR.7 = 0). Upon completion, STS and the Status Register indicates a ready status

(SR7 = 1). The Status Register should be checked for any errors, then cleared. If any

errors did occur, subsequent erase commands to the device are ignored unless the

Status Register is cleared.

The only valid commands during a block erase operation are Read Array, Read Device

Information, CFI Query, and Erase Suspend. After the block-erase operation has

completed, any valid command can be issued.

Note:

Issuing the Read Array command to the device while it is actively erasing causes

subsequent reads from the device to output invalid data. Valid array data is output only

after the block-erase operation has finished.

Standby power levels are not be realized until the block-erase operation has finished.

Also, asserting RP# aborts the block-erase operation, and array contents at the

addressed location are indeterminate. The addressed block should be erased before

programming within the block is attempted.

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9.5

Suspend and Resume

An erase or programming operation can be suspended to perform other operations, and

then subsequently resumed. Table 24 shows the Suspend and Resume command bus-

cycles.

Note:

All erase and programming operations require the addressed block to remain unlocked

with a valid voltage applied to VPEN throughout the suspend operation. Otherwise, the

block-erase or programming operation will abort, setting the appropriate Status

Register error bit(s). Also, asserting RP# aborts suspended block-erase and

programming operations, rendering array contents at the addressed location(s)

indeterminate.

Table 24: Suspend and Resume Command Bus-Cycles

Setup Write Cycle

Command

Confirm Write Cycle

Address Bus Data Bus

Address Bus

Data Bus

Suspend

Resume

Device Address

00B0h

00D0h

—

To suspend an on-going erase or program operation, issue the Suspend command to

any device address. The program or erase operation suspends at pre-determined points

during the operation after a delay of t_SUSP. Suspend is achieved whenSTS (in RY/BY#

mode) goes high, SR[7,6] = 1 (erase-suspend) or SR[7,2] = 1 (program-suspend).

Note:

Issuing the Suspend command does not change the read mode of the device. The

device will be in Read Status Register mode from when the erase or program command

was first issued, unless the read mode was changed prior to issuing the Suspend

command.

Not all commands are allowed when the device is suspended. Table 25 shows which

device commands are allowed during Program Suspend or Erase Suspend.

Table 25: Valid Commands During Suspend

Device Command

Program Suspend

Erase Suspend

STS Configuration

Read Array

Allowed

Read Status Register

Clear Status Register

Read Device Information

CFI Query

Allowed

Word/Byte Program

Buffered Program

Block Erase

Not Allowed

Allowed

Not Allowed

Allowed

Program Suspend

Erase Suspend

Not Allowed

Allowed

Program/Erase Resume

Lock Block

Not Allowed

Unlock Block

Program OTP Register

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

During Suspend, array-read operations are not allowed in blocks being erased or

programmed.

A block-erase under program-suspend is not allowed. However, word-program under

erase-suspend is allowed, and can be suspended. This results in a simultaneous erase-

suspend/ program-suspend condition, indicated by SR[7,6,2] = 1.

To resume a suspended program or erase operation, issue the Resume command to

any device address. The read mode of the device is automatically changed to Read

Status Register. The operation continues where it left off, STS (in RY/BY# mode) goes

low, and the respective Status Register bits are cleared.

When the Resume command is issued during a simultaneous erase-suspend/ program-

suspend condition, the programming operation is resumed first. Upon completion of the

programming operation, the Status Register should be checked for any errors, and

cleared. The resume command must be issued again to complete the erase operation.

Upon completion of the erase operation, the Status Register should be checked for any

errors, and cleared.

9.6

Status Signal

The STATUS (STS) signal can be configured to different states using the STS

Configuration command (Table 26). Once the STS signal has been configured, it

remains in that configuration until another Configuration command is issued or RP# is

asserted low. Initially, the STS signal defaults to RY/BY# operation where RY/BY# low

indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready

for a new operation or suspended. Table 27 displays possible STS configurations.

Table 26: STS Configuration Register Command Bus-Cycles

Setup Write Cycle

Command

Confirm Write Cycle

Address Bus

Data Bus

Address Bus

Device Address

Data Bus

STS Configuration

Device Address

00B8h

Register Data

To reconfigure the STATUS (STS) signal to other modes, the Configuration command is

given followed by the desired configuration code. The three alternate configurations are

all pulse mode for use as a system interrupt as described in the following paragraphs.

For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1

controls Program Complete interrupt pulse. Supplying the 00h configuration code with

the Configuration command resets the STS signal to the default RY/BY# level mode.

The Configuration command may only be given when the device is not busy or

suspended. Check SR.7 for device status. An invalid configuration code will result in

SR.4 and SR.5 being set.

Note:

STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands.

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Table 27: STS Configuration Register and Coding Definitions

D7

D6

D5

D4

D3

D2

D1

D0

Pulse on

Program

Complete

Pulse on

Erase

Complete

3

Reserved

1

2

D[1:0] = STS Configuration Codes

Notes

00 = default, level mode;

device ready indication

Controls HOLD to a memory controller to prevent accessing a flash memory

subsystem while any flash device's WSM is busy.

Generates a system interrupt pulse when any flash device in an array has

completed a block erase. Helpful for reformatting blocks after file system free

space reclamation or “cleanup.”

01 = pulse on Erase Complete

10 = pulse on Program Complete

Not supported on this device.

Generates system interrupts to trigger servicing of flash arrays when either

erase or program operations are completed, when a common interrupt service

routine is desired.

11 = pulse on Erase or Program Complete

Notes:

1.

2.

3.

When configured in one of the pulse modes, STS pulses low with a typical pulse width of 500 ns.

An invalid configuration code will result in both SR.4 and SR.5 being set.

Reserved bits are invalid should be ignored.

9.7

Security and Protection

J3 65 nm SBC device offers both hardware and software security features. Block lock

operations, PRs and VPEN allow users to implement various levels of data protection.

9.7.1

Normal Block Locking

J3 65 nm SBC has the capability of Flexible Block Locking (locked blocks remain locked

upon reset or power cycle): All blocks within the device are in unlocked state when ship

from Numonyx. Blocks can be locked individually by issuing the Set Block Lock Bit

command sequence to any address within a block. Once locked, blocks remain locked

when power is removed, or when the device is reset.

All locked blocks are unlocked simultaneously by issuing the Clear Block Lock Bits

command sequence to any device address. Locked blocks cannot be erased or

programmed. Table 28 summarizes the command bus-cycles.

Table 28: Block Locking Command Bus-Cycles

Setup Write Cycle

Confirm Write Cycle

Command

Address Bus

Data Bus

Address Bus

Data Bus

Set Block Lock Bit

Clear Block Lock Bits

Block Address

Device Address

0060h

Block Address

Device Address

0001h

00D0h

After issuing the Set Block Lock Bit setup command or Clear Block Lock Bits setup

command, the device’s read mode is automatically changed to Read Status Register

mode. After issuing the confirm command, completion of the operation is indicated by

STS (in RY/BY# mode) going high and SR.7 = 1.

Blocks cannot be locked or unlocked while programming or erasing, or while the device

is suspended. Reliable block lock and unlock operations occur only when V_CCand V_PEN

are valid. When V_PEN≤ V_PENLK, block lock-bits cannot be changed.

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

When the set lock-bit operation is complete, SR.4 should be checked for any error.

When the clear lock-bit operation is complete, SR.5 should be checked for any error.

Errors bits must be cleared using the Clear Status Register command.

Block lock-bit status can be determined by first issuing the Read Device Information

command, and then reading from <block base address> + 02h. DQ0 indicates the lock

status of the addressed block (0 = unlocked, 1 = locked).

9.7.2

9.7.3

Configurable Block Locking

One of the features on the J3 65 nm SBC is the ability to protect and/or secure the

user’s system by offering user configurable block locking solution: Non-Volatile

Temporary, Non-Volatile Semi-Permanently or Non-Volatile Permanently. For additional

information and collateral, please contact the sales representative.

Password Access

Password Access is a security enhancement offered on the J3 65 nm SBC device. This

feature protects information stored in main-array memory blocks by preventing content

alteration or reads, until a valid 64-bit password is received. Password Access may be

combined with Non-Volatile Protection and/or Volatile Protection to create a multi-

tiered solution.

Please contact your Numonyx Sales for further details concerning Password Access.

9.7.4

128-bit Protection Register

J3 65 nm SBC includes a 128-bit Protection Register (PR) that can be used to increase

the security of a system design. For example, the number contained in the PR can be

used to “match” the flash component with other system components such as the CPU

or ASIC, hence preventing device substitution.

The 128-bits of the PR are divided into two 64-bit segments:

• One segment is programmed at the Numonyx factory with a unique unalterable 64-

bit number.

• The other segment is left blank for customer designers to program as desired. Once

the customer segment is programmed, it can be locked to prevent further

programming.

9.7.5

9.7.6

Reading the 128-bit Protection Register

The Protection Register is read in Identification Read mode. The device is switched to

this mode by issuing the Read Identifier command (0090h). Once in this mode, read

cycles from addresses shown in Table 31, “Word-Wide Protection Register Addressing”

or Table 32, “Byte-Wide Protection Register Addressing” retrieve the specified

information. To return to Read Array mode, write the Read Array command (00FFh).

Programming the 128-bit Protection Register

PR bits are programmed using the two-cycle Program OTP Register command. The 64-

bit number is programmed 16 bits at a time for word-wide configuration and eight bits

at a time for byte-wide configuration. First write the Protection Program Setup

command, 00C0h. The next write to the device will latch in address and data and

program the specified location. The allowable addresses are shown in Table 31, “Word-

Wide Protection Register Addressing” on page 44 or Table 32, “Byte-Wide Protection

Register Addressing” on page 44. See Figure 24, “Protection Register Programming

Flowchart” on page 56. Any attempt to address Program OTP Register command

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

outside the defined PR address space will result in a Status Register error (SR.4 will be

set). Attempting to program a locked PR segment will result in a Status Register error

(SR.4 and SR.1 will be set).

Table 29: Programming the 128-bit Protection Register Command Bus-Cycles

First Bus Cycle

Second Bus Cycle

Command

Address Bus

Device Address

Data Bus

Address Bus

Register Offset

Data Bus

Program OTP Register

00C0h

Register Data

9.7.7

Locking the 128-bit Protection Register

The user-programmable segment of the PR is lockable by programming Bit 1 of the

Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to 0 at the

Numonyx factory to protect the unique device number. Bit 1 is set using the Protection

Program command to program “0xFFFD” to the PLR. After these bits have been

programmed, no further changes can be made to the values stored in the Protection

Register. Protection Program commands to a locked section will result in a Status

Register error (SR.4 and SR.1 will be set). The PR lockout state is not reversible.

Table 30: Programming Protection Lock Register Command Bus-Cycles

First Bus Cycle

Second Bus Cycle

Command

Address Bus

Device Address

Data Bus

Address Bus

Data Bus

Program OTP Register

00C0h

80h

FFFDh

Figure 15: 128-bit Protection Register Memory Map

128-Mbit: A[23:1]

64-Mbit: A[22:1]

32-Mbit: A[21:1]

Word Address

128-Bit Protection Register

0x88

0x87

0x86

0x85

0x84

64- bit Segment

( User- Programmable)

0x83

0x82

0x81

64- bit Segment

( Factory- Programmed)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0x80

Protection Lock Register

Note: A0 is not used in x16 mode when accessing the protection register map. See Table 31 for x16 addressing. In x8 mode

A0 is used, see Table 32 for x8 addressing.

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 31: Word-Wide Protection Register Addressing

Word

Use

A8

A7

A6

A5

A4

A3

A2

A1

LOCK

Both

Factory

User

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

User

Note: All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.)

Table 32: Byte-Wide Protection Register Addressing

Byte

Use

A8

A7

A6

A5

A4

A3

A2

A1

A0

LOCK

Both

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LOCK

0

Factory

User

1

2

3

4

5

6

7

8

9

User

A

User

B

User

C

User

D

E

User

F

User

Note: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A[MAX:9] = 0.

9.7.8

VPEN Protection

When it’s necessary to protect the entire array, global protection can be achieved using

a hardware mechanism using VPP or VPEN. Whenever a valid voltage is present on VPP

or VPEN, blocks within the main flash array can be erased or programmed. By

grounding VPP or VPEN, blocks within the main array cannot be altered – attempts to

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program or erase blocks will fail resulting in the setting of the appropriate error bit in

the Status Register. By holding VPP or VPEN low, absolute write protection of all blocks

in the array can be achieved.

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

10.0

ID Codes

Table 33: Read Identifier Codes

Code

Address

Data

32-Mbit

64-Mbit

128-Mbit

00001h

0016h

0017h

0018h

Device Code

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

11.0

Device Command Codes

For a complete definition on device operations refer to Section 8.4, “Device Commands”

on page 33. The list of all applicable commands are included here one more time for

the convenience.

Table 34: Command Bus Cycles and Command Codes

Setup Write Cycle

Confirm Write Cycle

Command

Address Bus

Data Bus

Address Bus

Data Bus

Program Enhanced Configuration Register

Program OTP Register

Register Data

Device Address

0060h

00C0h

0050h

00B8h

00FFh

0070h

0090h

0098h

Register Data

0004h

Register Offset

Register Data

Clear Status Register

—

Program STS Configuration Register

Read Array

Device Address

Register Data

—

Read Status Register

Read Identifier Codes (Read Device Information)

CFI Query

0040h/

0010h

Word/Byte Program

Device Address

Array Data

Buffered Program

Block Erase

Device Address

Block Address

Device Address

00E8h

0020h

00B0h

Device Address

Block Address

—

00D0h

—

Program/Erase Suspend

Program/Erase Resume

Set Block Lock Bit

Device Address

Block Address

00D0h

0060h

—

Block Address

0001h

Clear Block Lock Bits

Device Address

0060h

Device Address

00D0h

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

12.0

Flow Charts

Figure 16: Write to Buffer Flowchart

Start

Setup

- Write 0xE8

End

- Block Address

Full Status Register Check(if

Check Buffer Status

- Perform Read Operation

desired)

- Read Ready Status on signal SR.7

Yes

No

SR.7 = 1 ?

Yes

Word Count

- Address = block address

- Data = word count minus 1

(Valid range = 0x00 to 0xFF)

Read Status Register(SR)

Load Buffer

- Fill write buffer up to word count

- Address = within buffer range

- Data = User data

Confirm

- Write 0xD0

- Block address

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Figure 17: Status Register Flowchart

Start

Command Cycle

- Issue Status Register Command

- Address = any dev ice address

- Data = 0x70

Data Cycle

- Read Status Register SR[7:0]

No

SR7 = '1'

Yes

- Set/Reset

by WSM

Erase Suspend

See Suspend/Resume Flowchart

SR6 = '1'

No

Program Suspend

See Suspend/Resume Flowchart

SR2 = '1'

No

Yes

Error

Command Sequence

SR5 = '1'

SR4 = '1'

No

Error

Erase Failure

Yes

Error

Program Failure

SR4 = '1'

No

- Set by WSM

- Reset by user

- See Clear Status

Register

Yes

Error

_PEN< V_PENLK

SR3 = '1'

Command

V

No

Error

Block Locked

SR1 = '1'

No

End

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Figure 18: Byte/Word Program Flowchart

Start

Bus

Operation

Command

Comments

Setup Byte/

Data = 40H

Write 40H,

Address

Write

Word Program Addr = Location to Be Programmed

Byte/Word

Program

Data = Data to Be Programmed

Addr = Location to Be Programmed

Write Data and

Address

Read

(Note 1)

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status

Register

Standby

1. Toggling OE# (low to high to low) updates the status register. This

can be done in place of issuing the Read Status Register command.

Repeat for subsequent programming operations.

0

SR.7 =

1

SR full status check can be done after each program operation, or

after a sequence of programming operations.

Full Status

Write FFH after the last program operation to place device in read

array mode.

Check if Desired

Byte/Word

Program Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Command

Comments

Check SR.3

1 = Programming to Voltage Error

Detect

Read Status

Register Data

(See Above)

Standby

1

Check SR.1

SR.3 =

SR.1 =

SR.4 =

Voltage Range Error

1 = Device Protect Detect

RP# = V_IH, Block Lock-Bit Is Set

Only required for systems

implemeting lock-bit configuration.

Standby

0

1

Check SR.4

1 = Programming Error

Device Protect Error

Programming Error

Toggling OE# (low to high to low) updates the status register. This can

be done in place of issuing the Read Status Register command.

Repeat for subsequent programming operations.

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register

command in cases where multiple locations are programmed before

full status is checked.

Byte/Word

Program

Successful

If an error is detected, clear the status register before attempting retry

or other error recovery.

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Figure 19: Program Suspend/Resume Flowchart

Bus

Operation

Start

Command

Comments

Data = B0H

Program

Suspend

Write

Addr = X

Write B0H

Status Register Data

Addr = X

Read

Check SR.7

Standby

1 - WSM Ready

0 = WSM Busy

Read Status Register

Check SR.6

Standby

1 = Programming Suspended

0 = Programming Completed

0

SR.7 =

Write

1

Data = FFH

Addr = X

Read Array

Read array locations other

than that being programmed.

Read

0

SR.2 =

Programming Completed

Program

Resume

Data = D0H

Addr = X

Write

1

Write FFH

Read Data Array

No

Done Reading

Yes

Write D0H

Write FFH

Programming Resumed

Read Array Data

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Figure 20: Block Erase Flowchart

Bus

Operation

Command

Comments

Data = 20H

Start

Write

Erase Block

Addr = Block Address

Erase

Confirm

Data = D0H

Addr = Block Address

Write (Note 1)

Read

Issue Single Block Erase

Command 20H, Block

Address

Status register data

With the device enabled,

OE# low updates SR

Addr = X

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Write Confirm D0H

Block Address

1. The Erase Confirm byte must follow Erase Setup.

This device does not support erase queuing. Please see

Application note AP-646 For software erase queuing

compatibility.

Read

Status Register

Full status check can be done after all erase and write

sequences complete. Write FFH after the last operation to

reset the device to read array mode.

No

Suspend

Erase Loop

0

Yes

SR.7 =

1

Suspend Erase

Full Status

Check if Desired

Erase Flash

Block(s) Complete

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Figure 21: Block Erase Suspend/Resume Flowchart

Bus

Operation

Start

Command

Comments

Data = B0H

Write

Erase Suspend

Addr = X

Write B0H

Status Register Data

Addr = X

Read

Check SR.7

Standby

1 - WSM Ready

0 = WSM Busy

Read Status Register

Check SR.6

Standby

1 = Block Erase Suspended

0 = Block Erase Completed

0

SR.7 =

Write

1

Data = D0H

Addr = X

Erase Resume

0

SR.6 =

Block Erase Completed

1

Read

Program

Read or Program?

Read Array

Data

Program

Loop

No

Done?

Yes

Write D0H

Write FFH

Block Erase Resumed

Read Array Data

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Figure 22: Set Block Lock-Bit Flowchart

Start

Bus

Operation

Command

Comments

Set Block Lock-Bit Data = 60H

Write 60H,

Block Address

Write

Setup

Addr =Block Address

Set Block Lock-Bit Data = 01H

Write

Read

Confirm

Addr = Block Address

Write 01H,

Block Address

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

Standby

Repeat for subsequent lock-bit operations.

0

SR.7 =

1

Full status check can be done after each lock-bit set operation or after

a sequence of lock-bit set operations.

Write FFH after the last lock-bit set operation to place device in read

array mode.

Full Status

Check if Desired

Set Lock-Bit Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus

Operation

Command

Comments

Check SR.3

1 = Programming Voltage Error

Detect

1

Standby

SR.3 =

Voltage Range Error

Check SR.4, 5

Standby

Both 1 = Command Sequence

Error

0

SR.4,5 =

0

1

Command Sequence

Error

Check SR.4

1 = Set Lock-Bit Error

SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register

command, in cases where multiple lock-bits are set before full status is

checked.

SR.4 =

0

Set Lock-Bit Error

If an error is detected, clear the status register before attempting retry

or other error recovery.

Set Lock-Bit

Successful

Datasheet

54

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Figure 23: Clear Lock-Bit Flowchart

Start

Bus

Operation

Command

Comments

Data = 60H

Clear Block

Lock-Bits Setup

Write

Write 60H

Write D0H

Addr = X

Clear Block or

Lock-Bits Confirm

Data = D0H

Addr = X

Write

Read

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

Standby

Write FFH after the clear lock-bits operation to place device in read

array mode.

0

SR.7 =

1

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Command

Comments

Read Status Register

Data (See Above)

Check SR.3

Standby

1 = Programming Voltage Error

Detect

1

SR.3 =

0

Voltage Range Error

Check SR.4, 5

Both 1 = Command Sequence

Error

Standby

1

Check SR.5

1 = Clear Block Lock-Bits Error

Command Sequence

Error

SR.4,5 =

0

SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register

command.

Clear Block Lock-Bits

Error

SR.5 =

0

If an error is detected, clear the status register before attempting retry

or other error recovery.

Clear Block Lock-Bits

Successful

May 2009

208032-01

Datasheet

55

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Figure 24: Protection Register Programming Flowchart

Start

Bus Operation

Write

Command

Comments

Protection Program

Setup

Data = C0H

Write C0H

(Protection Reg.

Program Setup)

Data = Data to Program

Addr = Location to Program

Write

Protection Program

Status Register Data Toggle

CE# or OE# to Update Status

Register Data

Write Protect. Register

Address/Data

Read

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Protection Program operations can only be addressed within the protection

register address space. Addresses outside the defined space will return an

error.

No

SR.7 = 1?

Yes

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of

program operations.

Full Status

Check if Desired

Write FFH after the last program operation to reset device to read array mode.

Program Complete

FULL STATUS CHECK PROCEDURE

Bus Operation

Standby

Command

Comments

SR.1 SR.3 SR.4

Read Status Register

Data (See Above)

0

1

V_PENLow

1, 1

0

1

Prot. Reg.

Prog. Error

Standby

SR.3, SR.4 =

SR.1, SR.4 =

V_PENRange Error

1

0

1

Register

Locked:

Aborted

0,1

1,1

Standby

Protection Register

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Register -

Aborted

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases of multiple protection register program operations before full status is

checked.

SR.1, SR.4 =

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

Datasheet

56

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

13.0

Common Flash Interface

The (CFI) specification outlines device and host system software interrogation

handshake which allows specific vendor-specified software algorithms to be used for

entire families of devices. This allows device independent, JEDEC ID-independent, and

forward- and backward-compatible software support for the specified flash device

families. It allows flash vendors to standardize their existing interfaces for long-term

compatibility.

This section defines the data structure or “database” returned by the (CFI) Query

command. System software should parse this structure to gain critical information such

as block size, density, x8/x16, and electrical specifications. Once this information has

been obtained, the software will know which command sets to use to enable flash

writes, block erases, and otherwise control the flash component. The Query is part of

an overall specification for multiple command set and control interface descriptions

called CFI.

13.1

Query Structure Output

The Query “database” allows system software to gain information for controlling the

flash component. This section describes the device’s CFI-compliant interface that allows

the host system to access Query data.

Query data are always presented on the lowest-order data outputs (D[7:0]) only. The

numerical offset value is the address relative to the maximum bus width supported by

the device. On this family of devices, the Query table device starting address is a 10h,

which is a word address for x16 devices.

For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in

ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant

device outputs 00h data on upper bytes. Thus, the device outputs ASCII “Q” in the low

byte (D[7:0]) and 00h in the high byte (D[15:8]).

At Query addresses containing two or more bytes of information, the least significant

data byte is presented at the lower address, and the most significant data byte is

presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal

notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-

wide devices is always “00h,” the leading “00” has been dropped from the table

notation and only the lower byte value is shown. Any x16 device outputs can be

assumed to have 00h on the upper byte in this mode.

Table 35: Summary of Query Structure Output as a Function of Device and Mode

Query data with maximum device

Query data with byte addressing

bus width addressing

Device

Type/

Mode

Query start location in

maximum device bus

width addresses

Hex

Offset

ASCII

Value

Hex

Offset

ASCII

Value

Hex Code

x16 device

x16 mode

10h

10:

11:

12:

0051

0052

0059

“Q”

“R”

“Y”

20:

21:

22:

20:

51

00

52

51

“Q”

“Null”

“R”

x16 device

“Q”

May 2009

208032-01

Datasheet

57

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 35: Summary of Query Structure Output as a Function of Device and Mode

Query data with maximum device

Query data with byte addressing

bus width addressing

Device

Type/

Mode

Query start location in

maximum device bus

width addresses

Hex

ASCII

Value

Hex

Offset

ASCII

Value

Hex Code

Offset

(1)

x8 mode

N/A

21:

22:

51

52

“Q”

“R”

Note:

1.

The system must drive the lowest order addresses to access all the device's array data when the device is configured in

x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable"

for x8-configured devices.

Table 36: Example of Query Structure Output of a x16- and x8-Capable Device

Word Addressing

Hex Code

Byte Addressing

Hex Code

Offset

–A

Value

Offset

Value

A

D15–D

A –A

7

D –D

7 0

15

0

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

0051

0052

0059

“Q”

“R”

20h

21h

22h

23h

24h

25h

26h

27h

28h

...

51

“Q”

“Y”

52

“R”

P_ID

PrVendor

ID #

52

“R”

LO

P_ID

59

“Y”

HI

P

PrVendor

TblAdr

AltVendor

ID #

59

“Y”

LO

P

P_ID

PrVendor

ID #

...

HI

LO

A_ID

LO

A_ID

...

P_ID

...

HI

...

13.2

Query Structure Overview

The Query command causes the flash component to display the Common Flash

Interface (CFI) Query structure or “database.” The structure sub-sections and address

locations are summarized below. See AP-646 Common Flash Interface (CFI) and

Command Sets (order number 292204) for a full description of CFI.

The following sections describe the Query structure sub-sections in detail.

Table 37: Query Structure

Offset

Sub-Section Name

Description

Notes

00h

01h

Identification Code

Manufacturer Code

Device Code

1

Identification Code

(BA+2)h⁽²⁾

04-0Fh

10h

Block Status Register

Reserved

Block-Specific Information

1,2

1

Reserved for Vendor-Specific Information

Command Set ID and Vendor Data Offset

CFI Query Identification String

System Interface Information

1

1Bh

1

Datasheet

58

May 2009

208032-01

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 37: Query Structure

Offset

Sub-Section Name

Description

Flash Device Layout

Notes

27h

Device Geometry Definition

1

Primary Numonyx-Specific Extended

Query Table

Vendor-Defined Additional Information Specific to

the Primary Vendor Algorithm

(3)

P

1,3

Notes:

1.

Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2.

3.

BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is

128 KB).

Offset 15 defines “P” which points to the Primary Numonyx-Specific Extended Query Table.

13.3

Block Status Register

The Block Status Register indicates whether an erase operation completed successfully

or whether a given block is locked or can be accessed for flash program/erase

operations.

Table 38: Block Status Register

Offset

Length

Description

Address

Value

Block Lock Status Register

BA+2:

--00 or --01

BSR.0 Block Lock Status

0 = Unlocked

1 = Locked

(1)

(BA+2)h

1

BA+2:

(bit 0): 0 or 1

(bit 1–15): 0

BSR 1–15: Reserved for Future Use

Note:

1.

BA = The beginning location of a Block Address (i.e., 010000h is block 1’s (64-KW block) beginning location in word

mode).

13.4

CFI Query Identification String

The CFI Query Identification String provides verification that the component supports

the Common Flash Interface specification. It also indicates the specification version and

supported vendor-specified command set(s).

Table 39: CFI Identification

Hex

Code

Offset

Length

Description

Add.

Value

10

--51

--52

--59

--01

--00

--31

--00

“Q”

“R”

“Y”

10h

13h

15h

17h

19h

3

2

Query-unique ASCII string “QRY”

11:

12:

13:

14:

15:

16:

17:

18:

19:

1A:

Primary vendor command set and control interface ID code.

16-bit ID code for vendor-specified algorithms

Extended Query Table primary algorithm address

Alternate vendor command set and control interface ID code.

0000h means no second vendor-specified algorithm exists

Secondary algorithm Extended Query Table address.

0000h means none exists

May 2009

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Datasheet

59

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

13.5

System Interface Information

The following device information can optimize system interface software.

Table 40: System Interface Information

Hex

Code

Offset

Length

Description

Add.

Value

V

logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

CC

1Bh

1

1B:

--27

--36

--00

2.7 V

logic supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

CC

1Ch

1Dh

1Eh

1

1C:

1D:

1E:

3.6 V

0.0 V

[programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

PP

[programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

PP

--00

--06

1Fh

20h

21h

22h

23h

24h

25h

26h

1

“n” such that typical single word program time-out = 2ⁿµs

“n” such that typical max. buffer write time-out = 2ⁿµs

“n” such that typical block erase time-out = 2ⁿms

1F:

20:

21:

22:

23:

24:

25:

26:

64 µs

128 µs

1 s

1

--07

--0A

--00

--02

--03

--02

--00

“n” such that typical full chip erase time-out = 2ⁿms

NA

“n” such that maximum word program time-out = 2ⁿtimes typical

“n” such that maximum buffer write time-out = 2ⁿtimes typical

“n” such that maximum block erase time-out = 2ⁿtimes typical

“n” such that maximum chip erase time-out = 2ⁿtimes typical

256 µs

2048µs

4 s

NA

Notes:

1.

The value is 32 Bytes buffer write typical time out

13.6

Device Geometry Definition

This field provides critical details of the flash device geometry.

Table 41: Device Geometry Definition (Sheet 1 of 2)

Offset

Length

Description

Code See Table Below

27h

1

“n” such that device size = 2ⁿin number of bytes

27:

x8/

x16

28h

2

Flash device interface: x8 async x16 async x8/x16 async

28:

--02

--00

28:00,29:00 28:01,29:00 28:02,29:00

29:

2A:

2B:

1

2Ah

2

“n” such that maximum number of bytes in write buffer = 2ⁿ

--05

--00

32

Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions with one or more

contiguous same-size erase blocks

2Ch

1

2C:

--01

1

3. Symmetrically blocked partitions have one blocking region

4. Partition size = (total blocks) x (individual block size)

Datasheet

60

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 41: Device Geometry Definition (Sheet 2 of 2)

Offset

Length

Description

Erase Block Region 1 Information

Code See Table Below

2D:

2E:

2F:

30:

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

2Dh

4

Notes:

1.

Compatible with J3 130nm device (32 bytes). J3 65 nm SBC device supports up to maximum 256 words (x16 mode)/

256 bytes (x8 mode) buffer write.

Table 42: Device Geometry: Address Codes

Address

32 Mbit

64 Mbit

128 Mbit

27:

28:

29:

2A:

2B:

2C:

2D:

2E:

2F:

30:

--16

--02

--00

--05

--00

--01

--1F

--00

--02

--17

--02

--00

--05

--00

--01

--3F

--00

--02

--18

--02

--00

--05

--00

--01

--7F

--00

--02

13.7

Primary-Vendor Specific Extended Query Table

Certain flash features and commands are optional. The Primary Vendor-Specific

Extended Query table specifies this and other similar information.

Table 43: Primary Vendor-Specific Extended Query (Sheet 1 of 2)

(1)

Offset

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Add.

Value

P = 31h

(P+0)h

(P+1)h

(P+2)h

(P+3)h

(P+4)h

3

Primary extended query table

31:

32:

33:

34:

35:

--50

--52

--49

--31

“P”

“R”

“I”

Unique ASCII string “PRI”

1

Major version number, ASCII

Minor version number, ASCII

“1”

May 2009

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Datasheet

61

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 43: Primary Vendor-Specific Extended Query (Sheet 2 of 2)

(1)

Offset

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Add.

Value

P = 31h

4

36:

37:

38:

39:

--CE

--00

Optional feature and command support (1=yes, 0=no)

Undefined bits are “0.” If bit 31 is

“1” then another 31 bit field of optional features follows at

the end of the bit-30 field.

bit 0 Chip erase supported

bit 0 = 0

No

Yes

bit 1 Suspend erase supported

bit 1 = 1

bit 2 = 1

(P+5)h

(P+6)h

(P+7)h

(P+8)h

bit 2 Suspend program supported

bit 3 Legacy lock/unlock supported

bit 4 Queued erase supported

(1)

bit 3 = 1

bit 4 = 0

bit 5 = 0

bit 6 = 1

bit 7 = 1

bit 8 = 0

bit 9 = 0

Yes

No

Yes

No

bit 5 Instant Individual block locking supported

bit 6 Protection bits supported

bit 7 Page-mode read supported

bit 8 Synchronous read supported

bit9 Simultaneous Operation Supported

bit 30 CFI Link(s) to follow (32, 64, 128 Mb)

bit 31 Another “Optional Feature” field to follow

bit 30 = 0

bit 31 = 0

Supported functions after suspend: read Array, Status, Query

Other supported operations are:

bits 1–7 reserved; undefined bits are “0”

3A:

--01

(P+9)h

1

2

bit 0 Program supported after erase suspend

Block Status Register mask

bit 0 = 1

3B:

3C:

bit 0 = 1

bit 1 = 0

Yes

--01

--00

bits 2–15 are Reserved; undefined bits are “0”

bit 0 Block Lock-Bit Status register active

bit 1 Block Lock-Down Bit Status active

(P+A)h

(P+B)h

Yes

No

V

logic supply highest performance program/erase voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

CC

(P+C)h

(P+D)h

1

3D:

--33

--00

3.3 V

0.0 V

V

optimum program/erase supply voltage

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

PP

3E:

Note:

1.

2.

Future devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a value of “0.”

Setting this bit, will lead to the extension of the CFI table.

Datasheet

62

May 2009

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Table 44: Protection Register Information

(1)

Offset

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Add.

Value

P = 31h

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection bytes are available

(P+E)h

1

3F:

--01

01

Protection Field 1: Protection Description

This field describes user-available One Time Programmable (OTP)

protection register bytes. Some are pre-programmed with device-

unique serial numbers. Others are user-programmable. Bits 0-15 point

to the protection register lock byte, the section’s first byte. The

following bytes are factory pre-programmed and user-programmable.

40:

41:

42:

43:

--80

--00

--03

80h

00h

8bytes

(P+F)h

(P+10)h

(P+11)h

(P+12)h

4

bits 0-7 = Lock/bytes JEDEC-plane physical low address

bits 8-15 = Lock/bytes JEDEC-plane physical high address

n

bits 16-23 = “n” such that 2 = factory pre-programmed bytes

bits 24-31 = “n” such that 2 = user-programmable bytes

Note:

1.

The variable P is a pointer which is defined at CFI offset 15h.

Table 45: Burst Read Information

(1)

Offset

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Add.

Value

P = 31h

Page Mode Read capability

bits 0–7 = “n” such that 2ⁿHEX value represents the number of read-

page bytes. See offset 28h for device word width to determine page-

mode data output width. 00h indicates no read page buffer.

(P+13)h

1

44:

45:

--04

--00

16 byte

0

Number of synchronous mode read configuration fields that follow. 00h

indicates no burst capability.

(P+14)h

Synchronous Mode Read Capability Configuration 1

Bits 3-7 = Reserved

n+1

bits 0-2 = “n” such that 2

HEX value represents the maximum

number of continuous synchronous burst reads when the device is

configured for its maximum word width. A value of 07h indicates that

the device is capable of continuous linear bursts until that will output

data until the internal burst counter reaches the end of the device’s

burstable address space. This field’s 3-bit value can be written directly

to the Read Configuration Register Bits 0-2 if the device is configured for

its maximum word width. See offset 1Fh for word width to determine

the burst data output width.

(P+15)h

1

46:

--00

n/a

(P+16h)h

(P+45h)h

Note:

1

Synchronous Mode Read Capability Configuration 2

J3C mark for VIL fix for customers

47:

76:

--00

--01

n/a

01

1.

The variable P is a pointer which is defined at CFI offset 15h.

May 2009

208032-01

Datasheet

63

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Appendix A Additional Information

Order Number

Document/Tool

Numonyx™ Embedded Flash Memory (J3 v D); 28F256J3D, 28F128J3D, 28F640J3D,

28F320J3D Specification Update

316577

298136

292204

Numonyx™ Persistent Storage Manager (PSM) User’s Guide Software Manual

AP-646 Common Flash Interface (CFI) and Command Sets

Note: Contact your local Numonyx or distribution sales office or visit the Numonyx home page http://www.numonyx.com for

technical documentation, tools, or the most current information on Numonyx™ Embedded Flash Memory (J3 65 nm)

Single Bit per Cell (SBC) .

Datasheet

64

May 2009

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Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Appendix B Ordering Information

Figure 25: Decoder for 32-, 64-, 128-Mbit

l

P C2 8 F 3 2 0 J 3 F 7 5

Access Speed

75ns

Package

TE= 56-Lead TSOP

F = Numonyx^TM0.065

micron lithography

JS = Pb-Free 56-TSOP

RC = 64-Ball Easy BGA

PC= 64-Ball Pb-Free Easy BGA

Voltage (V_CC/V_PEN)

3 = 3 V/3 V

Product Line Designator

Product Family

J = Numonyx^TMEmbedded

Flash Memory

Device Density

128 = x8/x16 (128-Mbit )

640 = x8/x16 ( 64-Mbit )

320 = x8/x16 ( 32-Mbit )

Table 46: Valid Combinations

32-Mbit

64-Mbit

128-Mbit

TE28F320J3F75

JS28F320J3F75

RC28F320J3F75

PC28F320J3F75

TE28F640J3F75

JS28F640J3F75

RC28F640J3F75

PC28F640J3F75

TE28F128J3F75

JS28F128J3F75

RC28F128J3F75

PC28F128J3F75

May 2009

208032-01

Datasheet

65

Numonyx™ Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)

Datasheet

66

May 2009

208032-01


型号：	RC28F640J3F75
厂家：	NUMONYX B.V
描述：	Flash, 4MX16, 75ns, PBGA64, ESBGA-64 内存集成电路闪存
文件：	总66页 (文件大小：707K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RC28F640J3F75 [NUMONYX]

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