RC28F640P33TF60A [MICRON]
Numonyx® P33-65nm Flash Memory 128-Mbit, 64-Mbit Single Bit per Cell (SBC); Numonyx® P33-65nm快闪记忆体128兆， 64兆每单元单比特（ SBC ）
| 型号： | RC28F640P33TF60A |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | Numonyx® P33-65nm Flash Memory 128-Mbit, 64-Mbit Single Bit per Cell (SBC) |
| 文件： | 总88页 (文件大小：3952K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Numonyx P33-65nm Flash Memory
128-Mbit, 64-Mbit Single Bit per Cell (SBC)
Datasheet
Product Features
High performance:
Security:
— 60ns initial access time for Easy BGA
— 70ns initial access time for TSOP
— 25ns 8-word asynchronous-page read
mode
— 52MHz with zero wait states, 17ns clock-to-
data output synchronous-burst read mode
— 4-, 8-, 16-, and continuous-word options
for burst mode
— One-Time Programmable Registers:
— 64 OTP bits, programmed with unique
information by Numonyx
— 2112 OTP bits, available for customer
programming
— Absolute write protection: VPP = VSS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down capability
— Password Access feature
— 3.0V buffered programming at 1.8MByte/s
(Typ) using 256-word buffer
— Buffered Enhanced Factory Programming at
3.2MByte/s (typ) using 256-word buffer
Software:
— 20µs (Typ) program suspend
— 20µs (Typ) erase suspend
— Basic Command Set and Extended Function
Interface (EFI) Command Set compatible
Architecture:
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte main blocks
— Common Flash Interface capable
Density and Packaging:
— Blank Check to verify an erased block
— 56-Lead TSOP package (128-Mbit, 64-Mbit)
— 64-Ball Easy BGA package (128-Mbit, 64-
Mbit)
Voltage and Power:
— VCC (core) voltage: 2.3V – 3.6V
— VCCQ (I/O) voltage: 2.3V – 3.6V
— 16-bit wide data bus
— Standby current: 35μA(Typ) for 64-Mbit,
50μA(Typ) for 128-Mbit
Quality and Reliability:
— JESD47E Compliant
— Continuous synchronous read current:
23mA (Typ) at 52 MHz
— Operating temperature: –40°C to +85°C
— Minimum 100,000 erase cycles per block
— 65nm process technology
Datasheet
1
Jul 2011
Order Number: 208034-04
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and are trademarks or registered trademarks of Numonyx, B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2011, Numonyx, B.V., All Rights Reserved.
Datasheet
2
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Contents
1.0 Functional Description...............................................................................................5
1.1
1.2
1.3
Introduction .......................................................................................................5
Overview ...........................................................................................................5
Memory Maps .....................................................................................................6
2.0 Package Information.................................................................................................7
2.1
2.2
56-Lead TSOP.....................................................................................................7
64-Ball Easy BGA Package....................................................................................8
3.0 Ballouts................................................................................................................... 10
4.0 Signals .................................................................................................................... 12
5.0 Bus Operations........................................................................................................ 14
5.1
5.2
5.3
5.4
5.5
Read ............................................................................................................... 14
Write............................................................................................................... 14
Output Disable.................................................................................................. 15
Standby........................................................................................................... 15
Reset............................................................................................................... 15
6.0 Command Set .......................................................................................................... 16
6.1
6.2
Device Command Codes..................................................................................... 16
Device Command Bus Cycles .............................................................................. 18
7.0 Read Operation........................................................................................................ 20
7.1
7.2
7.3
7.4
Asynchronous Page-Mode Read........................................................................... 20
Synchronous Burst-Mode Read............................................................................ 20
Read Device Identifier........................................................................................ 21
Read CFI.......................................................................................................... 21
8.0 Program Operation.................................................................................................. 22
8.1
8.2
8.3
8.4
8.5
8.6
Word Programming ........................................................................................... 22
Buffered Programming....................................................................................... 22
Buffered Enhanced Factory Programming.............................................................. 23
Program Suspend.............................................................................................. 25
Program Resume............................................................................................... 26
Program Protection............................................................................................ 26
9.0 Erase Operation....................................................................................................... 27
9.1
9.2
9.3
9.4
9.5
Block Erase ...................................................................................................... 27
Blank Check ..................................................................................................... 27
Erase Suspend.................................................................................................. 28
Erase Resume................................................................................................... 28
Erase Protection................................................................................................ 28
10.0 Security................................................................................................................... 29
10.1 Block Locking.................................................................................................... 29
10.2 Selectable OTP Blocks........................................................................................ 31
10.3 Password Access ............................................................................................... 31
11.0 Status Register........................................................................................................ 32
11.1 Read Configuration Register................................................................................ 33
11.2 One-Time Programmable (OTP) Registers............................................................. 40
12.0 Power and Reset Specifications............................................................................... 43
12.1 Power-Up and Power-Down................................................................................. 43
12.2 Reset Specifications........................................................................................... 43
Datasheet
3
Jul 2011
Order Number: 208034-04
P33-65nm
12.3 Power Supply Decoupling....................................................................................44
13.0 Maximum Ratings and Operating Conditions ............................................................45
13.1 Absolute Maximum Ratings .................................................................................45
13.2 Operating Conditions..........................................................................................45
14.0 Electrical Specifications ...........................................................................................46
14.1 DC Current Characteristics..................................................................................46
14.2 DC Voltage Characteristics ..................................................................................47
15.0 AC Characteristics....................................................................................................48
15.1 AC Test Conditions.............................................................................................48
15.2 Capacitance ......................................................................................................49
15.3 AC Read Specifications .......................................................................................49
15.4 AC Write Specifications.......................................................................................54
15.5 Program and Erase Characteristics .......................................................................58
16.0 Ordering Information...............................................................................................59
A
Supplemental Reference Information.......................................................................60
A.1
A.2
A.3
Common Flash Interface.....................................................................................60
Flowcharts........................................................................................................72
Write State Machine...........................................................................................81
B
C
Conventions - Additional Documentation .................................................................85
B.1
B.2
Acronyms .........................................................................................................85
Definitions and Terms ........................................................................................85
Revision History.......................................................................................................87
Datasheet
4
Jul 2011
Order Number: 208034-04
P33-65nm SBC
1.0
Functional Description
1.1
Introduction
This document provides information about the Numonyx® P33-65nm Single
Bit per Cell (SBC) Flash Memory and describes its features, operations, and
specifications.
P33-65nm SBC device is offered in 64-Mbit and 128-Mbit densities. Benefits include
high-speed interface NOR device, and support for code and data storage. Features
include high-performance synchronous-burst read mode, a dramatical improvement in
buffer program time through larger buffer size, fast asynchronous access times, low
power, flexible security options, and two industry-standard package choices.
P33-65nm SBC device is manufactured using 65nm process technology.
1.2
Overview
This family of devices provides high performance at low voltage on a 16-bit data bus.
Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power-up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the RCR enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal.
A WAIT signal provides an easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast factory program and erase operations. The device features
a 256-word buffer to enable optimum programming performance, which can improve
system programming throughput time significantly to 1.8MByte/s.
The P33-65nm SBC device supports read operations with VCC at 3.0V, and erase and
program operations with VPP at 3.0V or 9.0V. Buffered Enhanced Factory Programming
provides the fastest flash array programming performance with VPP at 9.0V, which
increases factory throughput. With VPP at 3.0V, VCC and VPP can be tied together for a
simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP
connection provides complete data protection when VPP ≤ VPPLK
.
The Command User Interface is the interface between the system processor and all
internal operations of the device. An internal Write State Machine automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
The one-time-programmable (OTP) Register allows unique flash device identification
that can be used to increase system security. The individual Block Lock feature provides
zero-latency block locking and unlocking. The P33-65nm SBC device adds enhanced
protection via Password Access Mode which allows user to protect write and/or read
access to the defined blocks. In addition, the P33-65nm SBC device could also provide
the full-device OTP permanent lock feature.
Datasheet
5
Jul 2011
OrderNumber:208034-04
P33-65nm
1.3
Memory Maps
Figure 1: P33-65nm Memory Map (64-Mbit and 128-Mbit Densities)
A<23:1>128-Mbit
A<22:1> 64-Mbit
–
64- Kword Block 130
64- Kword Block 66
7F0000 7FFFFF
3F0000 – 3FFFFF
020000 – 02FFFF
010000 – 01FFFF
64- Kword Block
64- Kword Block
5
4
3
16- Kword Block
16- Kword Block
16- Kword Block
16- Kword Block
00C000– 00FFFF
008000 – 00BFFF
2
1
0
–
004000 007FFF
–
000000 003FFF
Bottom Boot
Word Wide (x16) Mode
A<23:1>128-Mbit
16- Kword Block
16- Kword Block
16- Kword Block
16- Kword Block
130
–
7FC000 7FFFFF
7F8000–7FBFFF
7F4000–7F7000
129
128
A<22:1> 64-Mbit
127
126
–
7F0000 7F3FFF
–
7E0000 7EFFFF
64- Kword Block
16- Kword Block
16- Kword Block
16- Kword Block
16- Kword Block
66
3FC000–3FFFFF
3F8000–3FBFFF
3F4000–3F7FFF
3F0000–3F3FFF
65
64
63
62
3E0000–3EFFFF
64- Kword Block
64- Kword Block
64- Kword Block
1
0
64- Kword Block
64- Kword Block
1
0
010000–01FFFF
000000–00FFFF
010000–01FFFF
000000–00FFFF
Top Boot
Word Wide (x16) Mode
Top Boot
Word Wide (x16) Mode
Datasheet
6
Jul 2011
Order Number: 208034-04
P33-65nm SBC
2.0
Package Information
2.1
56-Lead TSOP
Figure 2: TSOP Mechanical Specifications
Z
A
2
See Note 2
See Notes 1 and 3
Pin 1
e
See Detail B
E
Y
D
1
A
1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
0
b
L
Table 1:
TSOP Package Dimensions (Sheet 1 of 2)
Millimeters
Nom
Inches
Nom
Product Information
Symbol
Min
Max
Min
Max
Package Height
Standoff
A
A1
A2
b
-
-
1.200
-
-
-
0.047
-
0.050
0.965
0.170
0.100
18.200
13.800
-
-
0.002
0.038
0.0067
0.004
0.717
0.543
-
-
Package Body Thickness
Lead Width(4)
0.995
0.220
0.150
18.400
14.000
0.500
20.00
0.600
1.025
0.270
0.200
18.600
14.200
-
0.039
0.0087
0.006
0.724
0.551
0.0197
0.787
0.024
0.040
0.0106
0.008
0.732
0.559
-
Lead Thickness
Package Body Length
Package Body Width
Lead Pitch
C
D1
E
e
Terminal Dimension
Lead Tip Length
D
19.800
0.500
20.200
0.700
0.780
0.020
0.795
0.028
L
Datasheet
7
Jul 2011
OrderNumber:208034-04
P33-65nm
Table 1:
TSOP Package Dimensions (Sheet 2 of 2)
Millimeters
Inches
Nom
Product Information
Symbol
Min
Nom
Max
Min
Max
Lead Count
N
θ
-
0°
56
3°
-
-
0°
56
3°
-
Lead Tip Angle
5°
5°
Seating Plane Coplanarity
Lead to Package Offset
Notes:
Y
Z
-
-
0.100
0.350
-
-
0.004
0.014
0.150
0.250
0.006
0.010
1.
2.
3.
4.
One dimple on package denotes Pin 1.
If two dimples, then the larger dimple denotes Pin 1.
Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
For legacy lead width, 0.10mm(Min), 0.15mm(Typ) and 0.20mm(Max).
2.2
64-Ball Easy BGA Package
Figure 3: Easy BGA Mechanical Specifications (8x10x1.2 mm)
S1
Ball A1
Corner
Ball A1
Corner
D
1
2
3
4
5
6
7
8
8
7
5
4
3
2
1
6
S2
A
B
A
B
C
D
C
D
E
b
e
E
E
F
F
G
G
H
H
Top View - Ball side down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Note: Drawing not to scale
Datasheet
8
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 2:
Easy BGA Package Dimensions
Millimeters
Nom
Inches
Nom
Product Information
Symbol
Min
Max
Min
Max
Package Height
A
A1
A2
b
-
-
1.200
-
-
-
0.0472
-
Ball Height
0.250
-
-
0.0098
-
-
Package Body Thickness
Ball (Lead) Width
0.780
0.410
10.000
8.000
1.000
64
-
0.0307
0.0160
0.3937
0.3149
0.0394
64
-
0.310
9.900
7.900
-
0.510
10.100
8.100
-
0.0120
0.3898
0.3110
-
0.0200
0.3976
0.3189
-
Package Body Width
Package Body Length
Pitch
D
E
[e]
N
Ball (Lead) Count
-
-
-
-
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
Y
-
-
0.100
1.600
0.600
-
-
0.0039
0.0630
0.0236
S1
S2
1.400
0.400
1.500
0.500
0.0551
0.0157
0.0591
0.0197
Note: Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://
developer.numonyx.com/design/flash/packtech.
Datasheet
9
Jul 2011
OrderNumber:208034-04
P33-65nm
3.0
Ballouts
Figure 4: 56-Lead TSOP Pinout (64-Mbit and 128-Mbit Densities)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WAIT
A17
1
2
3
4
5
6
7
8
A16
A15
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
A14
A13
A12
A11
A10
A9
A23
A22
A21
VSS
NC
WE#
WP#
A20
A19
A18
A8
A7
A6
A5
A4
A3
A2
RFU
RFU
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RST#
VPP
56-Lead TSOP Pinout
14 mm x 20 mm
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#
VSS
Top View
CE#
A1
Notes:
1.
2.
3.
4.
5.
A1 is the least significant address bit.
A23 is valid for 128-Mbit densities; otherwise, it is a no connect (NC).
A22 is valid for 64-Mbit densities and above; otherwise, it is a no connect (NC).
No Internal Connection on VCC Pin 13; it may be driven or floated. For legacy designs, pin can be tied to Vcc.
One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the
product mark.
Datasheet
10
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 5: 64-Ball Easy BGA Ballout (64-Mbit and 128-Mbit Densities)
5
8
8
5
1
2
3
4
6
7
7
6
4
3
2
1
A
B
C
D
A
A1
A2
A3
A4
A6
A8
VPP A13 VCC A18 A22
A22 A18 VCC A13 VPP A8
RFU A19 RFU A14 CE# A9
A21 A20 WP# A15 A12 A10
A17 A16 VCCQ VCCQ RST# A11
A6
A1
B
C
VSS A9 CE# A14 RFU A19 RFU
VSS A2
A7
A10 A12 A15 WP# A20 A21
A7
A5
A3
A4
D
E
A5 A11 RST# VCCQ VCCQ A16 A17
E
F
DQ8 DQ1 DQ9 DQ3 DQ4 CLK DQ15 RFU
RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE#
A23 RFU DQ2 VCCQ DQ5 DQ6 DQ14 WE#
RFU DQ15 CLK DQ4 DQ3 DQ9 DQ1 DQ8
OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0 RFU
WE# DQ14 DQ6 DQ5 VCCQ DQ2 RFU A23
F
G
G
H
H
RFU VSS VCC VSS DQ13 VSS DQ7 RFU
RFU DQ7 VSS DQ13 VSS VCC VSS RFU
Easy BGA
Easy BGA
Top View- Ball side down
Bottom View- Ball side up
Notes:
1.
2.
3.
4.
A1 is the least significant address bit.
A23 is valid for 128-Mbit densities; otherwise, it is a no connect.
A22 is valid for 64-Mbit densities and above; otherwise, it is a no connect (NC).
One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the
product mark.
Datasheet
11
Jul 2011
OrderNumber:208034-04
P33-65nm
4.0
Signals
Table 3:
TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Name and Function
ADDRESS INPUTS: Device address inputs. 128-Mbit: A[23:1]; 64-Mbit: A[22:1].
A[MAX:1]
DQ[15:0]
Input
WARNING: The active address pins unused in design should not be left float. Please tie them to
VCCQ or VSS according to specific design requirements.
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
reads of memory, Status Register, OTP Register, and Read Configuration Register. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
Input/
Output
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
Input
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted,
flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
CE#
CLK
Input
Input
WARNING: All chip enables must be high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
OE#
Input
Input
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
RST#
WAIT: Indicates data valid in synchronous array or non-array burst reads. RCR.10, (WT) determines
its polarity when asserted. WAIT’s active output is VOL or VOH when CE# and OE# are VIL. WAIT is
high-Z if CE# or OE# is VIH
.
WAIT
Output
•
•
In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
In asynchronous page mode, and all write modes, WAIT is deasserted.
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE# or CE#, whichever occurs first.
WE#
WP#
Input
Input
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
WARNING: Designs not using WP# for protection could tie it to VCCQ or VSS without additional
capacitor.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP
voltages should not be attempted.
Set VPP = VPPL for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
Power/
Input
VPP
V
PPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCC
Power
VCCQ
VSS
Power
Power
OUTPUT POWER SUPPLY: Output-driver source voltage.
GROUND: Connect to system ground. Do not float any VSS connection.
Datasheet
12
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 3:
TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)
Symbol
Type
Name and Function
RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
enhancement. These should be treated in the same way as a Don’t Use (DU) signal.
RFU
—
DU
NC
—
—
DON’T USE: Do not connect to any other signal, or power supply; must be left floating.
NO CONNECT: No internal connection; can be driven or floated.
Datasheet
13
Jul 2011
OrderNumber:208034-04
P33-65nm
5.0
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#
and RST# must be VIH; CE# must be VIL).
Bus cycles to/from the P33-65nm SBC device conform to standard microprocessor bus
operations. Table 4, “Bus Operations Summary”summarizes the bus operations and the
logic levels that must be applied to the device control signal inputs.
Table 4:
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0] Notes
Asynchronous
Synchronous
VIH
X
L
L
L
H
Output
-
Deasserted
Driven
Read
Write
VIH
VIH
VIH
VIH
VIL
Running
L
L
L
L
L
H
H
X
X
H
L
Output
Input
-
X
X
X
X
High-Z
High-Z
High-Z
High-Z
1
2
Output Disable
Standby
Reset
X
X
X
L
H
X
X
High-Z
High-Z
High-Z
H
X
2
2,3,4
Notes:
1.
Refer to the Table 6, “Command Bus Cycles” on page 18 for valid DQ[15:0] during a write
operation.
2.
3.
4.
X = Don’t Care (H or L).
RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.
Recommend to set CE# and WE# to VIH on 65nm device during power-on/reset to avoid invalid commands
written into flash accidently.
5.1
5.2
Read
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 6, “Command Bus Cycles” on page 18
shows the bus cycle sequence for each of the supported device commands, while
Table 5, “Command Codes and Definitions” on page 16 describes each command. See
Section 15.0, “AC Characteristics” on page 48 for signal-timing details.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
Datasheet
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P33-65nm SBC
5.3
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
5.4
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
5.5
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
Numonyx allow proper CPU initialization following a system reset through the use of the
RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80. Asserting RST# de-energizes all internal
circuits, and places the output drivers in High-Z. When RST# is asserted, the device
shuts down the operation in progress, a process which takes a minimum amount of
time to complete. When RST# has been deasserted, the device is reset to
asynchronous Read Array state.
Note:
If RST# is asserted during a program or erase operation, the operation is terminated
and the memory contents at the aborted location (for a program) or block (for an
erase) are no longer valid, because the data may have been only partially written or
erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restored. See Section 15.0, “AC Characteristics” on page 48 for details
about signal-timing.
Datasheet
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P33-65nm
6.0
Command Set
6.1
Device Command Codes
The flash Command User Interface (CUI) provides access to device read, write, and
erase operations. The CUI does not occupy an addressable memory location; it is part
of the internal logic which allows the flash device to be controlled. The Write State
Machine provides the management for its internal erase and program algorithms.
Commands are written to the CUI to control flash device operations. Table 5,
“Command Codes and Definitions” describes all valid command codes.
For operations that involve multiple command cycles, the possibility exists that the
subsequent command does not get issued in the proper sequence. When this happens,
the CUI sets Status Register bits SR[5,4] to indicate a command sequence error.
Some applications use illegal or invalid commands (like 0x00) accidentally or
intentionally with the device. An illegal or invalid command doesn't change the device
output state compared with the previous operation on 130nm device. But the output
will change to Read Status Register mode on 65nm device.
After an illegal or invalid command, software may attempt to read the device. If the
previous state is read array mode before an illegal command, software will expect to
read array data on 130nm device, such as 0xFFFF in an unprogrammed location. On
the 65nm device, software may not get the expected array data and instead the status
register is read.
Please refer to the legal and valid commands/spec defined in the Datasheet, such as for
read mode, issue 0xFF to Read Array mode, 0x90 to Read Signature, 0x98 to Read CFI/
OTP array mode.
Table 5:
Command Codes and Definitions (Sheet 1 of 3)
Mode
Code
Device Mode
Read Array
Description
0xFF
Places the device in Read Array mode. Array data is output on DQ[15:0].
Read Status
Register
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. SR data is output on DQ[7:0].
0x70
0x90
Read Device ID
or Configuration
Register
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or OTP Register data on DQ[15:0].
Read
Places the device in Read Query mode. Subsequent reads output Common
Flash Interface information on DQ[7:0].
0x98
0x50
Read Query
Clear Status
Register
The WSM can only set SR error bits. The Clear Status Register command is
used to clear the SR error bits.
Datasheet
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Order Number: 208034-04
P33-65nm SBC
Table 5:
Command Codes and Definitions (Sheet 2 of 3)
Mode
Code
Device Mode
Description
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to
update the SR Data for synchronous Non-array reads. The Read Array
command must be issued to read array data after programming has finished.
Word Program
Setup
0x40
This command loads a variable number of words up to the buffer size of 256
words onto the program buffer.
0xE8
0xD0
Buffered Program
Write
The confirm command is issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
Buffered Program
Confirm
First cycle of a 2-cycle command; initiates the BEFP mode. The CUI then
waits for the BEFP Confirm command, 0xD0, that initiates the BEFP
algorithm. All other commands are ignored when BEFP mode begins.
0x80
0xD0
BEFP Setup
If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
BEFP Confirm
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command. If the next command is not the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR [5,4], and places the
device in Read Status Register mode.
0x20
0xD0
Block Erase Setup
Erase
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
erase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
SR Data for synchronous Non-array reads.
Block Erase Confirm
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR.2 (program
suspended) or SR 6 (erase suspended), along with SR.7 (ready). The WSM
remains in the suspend mode regardless of control signal states (except for
RST# asserted).
Program or Erase
Suspend
0xB0
Suspend
This command issued to any device address resumes the suspended program
or block-erase operation.
0xD0
0x60
Suspend Resume
Block lock Setup
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes. If the next command is not Block Lock (0x01), Block
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets SR.5 and SR.4,
indicating a command sequence error.
If the previous command was Block Lock Setup (0x60), the addressed block
is locked.
0x01
0xD0
0x2F
Block lock
If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
Protection
Unlock Block
Lock-Down Block
If the previous command was Block Lock Setup (0x60), the addressed block
is locked down.
First cycle of a 2-cycle command; prepares the device for a OTP Register or
Lock Register program operation. The second cycle latches the register
address and data, and starts the programming algorithm to program data
into the OTP array.
Protection program
setup
0xC0
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Table 5:
Command Codes and Definitions (Sheet 3 of 3)
Mode
Code
Device Mode
Description
First cycle of a 2-cycle command; prepares the CUI for device read
Read Configuration
Register Setup
configuration. If the Set Read Configuration Register command (0x03) is not
the next command, the CUI sets Status Register bits SR.5 and SR.4,
indicating a command sequence error.
0x60
Configuration
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[16:1]to the Read Configuration
Register. Following a Configure RCR command, subsequent read operations
access array data.
Read Configuration
Register
0x03
First cycle of a 2-cycle command; initiates the Blank Check operation on a
main block.
0xBC
0xD0
Blank Check
blank check
other
Blank Check
Confirm
Second cycle of blank check command sequence; it latches the block address
and executes blank check on the main array block.
This command is used in extended function interface. first cycle of a multiple-
cycle command second cycle is a Sub-Op-Code, the data written on third
cycle is one less than the word count; the allowable value on this cycle are 0
through 511. The subsequent cycles load data words into the program buffer
at a specified address until word count is achieved.
Extended Function
Interface
0xEB
6.2
Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the CUI. See
Table 6, “Command Bus Cycles” on page 18. Several commands are used to modify
array data including Word Program and Block Erase commands. Writing either
command to the CUI initiates a sequence of internally-timed functions that culminate in
the completion of the requested task. However, the operation can be aborted by either
asserting RST# or by issuing an appropriate suspend command.
Table 6:
Command Bus Cycles (Sheet 1 of 2)
First Bus Cycle
Second Bus Cycle
Bus
Mode
Command
Cycles
Oper
Addr(1)
Data(2)
Oper
Addr(1)
Data(2)
Read Array
1
Write
DnA
0xFF
0x90
-
-
-
Read Device
Identifier
≥ 2
Write
DnA
Read
DBA + IA
ID
Read
Read CFI
≥ 2
2
Write
Write
Write
Write
Write
DnA
DnA
DnA
WA
0x98
0x70
0x50
0x40
0xE8
Read
Read
-
DBA + CFI-A
CFI-D
SRD
-
Read Status Register
Clear Status Register
Word Program
DnA
-
1
2
Write
Write
WA
WA
WD
Buffered Program(3)
> 2
WA
N - 1
Program
Buffered Enhanced
Factory Program
(BEFP)(4)
> 2
Write
WA
0x80
Write
WA
0xD0
Erase
Block Erase
2
1
Write
Write
BA
0x20
0xB0
Write
-
BA
-
0xD0
-
Program/Erase
Suspend
DnA
Suspend
Program/Erase
Resume
1
Write
DnA
0xD0
-
-
-
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P33-65nm SBC
Table 6:
Command Bus Cycles (Sheet 2 of 2)
First Bus Cycle
Second Bus Cycle
Bus
Mode
Command
Cycles
Oper
Addr(1)
Data(2)
Oper
Addr(1)
Data(2)
Lock Block
2
2
2
Write
Write
Write
BA
BA
BA
0x60
0x60
0x60
Write
Write
Write
BA
BA
BA
0x01
0xD0
0x2F
Unlock Block
Lock-down Block
Protection
Program OTP
Register
2
2
Write
Write
PRA
LRA
0xC0
0xC0
Write
Write
OTP-RA
LRA
OTP-D
LRD
Program Lock
Register
Program Read
Configuration Configuration
2
Write
RCD
0x60
Write
RCD
0x03
D0
Register
Blank Check
2
Write
Write
BA
0xBC
0xEB
Write
Write
BA
Others
Extended Function
Interface(5)
Sub-Op
code
>2
WA
WA
Notes:
1.
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = OTP Register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[16:1].
ID = Identifier data.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = OTP Register data.
LRD = Lock Register data.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 256 words of data.Then the confirm command (0xD0) is issued, triggering the array programming
operation.
2.
3.
4.
5.
The confirm command (0xD0) is followed by the buffer data.
The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1≤ N ≤ 256. The subsequent cycles load data
words into the program buffer at a specified address until word count is achieved, after the data words are loaded, the
final cycle is the confirm cycle 0xD0).
Datasheet
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7.0
Read Operation
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read Query. Upon power-up, or after a reset, the device defaults to Read Array
mode. To change the read state, the appropriate read command must be written to the
device (see Section 6.2, “Device Command Bus Cycles” on page 18). The following
sections describe read-mode operations in detail.
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a
reset. The RCR must be configured to enable synchronous burst reads of the flash
memory array (see Section 11.1, “Read Configuration Register” on page 33).
7.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read
mode and the device is set to Read Array mode. However, to perform array reads after
any other device operation (e.g. write operation), the Read Array command must be
issued in order to read from the flash memory array.
To perform an asynchronous page-mode read, an address is driven onto the address
bus, and CE# and ADV# are asserted. WE# and RST# must already have been
deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven
high to latch the address, or it must be held low throughout the read cycle. CLK is not
used for asynchronous page-mode reads, and is ignored. If only asynchronous reads
are to be performed, CLK should be tied to a valid VIH or VILlevel, WAIT signal can be
floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an
initial access time tAVQV delay. (see Section 15.0, “AC Characteristics” on page 48).
In asynchronous page mode, eight data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after
the initial access delay. The lowest four address bits determine which word of the
16-word page is output from the data buffer at any given time.
7.2
Synchronous Burst-Mode Read
To perform a synchronous burst-read, an initial address is driven onto the address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can
remain asserted throughout the burst access, in which case the address is latched on
the next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay (see Section
11.1.2, “Latency Count (RCR[13:11])” on page 34). Subsequent data is output on valid
CLK edges following a minimum delay. However, for a synchronous non-array read, the
same word of data will be output on successive clock edges until the burst length
requirements are satisfied. Refer to the following waveforms for more detailed
information:
• Figure 20, “Synchronous Single-Word Array or Non-array Read Timing” on page 52
• Figure 21, “Continuous Burst Read, showing an Output Delay Timing” on page 53
• Figure 22, “Synchronous Burst-Mode Four-Word Read Timing” on page 53
Datasheet
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P33-65nm SBC
7.3
Read Device Identifier
The Read Device Identifier command instructs the device to output manufacturer code,
device identifier code, block-lock status, OTP Register data, or Read Configuration
Register data (see Section 6.2, “Device Command Bus Cycles” on page 18 for details on
issuing the Read Device Identifier command). Table 7, “Device Identifier Information”
on page 21 and Table 8, “Device ID codes” on page 21 show the address offsets and
data values for this device.
Table 7:
Device Identifier Information
Item
Address(1,2)
Data
Manufacturer Code
0x00
0x01
0x89h
ID (see Table 8
Lock Bit:
Device ID Code
)
Block Lock Configuration:
• Block Is Unlocked
DQ0 = 0b0
DQ0 = 0b1
DQ1 = 0b0
DQ1 = 0b1
RCR Contents
GPR data
• Block Is Locked
BBA + 0x02
• Block Is not Locked-Down
• Block Is Locked-Down
Read Configuration Register
General Purpose Register(3)
Lock Register 0
0x05
DBA + 0x07
0x80
PR-LK0
64-bit Factory-Programmed OTP Register
64-bit User-Programmable OTP Register
Lock Register 1
0x81–0x84
0x85–0x88
0x89
Numonyx Factory OTP Register data
User OTP Register data
OTP Register lock data
128-bit User-Programmable OTP Registers
0x8A–0x109
User OTP Register data
Notes:
1.
2.
3.
BBA = Block Base Address.
DBA = Device base Address, Numonyx reserves other configuration address locations.
In P33-65nm SBC, the GPR is used as read out register for Extended Function interface command.
Table 8:
Device ID codes
Device Identifier Codes
ID Code Type
Device Density
–T
–B
(Top Parameter)
(Bottom Parameter)
64-Mbit
881D
881E
8820
8821
Device Code
128-Mbit
7.4
Read CFI
The Read CFI command instructs the device to output Common Flash Interface data
when read. See Section 6.1, “Device Command Codes” on page 16 for detail on issuing
the CFI Query command. Section A.1, “Common Flash Interface” on page 60 shows CFI
information and address offsets within the CFI database.
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8.0
Program Operation
The device supports three programming methods: Word Programming (40h/10h),
Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h,
D0h). The following sections describe device programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be deasserted and the block must be unlocked before
attempting to program the block. Attempting to program a locked block causes a
program error (SR.4 and SR.1 set) and termination of the operation. See Section 10.0,
“Security” on page 29 for details on locking and unlocking blocks.
8.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup
command to the device. This is followed by a second write to the device with the
address and data to be programmed. The device outputs Status Register data when
read. See Figure 29, “Word Program Flowchart” on page 72. VPP must be above VPPLK
,
and within the specified VPPL Min/Max values.
During programming, the WSM executes a sequence of internally-timed events that
program the desired data bits at the addressed location, and verifies that the bits are
sufficiently programmed. Programming the flash memory array changes “ones” to
“zeros”. Memory array bits that are zeros can be changed to ones only by erasing the
block.
The Status Register can be examined for programming progress and errors by reading
at any address. The device remains in the Read Status Register state until another
command is written to the device.
Status Register bit SR.7 indicates the programming status while the sequence
executes. Commands that can be issued to the device during programming are
Program Suspend, Read Status Register, Read Device Identifier, Read CFI, and Read
Array (this returns unknown data).
When programming has finished, Status Register bit SR.4 (when set) indicates a
programming failure. If SR.3 is set, the WSM could not perform the word programming
operation because VPP was outside of its acceptable limits. If SR.1 is set, the word
programming operation attempted to program a locked block, causing the operation to
abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow,
when word programming has completed.
8.2
Buffered Programming
The device features a 256-word buffer to enable optimum programming performance.
For Buffered Programming, data is first written to an on-chip write buffer. Then the
buffer data is programmed into the flash memory array in buffer-size increments. This
can improve system programming performance significantly over non-buffered
programming. (see Figure 32, “Buffer Program Flowchart” on page 75).
When the Buffered Programming Setup command is issued, Status Register information
is updated and reflects the availability of the buffer. SR.7 indicates buffer availability: if
set, the buffer is available; if cleared, the buffer is not available.
Note:
The device defaults to output SR data after the Buffered Programming Setup Command
(E8h) is issued. CE# or OE# must be toggled to update Status Register. Don’t issue the
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P33-65nm SBC
Read SR command (70h), which would be interpreted by the internal state machines as
Buffer Word Count.
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 256-word boundary (A[8:1] = 0x00).
Note:
If a misaligned address range is issued during buffered programming, the program
region must also be within an 256-word aligned boundary.
After the last data is written to the buffer, the Buffered Programming Confirm command
must be issued to the original block address. The WSM begins to program buffer
contents to the flash memory array. If a command other than the Buffered
Programming Confirm command is written to the device, a command sequence error
occurs and SR[7,5,4] are set. If an error occurs while writing to the array, the device
stops programming, and SR[7,4] are set, indicating a programming failure.
When Buffered Programming has completed, additional buffer writes can be initiated by
issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with VPP = VPPL or VPPH
(See Section 13.2, “Operating Conditions” on page 45 for limitations when operating
the device with VPP = VPPH).
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and SR[5,4] are set.
If Buffered programming is attempted while VPP is below VPPLK, SR[4,3] are set. If any
errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
8.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up flash programming. The
enhanced programming algorithm used in BEFP eliminates traditional programming
elements that drive up overhead in device programmer systems. (see Figure 33, “BEFP
Flowchart” on page 76).
BEFP consists of three phases: Setup, Program/Verify, and Exit It uses a write buffer to
spread flash program performance across 256 data words. Verification occurs in the
same phase as programming to accurately program the flash memory cell to the
correct bit state.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 256 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR.0 indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 256-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
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P33-65nm
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
8.3.1
BEFP Requirements and Considerations
Table 9:
BEFP Requirements
Parameter/Issue
Requirement
Notes
Case Temperature
VCC
TC = 30
°
C ± 10°C
-
-
-
-
Nominal Vcc
VPP
Driven to VPPH
Setup and Confirm
Target block must be unlocked before issuing the BEFP Setup and Confirm commands.
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired.
Programming
-
Buffer Alignment
WA0 must align with the start of an array buffer boundary.
1
Note: Word buffer boundaries in the array are determined by A[8:1] (0x00 through 0xFF); the alignment start point is A[8:1] =
0x00.
Table 10: BEFP Considerations
Parameter/Issue
Cycling
Requirement
Notes
For optimum performance, cycling must be limited below 50 erase cycles per block.
BEFP programs one block at a time; all buffer data must fall within a single block.
BEFP cannot be suspended.
1
2
-
Programming blocks
Suspend
Programming the flash
memory array
Programming to the flash memory array can occur only when the buffer is full.
3
Notes:
1.
2.
3.
Some degradation in performance may occur is this limit is exceeded, but the internal algorithm continues to work
properly.
If the internal address counter increments beyond the block’s maximum address, addressing wraps around to the
beginning of the block.
If the number of words is less than 256, remaining locations must be filled with 0xFFFF.
8.3.2
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A
delay before checking SR.7 is required to allow the WSM enough time to perform all of
its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4
is set and BEFP operation terminates. If the block was found to be locked, SR.1 is also
set. SR.3 is set if the error occurred due to an incorrect VPP level.
Note:
Reading from the device after the BEFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be
interpreted as data to be loaded into the buffer.
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8.3.3
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR.7
cleared indicates the device is busy and the BEFP program/verify phase is activated.
SR.0 indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
the maximum buffer size of 256 words. During the buffer-loading sequence, data is
stored to sequential buffer locations starting at address 0x00. Programming of the
buffer contents to the flash memory array starts as soon as the buffer is full. If the
number of words is less than 256, the remaining buffer locations must be filled with
0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an
address outside of the current block's range during a buffer-fill sequence
causes the algorithm to exit immediately. Any data previously loaded into the
buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the BEFP
algorithm will be aborted and the program fails and (SR.4) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the
flash memory array; programming continues from where the previous buffer sequence
ended. The host programming system must poll SR.0 to determine when the buffer
program sequence completes. SR.0 cleared indicates that all buffer data has been
transferred to the flash array; SR.0 set indicates that the buffer is not available yet for
the next fill cycle. The host system may check full status for errors at any time, but it is
only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write
cycles should be issued to the device until SR.0 = 0 and the device is ready for the next
buffer fill.
Note:
Any spurious writes are ignored after a buffer fill operation and when internal program
is proceeding.
The host programming system continues the BEFP algorithm by providing the next
group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
8.3.4
8.4
BEFP Exit Phase
When SR.7 is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. When exiting the BEFP algorithm with a block address change, the read
mode will not change. After BEFP exit, any valid command can be issued to the device.
Program Suspend
Issuing the Program Suspend command while programming suspends the
programming operation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program operation can be suspended to perform reads only. Additionally, a
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program operation that is running during an erase suspend can be suspended to
perform a read operation (see Figure 30, “Program Suspend/Resume Flowchart” on
page 73).
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend
latency is specified in Section 15.5, “Program and Erase Characteristics” on page 58.
To read data from the device, the Read Array command must be issued. Read Array,
Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid
commands during a program suspend.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in program suspend. If RST# is asserted, the device is reset.
8.5
8.6
Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status Register bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted (see Figure 30, “Program Suspend/
Resume Flowchart” on page 73).
Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If
VPP is at or below VPPLK, programming operations halt and SR.3 is set indicating a VPP-
level error. Block Lock Registers are not affected by the voltage level on VPP; they may
still be programmed and read, even if VPP is less than VPPLK
.
Figure 6: Example VPP Supply Connections
VCC
VCC
VPP
VCC
VPP
VCC
VPP
PROT #
≤ 10K Ω
• Low-voltage Programming only
• Logic Control of Device Protection
• Factory Programming with VPP = VPPH
• Complete write/Erase Protection when VPP ≤ VPPLK
VCC
VCC
VCC
VCC
VPP
VPP=VPPH
VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable
• Low Voltage and Factory Programming
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9.0
Erase Operation
Flash erasing is performed on a block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
9.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the
address of the block to be erased (see Section 6.2, “Device Command Bus Cycles” on
page 18). Next, the Block Erase Confirm command is written to the address of the
block to be erased. If the device is placed in standby (CE# deasserted) during an erase
operation, the device completes the erase operation before entering standby. VPP must
be above VPPLK and the block must be unlocked (see Figure 34, “Block Erase Flowchart”
on page 77).
During a block erase, the WSM executes a sequence of internally-timed events that
conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros
only by programming the block.
The Status Register can be examined for block erase progress and errors by reading
any address. The device remains in the Read Status Register state until another
command is written. SR.0 indicates whether the addressed block is erasing. Status
Register bit SR.7 is set upon erase completion.
Status Register bit SR.7 indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR.5 indicates an erase
failure if set. SR.3 set would indicate that the WSM could not perform the erase
operation because VPP was outside of its acceptable limits. SR.1 set indicates that the
erase operation attempted to erase a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
The Block Erase operation is aborted by performing a reset or powering down the
device. In this case, data integrity cannot be ensured, and it is recommended to erase
again the blocks aborted.
9.2
Blank Check
The Blank Check operation determines whether a specified main block is blank (i.e.
completely erased). Without Blank Check, Block Erase would be the only other way to
ensure a block is completely erased. so Blank Check can be used to determine whether
or not a prior erase operation was successful; this includes erase operations that may
have been interrupted by power loss.
Blank check can apply to only one block at a time, and no operations other than Status
Register Reads are allowed during Blank Check (e.g. reading array data, program,
erase etc). Suspend and resume operations are not supported during Blank Check, nor
is Blank Check supported during any suspended operations.
Blank Check operations are initiated by writing the Blank Check Setup command to the
block address. Next, the Check Confirm command is issued along with the same block
address. When a successful command sequence is entered, the device automatically
enters the Read Status State. The WSM then reads the entire specified block, and
determines whether any bit in the block is programmed or over-erased.
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The Status Register can be examined for Blank Check progress and errors by reading
any address within the block being accessed. During a blank check operation, the
Status Register indicates a busy status (SR.7 = 0). Upon completion, the Status
Register indicates a ready status (SR.7 = 1). The Status Register should be checked for
any errors, and then cleared. If the Blank Check operation fails, which means the block
is not completely erased, the Status Register bit SR.5 will be set (“1”). CE# or OE#
toggle (during polling) updates the Status Register.
After examining the Status Register, it should be cleared by the Clear Status Register
command before issuing a new command. The device remains in Status Register Mode
until another command is written to the device. Any command can follow once the
Blank Check command is complete.
9.3
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address. A block
erase operation can be suspended to perform a word or buffer program operation, or a
read operation within any block except the block that is erase suspended (see
Figure 31, “Erase Suspend/Resume Flowchart” on page 74).
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The device
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in Section 15.5, “Program and Erase Characteristics” on page 58.
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Program command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, Read CFI, and Erase Resume are valid commands
during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,
Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at a valid level, and WP# must remain unchanged
while in erase suspend. If RST# is asserted, the device is reset.
9.4
9.5
Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears SR[7,6]. This command can be written to any address. If Status
Register error bits are set, the Status Register should be cleared before issuing the next
instruction. RST# must remain deasserted.
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If
VPP is at or below VPPLK, erase operations halt and SR.3 is set indicating a VPP-level
error.
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10.0
Security
The device features security modes used to protect the information stored in the flash
memory array. The following sections describe each security mode in detail.
10.1
Block Locking
Individual instant block locking is used to protect user code and/or data within the flash
memory array. All blocks power up in a locked state to protect array data from being
altered during power transitions. Any block can be locked or unlocked with no latency.
Locked blocks cannot be programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock
commands. Hardware-controlled security can be implemented using the Block Lock-
Down command along with asserting WP#. Also, VPP data security can be used to
inhibit program and erase operations (see Section 8.6, “Program Protection” on
page 26 and Section 9.5, “Erase Protection” on page 28).
The P33-65nm SBC device also offers four pre-defined areas in the main array that can
be configured as One-Time Programmable (OTP) for the highest level of security. These
include the four 32 KB parameter blocks together as one and the three adjacent 128 KB
main blocks. This is available for top or bottom parameter devices.
10.1.1
Lock Block
To lock a block, issue the Lock Block Setup command. The next command must be the
Lock Block command issued to the desired block’s address (see Section 6.2, “Device
Command Bus Cycles” on page 18 and Figure 35, “Block Lock Operations Flowchart” on
page 78). If the Set Read Configuration Register command is issued after the Block
Lock Setup command, the device configures the RCR instead.
Block lock and unlock operations are not affected by the voltage level on VPP. The block
lock bits may be modified and/or read even if VPP is at or below VPPLK
.
10.1.2
10.1.3
Unlock Block
The Unlock Block command is used to unlock blocks (see Section 6.2, “Device
Command Bus Cycles” on page 18). Unlocked blocks can be read, programmed, and
erased. Unlocked blocks return to a locked state when the device is reset or powered
down. If a block is in a lock-down state, WP# must be deasserted before it can be
unlocked (see Figure 7, “Block Locking State Diagram” on page 30).
Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock-Down Block
command sequence (see Section 6.2, “Device Command Bus Cycles” on page 18).
Blocks in a lock-down state cannot be programmed or erased; they can only be read.
However, unlike locked blocks, their locked state cannot be changed by software
commands alone. A locked-down block can only be unlocked by issuing the Unlock
Block command with WP# deasserted. To return an unlocked block to locked-down
state, a Lock-Down command must be issued prior to changing WP# to VIL. Locked-
down blocks revert to the locked state upon reset or power up the device (see Figure 7,
“Block Locking State Diagram” on page 30).
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10.1.4
Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 7.3, “Read Device Identifier” on page 21). Data bits DQ[1:0] display the
addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the
addressed block’s lock-down bit.
Figure 7: Block Locking State Diagram
P G M /E R A S E
A L L O W E D
P G M /E R A S E
P R E V E N T E D
L K /
D 0 h
L K /
0 1 h
[0 0 0 ]
[0 0 1 ]
P o w e r-U p /
R e s e t D e fa u lt
L K /
2 F h
W P # = V IL = 0
[0 1 1 ]
V irtu a l lo c k-
d o w n
[0 1 0 ]
L o c k e d -d o w n
A n y L o c k
c o m m a n d s
W P # to g g le
L K /
D 0 h
L K /
0 1 h o r 2 F h
L o c k e d -d o w n
is d is a b le d b y
W P # = V IH
[1 1 0 ]
[1 1 1 ]
W P # = V IH = 1
L K /
2 F h
L K /
2 F h
P o w e r-U p /
R e s e t D e fa u lt
L K /
D 0 h
L K /
0 1 h
[1 0 0 ]
[1 0 1 ]
Note: LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; LK/01h: Lock Command; LK/2Fh: Lock-Down Command.
10.1.5
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change
block locking during an erase operation, first issue the Erase Suspend command.
Monitor the Status Register until SR.7 and SR.6 are set, indicating the device is
suspended and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operation using the Erase Resume command.
Note:
A Lock Block Setup command followed by any command other than Lock Block, Unlock
Block, or Lock-Down Block produces a command sequence error and set Status
Register bits SR.4 and SR.5. If a command sequence error occurs during an erase
suspend, SR.4 and SR.5 remains set, even after the erase operation is resumed. Unless
the Status Register is cleared using the Clear Status Register command before
resuming the erase operation, possible erase errors may be masked by the command
sequence error.
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If a block is locked or locked-down during an erase suspend of the same block, the lock
status bits change immediately. However, the erase operation completes when it is
resumed. Block lock operations cannot occur during a program suspend. See Appendix
A, “Write State Machine” on page 81, which shows valid commands during an erase
suspend.
10.2
10.3
Selectable OTP Blocks
Blocks from the main array may be optionally configured as OTP. Ask your local
Numonyx representative for details about any of these selectable OTP implementations.
Password Access
Password Access is a security enhancement offered on the P33-65nm device. This
feature protects information stored in main-array memory blocks by preventing content
alteration or reads until a valid 64-bit password is received. Password Access may be
combined with Non-Volatile Protection and/or Volatile Protection to create a multi-
tiered solution. Please contact your Numonyx Sales for further details concerning
Password Access.
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11.0
Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Ready Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
Table 11: Status Register Description
Status Register (SR)
Default Value = 0x80
Erase
Suspend
Status
Program
Suspend
Status
Device Ready
Status
Erase/Blank
Check Status
Program
Status
Block-Locked
BEFP Write
Status
VPP Status
Status
1
DRS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
BWS
0
Bit
Name
Description
0 = Device is busy; program or erase cycle in progress; SR.0 valid.
1 = Device is ready; SR[6:1] are valid.
7
Device Ready Status
Erase Suspend Status
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
6
5
Erase/Blank
Check Status
SR.5
SR.4
Description
Command
Sequence
Error
0
0
1
1
0
1
0
1
Program or Erase operation successful.
Program error -operation aborted.
Erase or Blank Check error - operation aborted.
Command sequence error - command aborted.
Program
Status
4
0 = VPP within acceptable limits during program or erase operation.
1 = VPP < VPPLK during program or erase operation.
3
2
1
VPP Status
0 = Program suspend not in effect.
1 = Program suspend in effect.
Program Suspend Status
Block-Locked Status
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
2
0
BEFP Write Status
1 = BEFP in-progress.
1. Always clear the Status Register before resuming erase operations afer an Erase Suspend command; this prevents ambiguity in
Status Register information. For example, if a command sequence error occurs during an erase suspend state, the Status
Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible
errors during the erase operation cannot be deteted via the Stauts Register because it contains the previous error status.
2. BEFP mode is only valid in array.
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11.0.1
Clear Status Register
The Clear Status Register command clears the Status Register. It functions independent
of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.
11.1
Read Configuration Register
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see Section 6.2, “Device Command
Bus Cycles” on page 18).
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see Section 7.3, “Read Device Identifier” on page 21).
The RCR is shown in Table 12. The following sections describe each RCR bit.
Table 12: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Data
Output
Config
WAIT
Delay
Burst
Wrap
Read
Mode
WAIT
Burst
Seq
CLK
RES
Latency Count
LC[3:0]
RES RES
Burst Length
Polarity
Edge
RM
15
Bit
R
WP
10
DOC
9
WD
8
BS
7
CE
6
R
5
R
4
BW
3
BL[2:0]
1
14
13
12
11
2
0
Name
Description
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
15
Read Mode (RM)
Reserved (R)
14
Set to 0. This bit cannot be altered by customer.
000 =Code 0 reserved
001 =Code 1 reserved
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
13:11
Latency Count (LC[2:0])
WAIT Polarity (WP)
111 =Code 7(default)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
10
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
Data Output Configuration
(DOC)
9
8
7
6
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
WAIT Delay (WD)
Burst Sequence (BS)
0 =Reserved
1 =Linear (default)
Clock Edge (CE)
0 = Falling edge
1 = Rising edge (default)
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Table 12: Read Configuration Register Description (Sheet 2 of 2)
5:4
Reserved (R)
Set to 0. This bit cannot be altered by customer.
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
3
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
2:0
Burst Length (BL[2:0])
(Other bit settings are reserved)
11.1.1
Read Mode (RCR.15)
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
11.1.2
Latency Count (RCR[13:11])
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 8 shows the data output latency for the different
settings of LC. The maximum Latency Count for P33 would be Code 4 based on the Max
clock frequency specification of 52 MHz, and there will be zero WAIT States when
bursting within the word line. Please also refer to Section 11.1.3, “End of Word Line
(EOWL) Considerations” on page 36 for more information on EOWL.
Refer to Table 13, “LC and Frequency Support” on page 35 for Latency Code Settings.
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Figure 8: First-Access Latency Count
CLK [C]
Valid
Address
Address [A]
ADV# [V]
Code 0 (Reserved)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
Code 1
(Reserved
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 3
Code 4
Code 5
Code 6
Code 7
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Table 13: LC and Frequency Support
Latency Count Settings
Frequency Support (MHz)
3
4
≤ 40
≤ 52
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OrderNumber:208034-04
P33-65nm
Figure 9: Example Latency Count Setting Using Code 3
tData
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:1]
Code 3
High-Z
Data
D[15:0]
R103
11.1.3
End of Word Line (EOWL) Considerations
End of Wordline (EOWL) WAIT states can result when the starting address of the burst
operation is not aligned to an 8-word boundary; that is, A[3:1] of start address does
not equal 0x0. Figure 10, “End of Wordline Timing Diagram” on page 36 illustrates the
end of wordline WAIT state(s), which occur after the first 8-word boundary is reached.
The number of data words and the number of WAIT states is summarized in Table 14,
“End of Wordline Data and WAIT state Comparison” on page 37for both P33-130nm
and P33-65nm SBC devices.
Figure 10: End of Wordline Timing Diagram
Latency Count
CLK
A[Max:1]
DQ[15:0]
Address
Data
Data
Data
ADV#
OE#
WAIT
EOWL
Datasheet
36
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 14: End of Wordline Data and WAIT state Comparison
P33-130nm
P33-65nm
Latency Count
Data States
WAIT States
Data States
WAIT States
1
2
3
4
5
6
7
Not Supported
Not Supported
0 to 1
Not Supported
Not Supported
0 to 1
4
4
4
4
4
4
8
8
8
8
8
8
0 to 2
0 to 3
0 to 4
0 to 5
0 to 2
0 to 3
0 to 4
0 to 5
0 to 6
0 to 6
11.1.4
WAIT Polarity (RCR.10)
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
11.1.5
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read
status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid
on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word
read mode, and all write operations, WAIT is set to a deasserted state as determined
by RCR.10. See Figure 18, “Asynchronous Single-Word Read (ADV# Latch)” on
page 51, and Figure 19, “Asynchronous Page-Mode Read Timing” on page 52.
Datasheet
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Jul 2011
OrderNumber:208034-04
P33-65nm
Table 15: WAIT Functionality Table
Condition
WAIT
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
High-Z
Active
1
1
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Active
1
Active
1
Deasserted
High-Z
1
1,2
Notes:
1.
2.
Active: WAIT is asserted until data becomes valid, then deasserts.
When OE# = VIH during writes, WAIT = High-Z.
11.1.6
Data Output Configuration (RCR.9)
The Data Output Configuration (DOC) bit, RCR.9 determines whether a data word
remains valid on the data bus for one or two clock cycles. This period of time is called
the “data cycle”. When DOC is set, output data is held for two clocks (default). When
DOC is cleared, output data is held for one clock (see Figure 11, “Data Hold Timing” on
page 38). The processor’s data setup time and the flash memory’s clock-to-data output
delay should be considered when determining whether to hold output data for one or
two clocks. A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
tCHQV (ns) + tDATA (ns)
≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:
20 ns + 4 ns
≤ 25 ns
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock. If tCHQV (ns) + DATA (ns) >One CLK Period (ns), data hold setting of
t
2 clock periods must be used.
Figure 11: Data Hold Timing
CLK [C]
1 CLK
Valid
Output
Valid
Output
Valid
Output
D[15:0] [Q]
Data Hold
2 CLK
Valid
Output
Valid
Output
D[15:0] [Q]
Data Hold
Datasheet
38
Jul 2011
Order Number: 208034-04
P33-65nm SBC
11.1.7
WAIT Delay (RCR.8)
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
11.1.8
Burst Sequence (RCR.7)
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 16 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
Table 16: Burst Sequence Word Ordering
Burst Addressing Sequence (DEC)
Start
Addr.
(DEC)
Burst
Wrap
(RCR.3)
4-Word Burst
(BL[2:0] = 0b001)
8-Word Burst
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
(BL[2:0] = 0b010)
0
1
2
3
4
0
0
0
0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
0-1-2-3-4…14-15
1-2-3-4-5…15-0
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
2-3-4-5-6…15-0-1
3-4-5-6-7…15-0-1-2
4-5-6-7-8…15-0-1-2-3
5-6-7-8-9…15-0-1-2-3-
4
5
6
7
0
0
0
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
6-7-8-9-10…15-0-1-2-
3-4-5
7-8-9-10…15-0-1-2-3-
4-5-6
14-15-16-17-18-19-20-
…
14
15
0
0
14-15-0-1-2…12-13
15-0-1-2-3…13-14
15-16-17-18-19-20-21-
…
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
0-1-2-3-4…14-15
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
4-5-6-7-8…18-19
5-6-7-8-9…19-20
6-7-8-9-10…20-21
7-8-9-10-11…21-22
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
14-15-16-17-18-19-20-
…
14
15
1
1
14-15-16-17-18…28-29
15-16-17-18-19…29-30
15-16-17-18-19-20-21-
…
Datasheet
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Jul 2011
OrderNumber:208034-04
P33-65nm
11.1.9
Clock Edge (RCR.6)
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
11.1.10
Burst Wrap (RCR.3)
The Burst Wrap (BW) bit determines whether 4, 8, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries.
When BW is set, burst wrapping does not occur (default). When BW is cleared, burst
wrapping occurs.
11.1.11
Burst Length (RCR[2:0])
The Burst Length bits (BL[2:0]) selects the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and
continuous word.
Continuous burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 16, “Burst Sequence Word Ordering” on page 39). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
11.2
One-Time Programmable (OTP) Registers
The device contains 17 OTP Registers that can be used to implement system security
measures and/or device identification. Each OTP Register can be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit
number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
are blank. Users can program these registers as needed. Once programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see Figure 12,
“OTP Register Map” on page 41).
The OTP Registers contain OTP bits; when programmed, PR bits cannot be erased. Each
OTP Register can be accessed multiple times to program individual bits, as long as the
register remains unlocked.
Each OTP Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated OTP Register can only be read; it can no longer be
programmed. Additionally, because the Lock Register bits themselves are OTP, when
programmed, Lock Register bits cannot be erased. Therefore, when a OTP Register is
locked, it cannot be unlocked.
Datasheet
40
Jul 2011
Order Number: 208034-04
P33-65nm SBC
.
Figure 12: OTP Register Map
0x109
128-bit OTP Register 16
(User-Programmable)
0x102
0x91
128-bit OTP Register 1
(User-Programmable)
0x8A
0x89
Lock Register 1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit OTP Register 0
64-bit Segment
(Factory-Programmed)
0x81
0x80
Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
11.2.1
11.2.2
Reading the OTP Registers
The OTP Registers can be read from OTP-RA address. To read the OTP Register, first
issue the Read Device Identifier command at OTP-RA address to place the device in the
Read Device Identifier state (see Section 6.2, “Device Command Bus Cycles” on
page 18). Next, perform a read operation using the address offset corresponding to the
register to be read. Table 7, “Device Identifier Information” on page 21 shows the
address offsets of the OTP Registers and Lock Registers. PR data is read 16 bits at a
time.
Programming the OTP Registers
To program any of the OTP Registers, first issue the Program OTP Register command at
the parameter’s base address plus the offset to the desired OTP Register (see Section
6.2, “Device Command Bus Cycles” on page 18). Next, write the desired OTP Register
data to the same OTP Register address (see Figure 12, “OTP Register Map” on
page 41).
Datasheet
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Jul 2011
OrderNumber:208034-04
P33-65nm
The device programs the 64-bit and 128-bit user-programmable OTP Register data 16
bits at a time (see Figure 36, “OTP Register Programming Flowchart” on page 79).
Issuing the Program OTP Register command outside of the OTP Register’s address
space causes a program error (SR.4 set). Attempting to program a locked OTP Register
causes a program error (SR.4 set) and a lock error (SR.1 set).
Note:
When programming the OTP bits in the OTP Registers for a Top Parameter Device, the
following upper address bits must also be driven properly: A[Max:17] driven high (VIH).
11.2.3
Locking the OTP Registers
Each OTP Register can be locked by programming its respective lock bit in the Lock
Register. To lock a OTP Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by the desired Lock Register
data (see Section 6.2, “Device Command Bus Cycles” on page 18). The physical
addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These
addresses are used when programming the Lock Registers (see Table 7, “Device
Identifier Information” on page 21).
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at the
“factory”, locking the lower, pre-programmed 64-bit region of the first 128-bit OTP
Register containing the unique identification number of the device. Bit 1 of Lock
Register 0 can be programmed by the user to lock the user-programmable, 64-bit
region of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all
other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each of
the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit OTP
Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit OTP
Register.
Caution:
After being locked, the OTP Registers cannot be unlocked.
Datasheet
42
Jul 2011
Order Number: 208034-04
P33-65nm SBC
12.0
Power and Reset Specifications
12.1
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
12.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 17: Power and Reset
Num
Symbol
Parameter
RST# pulse width low
Min
Max
Unit
Notes
P1
tPLPH
100
-
-
ns
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
RST# low to device reset during erase
RST# low to device reset during program
VCC Power valid to RST# de-assertion (high)
25
25
-
P2
tPLRH
-
µs
P3
tVCCPH
60
Notes:
1.
2.
3.
4.
5.
6.
7.
These specifications are valid for all device versions (packages and speeds).
The device may reset if tPLPH is < tPLPH Min, but this is not guaranteed.
Not applicable if RST# is tied to VCC.
Sampled, but not 100% tested.
When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN
.
When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN
.
Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
Datasheet
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Jul 2011
OrderNumber:208034-04
P33-65nm
Figure 13: Reset Operation Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
RST# [P]
RST# [P]
RST# [P]
VCC
read mode
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
12.3
Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power
supply current considerations are: 1) standby current levels; 2) active current levels;
and 3) transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
de-coupling capacitor selection suppress transient voltage peaks.
Because Numonyx flash memory devices draw their power from VCC, VPP, and VCCQ,
each power connection should have a 0.1 µF ceramic capacitor to ground. High-
frequency, inherently low-inductance capacitors should be placed as close as possible
to package leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
Datasheet
44
Jul 2011
Order Number: 208034-04
P33-65nm SBC
13.0
Maximum Ratings and Operating Conditions
13.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the Absolute Maximum Ratings may cause permanent
damage. These are stress ratings only.
Table 18: Absolute Maximum Ratings
Parameter
Maximum Rating
Notes
Temperature under bias
–40 °C to +85 °C
–65 °C to +125 °C
–2.0 V to +5.6 V
–2.0 V to +11.5 V
–2.0 V to +5.6 V
–2.0 V to +5.6 V
100 mA
-
-
Storage temperature
Voltage on any input/output signal (except VCC, VPP and VCCQ)
1
VPP voltage
1,2
1
VCC voltage
VCCQ voltage
Output short circuit current
Notes:
1
3
1.
2.
3.
Voltages shown are specified with respect to VSS. During infrequent non-periodic transitions, the level may undershoot
to –2.0 V for periods less than 20 ns or overshoot to VCC + 2.0 V or VCCQ + 2.0 V for periods less than 20 ns.
Program/erase voltage is typically 2.3 V ~ 3.6 V. 9.0 V can be applied for 80 hours maximum total. 9.0 V program/erase
voltage may reduce block cycling capability.
Output shorted for no more than one second. No more than one output shorted at a time.
13.2
Operating Conditions
Note:
Operation beyond the Operating Conditions is not recommended and extended
exposure beyond the Operating Conditions may affect device reliability.
Table 19: Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
TC
Operating Temperature
VCC Supply Voltage
–40
+85
3.6
3.6
3.6
3.6
9.5
80
°C
1
-
VCC
2.3
CMOS inputs
TTL inputs
2.3
VCCQ
I/O Supply Voltage
-
2.4
V
VPPL
VPPH
tPPH
VPP Voltage Supply (Logic Level)
1.5
Buffered Enhanced Factory Programming VPP
8.5
Maximum VPP Hours
Main and Parameter Blocks
Main Blocks
VPP = VPPH
-
Hours
Cycles
2
VPP = VPPL
VPP = VPPH
VPP = VPPH
100,000
-
Block
Erase
Cycles
-
-
1000
2500
Parameter Blocks
Notes:
1.
2.
TC = Case Temperature.
In typical operation VPP program voltage is VPPL
.
Datasheet
45
Jul 2011
OrderNumber:208034-04
P33-65nm
14.0
Electrical Specifications
14.1
DC Current Characteristics
Table 20: DC Current Characteristics (Sheet 1 of 2)
CMOS Inputs
(VCCQ =
TTL Inputs
(VCCQ =
2.3 V - 3.6 V) 2.4 V - 3.6 V)
Sym
Parameter
Unit
Test Conditions
Notes
Typ
Max
Typ
Max
VCC = VCC Max
VCCQ = VCCQ Max
VIN = VCCQ or VSS
ILI
Input Load Current
-
±1
-
±2
µA
µA
1,6
Output
VCC = VCC Max
ILO
Leakage
Current
DQ[15:0], WAIT
-
±1
-
±10
VCCQ = VCCQ Max
V
IN = VCCQ or VSS
64-Mbit
35
120
710
2000
VCC = VCC Max
VCCQ = VCC Max
CE# =VCCQ
RST# = VCCQ (for ICCS
RST# = VSS (for ICCD
WP# = VIH
ICCS
ICCD
,
VCC Standby,
Power-Down
µA
1,2
)
128-Mbit
55
120
710
2000
)
Asynchronous Single-
Word f = 5 MHz (1
CLK)
20
12
25
16
-
-
-
-
mA
mA
8-Word Read
Page-Mode Read
f = 13 MHz (17 CLK)
8-Word Read
4-Word Read
VCC = VCCMax
CE# = VIL
OE# = VIH
Average
VCC
Read
Current
16
19
19
22
-
-
-
-
mA
mA
ICCR
1
8-Word Read Inputs: VIL or
VIH
Synchronous Burst
f = 52 MHz, LC=4
16-Word
Read
22
26
-
-
mA
mA
Continuous
Read
23
35
26
35
28
50
-
-
35
50
VPP = VPPL, Pgm/Ers in progress
1,3,5
1,3,5
ICCW,
ICCE
VCC Program Current,
VCC Erase Current
mA
VPP = VPPH, Pgm/Ers in
progress
33
26
33
VCC Program
64-Mbit
120
710
2000
ICCWS,
ICCES
Suspend Current,
VCC Erase
Suspend Current
CE# = VCCQ; suspend in
progress
µA
µA
1,3,4
1,3,7
128-Mbit
55
120
5
710
0.2
2000
5
IPPS,
VPP Standby Current,
IPPWS, VPP Program Suspend Current,
0.2
VPP = VPPL, suspend in progress
VPP Erase Suspend Current
IPPES
IPPR
VPP Read
2
0.05
5
15
0.10
10
2
0.05
5
15
0.10
10
µA
VPP = VPPL
1,3
3
VPP = VPPL, program in progress
VPP = VPPH, program in progress
VPP = VPPL, erase in progress
VPP = VPPH, erase in progress
IPPW
VPP Program Current
VPP Erase Current
mA
0.05
5
0.10
10
0.05
5
0.10
10
IPPE
mA
3
Datasheet
46
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 20: DC Current Characteristics (Sheet 2 of 2)
CMOS Inputs
(VCCQ =
TTL Inputs
(VCCQ =
2.3 V - 3.6 V) 2.4 V - 3.6 V)
Sym
Parameter
Unit
Test Conditions
Notes
Typ
Max
Typ
Max
0.05
5
0.10
10
0.05
5
0.10
10
VPP = VPPL
VPP = VPPH
IPPBC
VPP Blank Check
mA
3
Notes:
1.
2.
3.
4.
5.
All currents are RMS unless noted. Typical values at typical VCC, TC = +25 °C.
ICCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
Sampled, not 100% tested.
I
I
CCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR
CCW, ICCE measured over typical or max times specified in Section 15.5, “Program and Erase
.
Characteristics” on page 58
.
6.
7.
if VIN > VCC the input load current increases to 10µA max.
the IPPS, IPPWS, IPPES Will increase to 200µA when VPP/WP# is at VPPH
.
14.2
DC Voltage Characteristics
Table 21: DC Voltage Characteristics
CMOS Inputs
(VCCQ = 2.3 V – 3.6 V)
TTL Inputs (1)
(VCCQ = 2.4 V – 3.6 V)
Sym
Parameter
Unit
Test Conditions
Notes
Min
Max
Min
Max
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
0.4
-0.5
2.0
0.6
V
V
-
-
2
-
VCCQ – 0.4
VCCQ + 0.5
VCCQ + 0.5
VCC = VCC Min
VCCQ = VCCQ Min
VOL
Output Low Voltage
Output High Voltage
-
0.2
-
-
0.2
-
V
V
I
OL = 100 µA
VCC = VCC Min
VCCQ = VCCQ Min
OH = –100 µA
VOH
VCCQ – 0.2
VCCQ – 0.2
-
I
VPPLK
VLKO
VPP Lock-Out Voltage
VCC Lock Voltage
-
0.4
-
0.4
V
V
V
-
-
-
3
-
1.5
0.9
-
-
1.5
0.9
-
-
VLKOQ
VCCQ Lock Voltage
-
VPP Voltage Supply
(Logic Level)
VPPL
1.5
8.5
3.6
9.5
1.5
8.5
3.6
9.5
V
V
-
-
-
-
Buffered Enhanced
Factory Programming
VPP
VPPH
Notes:
1.
2.
3.
Synchronous read mode is not supported with TTL inputs.
VIL can undershoot to –0.4 V and VIH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less.
VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH
.
outside their valid ranges
Datasheet
47
Jul 2011
OrderNumber:208034-04
P33-65nm
15.0
AC Characteristics
15.1
AC Test Conditions
Figure 14: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
IO_REF.WMF
Note: AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input
rise and fall times (10% to 90%) < 5 ns. Worst-case speed occurs at VCC = VCCMin
.
Figure 15: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Notes:
1.
2.
See the following table for component values.
Test configuration component value for worst case speed conditions.
CL includes jig capacitance
3.
.
Table 22: Test Configuration Component Value for Worst Case Speed Conditions
Test Configuration
VCCQ Min Standard Test
CL (pF)
30
Figure 16: Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
Datasheet
48
Jul 2011
Order Number: 208034-04
P33-65nm SBC
15.2
Capacitance
Table 23: Capacitance
Symbol
Parameter
Signals
Min
Typ
Max
Unit
Condition
Notes
Address, Data,
CE#, WE#, OE#,
RST#, CLK,
Typ temp = 25 °C,
Max temp = 85 °C,
VCC = (0 V - 3.6 V),
VCCQ = (0 V - 3.6 V),
Discrete silicon die
CIN
Input Capacitance
Output Capacitance
2
2
6
4
7
5
pF
pF
1,2,3
ADV#, WP#
COUT
Data, WAIT
Notes:
1.
2.
3.
Capacitance values are for a single die; for dual die, the capacitance values are doubled.
Sampled, not 100% tested.
Silicon die capacitance only, add 1 pF for discrete packages.
15.3
AC Read Specifications
Table 24: AC Read Specifications - (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
Easy BGA
TSOP
60
70
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
R1
R2
R3
tAVAV
tAVQV
tELQV
Read cycle time
-
Easy BGA
TSOP
60
70
60
70
25
150
-
-
-
Address to output valid
Easy BGA
TSOP
-
-
CE# low to output valid
OE# low to output valid
-
R4
R5
R6
R7
R8
R9
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
-
-
1,2
1
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
0
0
-
1,3
1,2,3
-
20
15
-
1,3
Output hold from first occurring address, CE#, or OE#
change
R10
tOH
0
-
ns
R11
R12
R13
R15
R16
R17
tEHEL
tELTV
tEHTZ
tGLTV
tGLTX
tGHTZ
CE# pulse width high
17
-
-
ns
ns
ns
ns
ns
ns
1
CE# low to WAIT valid
CE# high to WAIT high-Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
17
20
17
-
-
1,3
1
-
0
-
1,3
20
Latching Specifications
R101
R102
tAVVH
tELVH
Address setup to ADV# high
CE# low to ADV# high
10
10
-
-
ns
ns
ns
ns
1
1
1
1
-
Easy BGA
60
70
R103
tVLQV
ADV# low to output valid
TSOP
-
Datasheet
49
Jul 2011
OrderNumber:208034-04
P33-65nm
Table 24: AC Read Specifications - (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
R104
R105
R106
R108
R111
tVLVH
tVHVL
tVHAX
tAPA
ADV# pulse width low
ADV# pulse width high
10
10
9
-
-
ns
ns
ns
ns
ns
1
1
Address hold from ADV# high
Page address access
-
1,4
-
25
-
1
tphvh
RST# high to ADV# high
30
Clock Specifications
Easy BGA
TSOP
-
-
52
40
-
MHz
MHz
ns
R200
R201
fCLK
CLK frequency
CLK period
Easy BGA
TSOP
19.2
25
5
tCLK
-
ns
1,3,5,6
Easy BGA
TSOP
-
ns
R202
R203
tCH/CL
CLK high/low time
CLK fall/rise time
9
-
ns
tFCLK/RCLK
0.3
3
ns
Synchronous Specifications(5)
R301
R302
R303
tAVCH/L
tVLCH/L
tELCH/L
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
9
9
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,6
1,6
1,6
1,6
1,6
1,6
1,6
1,4,6
1,6
1,6
1
-
Easy BGA
TSOP
17
20
-
R304
tCHQV / tCLQV CLK to output valid
-
Easy BGA
TSOP
3
5
10
-
R305
R306
R307
R311
R312
tCHQX
tCHAX
tCHTV
tCHVL
tCHTX
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
-
-
Easy BGA
TSOP
17
20
-
-
CLK Valid to ADV# Setup
WAIT Hold from CLK
3
3
5
Easy BGA
TSOP
-
1,6
1,6
-
Notes:
1.
See Figure 14, “AC Input/Output Reference Waveform” on page 48 for timing measurements and max
allowable input slew rate.
2.
3.
4.
5.
6.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
Sampled, not 100% tested.
Address hold in synchronous burst read mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
Synchronous burst read mode is not supported with TTL level inputs.
Applies only to subsequent synchronous reads.
Datasheet
50
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 17: Asynchronous Single-Word Read (ADV# Low)
R1
R2
Address[A]
ADV#[V]
R3
R8
CE# [E]
R4
R9
OE# [G]
R15
R17
WAIT [T]
R7
R6
Data [D/Q]
R5
RST# [P]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Figure 18: Asynchronous Single-Word Read (ADV# Latch)
R1
R2
Address[A]
A[3:1][A]
R101
R105
R1 06
R104
ADV#[V]
CE#[E]
R3
R8
R4
R9
R17
OE#[G]
WAIT[T]
R15
R7
R6
R10
Data[D/Q]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low)
Datasheet
51
Jul 2011
OrderNumber:208034-04
P33-65nm
Figure 19: Asynchronous Page-Mode Read Timing
R2
A[Max:4] [A]
A[3:1]
Valid Address
R10
R10
R10
R10
0
1
2
7
R101
R105
R106
ADV# [V]
CE# [E]
R3
R8
R4
R9
OE# [G]
WAIT [T]
R6
R13
R108
Q1
R108
Q2
R108
Q 7
DATA [D/Q]
Q0
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
.
Figure 20: Synchronous Single-Word Array or Non-array Read Timing
R301
R306
CLK [C]
R2
Address [A]
R101
R104
R106
R105
ADV# [V]
R303
R102
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R7
R9
R15
R307
R304
R312 R17
R4
R305
Data [D/Q]
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
2.
Datasheet
52
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 21: Continuous Burst Read, showing an Output Delay Timing
R301
R302
R306
R304
R304
R304
CLK [C]
Address [A]
ADV# [V]
R2
R101
R106
R105
R303
R102
R3
CE# [E]
OE# [G]
R15
R307
R304
R312
WAIT [T]
R4
R7
R305
R305
R305
R305
Data [D/Q]
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
nAottth4e-weonrddobfoWunodrdarLyinaeli;gtnheed.deSleaeySinecucrtrieodnw1h1en.1a.3bu,rs“tEancdceossfcWroossreds Lai1n6e-w(oErOd WbouLn)dCaroynasniddtehreasttiaorntisng” aodndress is
page 36 for more information.
Figure 22: Synchronous Burst-Mode Four-Word Read Timing
R302
R301
R306
CLK [C]
Address [A]
ADV# [V]
R2
R101
A
R105
R102
R106
R303
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R9
R15
R17
R307
R4
R304
R305
Q0
R7
R304
R10
Data [D/Q]
Q1
Q2
Q3
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR.10=0, WAIT asserted low).
Datasheet
53
Jul 2011
OrderNumber:208034-04
P33-65nm
15.4
AC Write Specifications
Table 25: AC Write Specifications
Num
W1
Symbol
tPHWL
Parameter
Min
Max
Unit
Notes
RST# high recovery to WE# low
CE# setup to WE# low
150
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
W2
tELWL
0
W3
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
tVPWH
tQVVL
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
50
1,2,4
W4
50
1,2, 12
W5
50
W6
0
1,2
W7
0
W8
0
W9
20
1,2,5
W10
W11
W12
W13
W14
W16
VPP setup to WE# high
VPP hold from Status read
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
200
1,2,3,7
0
tQVBL
0
200
1,2,3,7
tBHWH
tWHGL
tWHQV
0
1,2,9
WE# high to read valid
tAVQV + 35
1,2,3,6,10
Write to Asynchronous Read Specifications
W18 tWHAV WE# high to Address valid
Write to Synchronous Read Specifications
0
-
ns
1,2,3,6,8
W19
W20
tWHCH/L
tWHVH
WE# high to Clock valid
WE# high to ADV# high
19
19
-
-
ns
ns
1,2,3,6,10
Write Specifications with Clock Active
W21
W22
tVHWL
tCHWL
ADV# high to WE# low
Clock high to WE# low
-
-
20
20
ns
ns
1,2,3,11
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH
.
5.
Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
6.
7.
8.
tWHVH or tWHCH/L must be met when transiting from a write cycle to a synchronous burst read.
VPP and WP# should be at a valid level until erase or program success is determined.
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
9.
10.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
Add 10 ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
11.
12.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation
to this timing specification.
Datasheet
54
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 23: Write-to-Write Timing
W5
W8
W5
W8
Address[A]
W2
W6
W2
W6
CE# [E]
W3
W9
W3
WE# [W]
OE# [G]
W4
W7
W4
W7
Data [D/Q]
W1
RST# [P]
Figure 24: Asynchronous Read-to-Write Timing
R1
R2
W5
W8
Address[A]
R3
R8
R9
CE# [E]
R4
OE# [G]
W2
W3
W6
WE# [W]
R15
R17
WAIT [T]
R7
R6
W7
R10
W4
Data [D/Q]
RST# [P]
Q
D
R5
Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted.
Datasheet
55
Jul 2011
OrderNumber:208034-04
P33-65nm
Figure 25: Write-to-Asynchronous Read Timing
W5
W8
R1
Address[A]
ADV# [V]
W2
W6
R10
CE# [E]
WE# [W]
OE# [G]
WAIT [T]
W3
W18
W14
R15
R17
R4
R2
R3
R8
R9
W4
W7
Data [D/Q]
RST# [P]
D
Q
W1
Figure 26: Synchronous Read-to-Write Timing
Latency Count
R301
R302
R306
CLK [C]
R2
W5
R101
W18
Address[A]
R105
R102
R106
R104
ADV# [V]
R303
R11
R13
R3
W6
CE# [E]
OE# [G]
R4
R8
W21
W22
W15
W21
W22
W2
W8
W3
W9
WE#[W]
WAIT [T]
R16
R307
R304
R312
R7
R305
W7
Q
D
D
Data [D/Q]
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR 10=0, WAIT asserted low). Clock is
ignored during write operation.
Datasheet
56
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 27: Write-to-Synchronous Read Timing
Latency Count
R302
R301
R2
CLK[C]
W5
W8
R306
R106
Address [A]
R104
R303
ADV#[V]
CE# [E]
W6
W2
R11
W18
W19
W20
W3
WE# [W]
OE# [G]
WAIT [T]
R4
R15
R3
R307
W7
R304
R305
R304
W4
D
Q
Q
Data [D/Q]
RST# [P]
W1
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low).
Datasheet
57
Jul 2011
OrderNumber:208034-04
P33-65nm
15.5
Program and Erase Characteristics
Table 26: Program and Erase Specifications
VPPL
Typ
VPPH
Typ
Num
Symbol
Parameter
Unit
Note
Min
Max
Min
Max
Conventional Word Programming
Single word 40
Buffered Programming
Program
Time
W200
tPROG/W
-
175
-
40
175
µs
µs
1
Aligned 16-Wd, BP time
(32 Words)
-
-
-
70
85
200
200
-
-
-
70
85
200
200
800
tPROG/
Buffer
Program
Time
Aligned 32-Wd, BP time
(32 Word)
W250
1
one full buffer (256
Words)
284
1280
160
Buffered Enhanced Factory Programming
W451
W452
tBEFP/B
Single byte
BEFP Setup
N/A
N/A
N/A
N/A
N/A
N/A
-
0.31
-
-
-
1,2
1
Program
µs
tBEFP/Setup
10
Erase and Suspend
W500
W501
W600
W601
W602
tERS/PB
tERS/MB
tSUSP/P
tSUSP/E
tERS/SUSP
32-KByte Parameter
128-KByte Main
Program suspend
Erase suspend
-
0.4
0.5
20
2.5
4.0
25
25
-
-
-
-
-
-
0.4
0.5
20
2.5
4.0
25
25
-
Erase Time
s
-
1
-
Suspend
Latency
-
20
20
µs
Erase to Suspend
-
blank check
-
500
500
1,3
-
W702
tBC/MB
blank check Main Array Block
3.2
-
-
3.2
-
ms
Notes:
1.
Typical values measured at TC = +25 °C and nominal voltages. Performance numbers are valid for all speed versions.
Excludes system overhead. Sampled, but not 100% tested.
2.
3.
Averaged over entire device.
W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
Datasheet
58
Jul 2011
Order Number: 208034-04
P33-65nm SBC
16.0
Ordering Information
Figure 28: Decoder for P33-65nm (SBC) Products
J S 2 8 F 1 2 8 P 3 3 B F
7 0
*
Device Features*
Package Designator
JS = 56-Lead TSOP, lead-free
RC =64-Ball Easy BGA, leaded
PC =64-Ball Easy BGA, lead-free
Speed
60ns
70ns
Device Details
65nm lithography
Product Line Designator
28F = Numonyx® Flash Memory
Parameter Location
Bottom Parameter
B =
T = Top Parameter
Device Density
128= 128-Mbit
640 = 64-Mbit
Product Family
Numonyx® Flash Memory (P33)
P 33 =
V
CC =2. 3– 3. 6V
V
CCQ =2. 3– 3. 6V
Table 27: Valid Combinations for Discrete Products
64-Mbit
128-Mbit
RC28F640P33TF60*
RC28F640P33BF60*
PC28F640P33TF60*
PC28F640P33BF60*
JS28F640P33TF70*
JS28F640P33BF70*
RC28F128P33TF60*
RC28F128P33BF60*
PC28F128P33TF60*
PC28F128P33BF60*
JS28F128P33TF70*
JS28F128P33BF70*
Note:
The last digit is randomly assigned to cover packing media and/or features or other specific configuration. For
further information on ordering products or for product part numbers, go to:
http://www.micron.com/partscatalog.html?categoryPath=products/nor_flash/parallel_nor_flash
Datasheet
59
Jul 2011
OrderNumber:208034-04
P33-65nm
Appendix A Supplemental Reference Information
A.1
Common Flash Interface
The Common Flash Interface (CFI) is part of an overall specification for multiple
command-set and control-interface descriptions. This appendix describes the database
structure containing the data returned by a read operation after issuing the Read CFI
command (see Section 6.2, “Device Command Bus Cycles” on page 18). System
software can parse this database structure to obtain information about the flash device,
such as block size, density, bus width, and electrical specifications. The system
software will then know which command set(s) to use to properly perform flash writes,
block erases, reads and otherwise control the flash device.
A.1.1
Query Structure Output
The Query database allows system software to obtain information for controlling the
flash device. This section describes the device’s CFI-compliant interface that allows
access to Query data.
Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical
offset value is the address relative to the maximum bus width supported by the device.
On this family of devices, the Query table device starting address is a 10h, which is a
word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0
)
and 00h in the high byte (DQ15-8).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs have 00h on
the upper byte in this mode.
Table 28: Summary of Query Structure Output as a Function of Device and Mode
Hex
Hex
Code
51
52
59
ASCII
Value
"Q"
"R"
"Y"
Device
Offset
00010:
00011:
00012:
Device Addresses
Datasheet
60
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 29: Example of Query Structure Output of x16 Devices
Offset
AX-A1
Hex Code
Value
D15-D0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
0051
0052
0059
P_IDLO
P_IDHI
PLO
“Q”
“R”
“Y”
PrVendor ID#
PrVendor TblAdr
PHI
A_IDLO
A_IDHI
...
AltVendor ID#
...
A.1.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or database. Table 30 summarizes the structure sub-sections and address
locations.
Table 30: Query Structure
00001-Fh Reserved
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
00010h
CFI query identification string
0001Bh System interface information
00027h
Device geometry definition
Vendor-defined additional information specific
to the Primary Vendor Algorithm
P(3)
Primary Numonyx-specific Extended Query
Note:
1.
Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of
device bus width and mode.
2.
3.
BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord).
Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table.
A.1.3
Read CFI Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Datasheet
61
Jul 2011
OrderNumber:208034-04
P33-65nm
Table 31: CFI Identification
Hex
Code
Offset Length
Description
Add.
Value
10:
11:
12:
-51
-52
-59
“Q”
“R”
“Y”
10h
3
Query-unique ASCII string “QRY”
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
13:
14:
-01
-00
13h
15h
17h
2
2
2
15:
16:
-0A
-01
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
17:
18:
-00
-00
Secondary algorithm Extended Query Table address.
0000h means none exists
19:
1A:
-00
-00
19h
2
Datasheet
62
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 32: System Interface Information
Hex
Code
Offset Length
Description
Add
Value
VCC logic supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1Bh
1Ch
1
1
1B:
-23
-36
2.3V
VCC logic supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1C:
1D:
1E:
3.6V
8.5V
9.5V
VPP [programming] supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
1Dh
1Eh
1
1
-85
-95
VPP [programming] supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
1Fh
20h
21h
22h
1
1
1
1
“n” such that typical single word program time-out = 2n
“n” such that typical full buffer write time-out = 2n
-sec
µ
-sec
1F:
20:
21:
22:
-06
-09
-09
-00
64µs
512µs
0.5s
µ
“n” such that typical block erase time-out = 2n m-sec
“n” such that typical full chip erase time-out = 2n m-sec
NA
“n” such that maximum word program time-out = 2n times
typical
23h
24h
1
1
23:
24:
-02
-02
256µs
“n” such that maximum buffer write time-out = 2n times
typical
2048µs
“n” such that maximum block erase time-out = 2n times
typical
25h
26h
1
1
25:
26:
-03
-00
4s
“n” such that maximum chip erase time-out = 2n times typical
NA
Datasheet
63
Jul 2011
OrderNumber:208034-04
P33-65nm
A.1.4
Device Geometry Definition
Table 33: Device Geometry Definition
Hex
Code
Offset Length
Description
Add
Value
27h
28h
1
“n” such that device size = 2n in number of bytes
Flash device interface code assignment:
"n" such that n+1 specifies the bit field that represents the flash device width
capabilities as described in the table:
27:
See Table Below
7
_
6
_
5
_
4
_
3
x64
11
_
2
x32
10
_
1
x16
9
0
x8
8
2
28:
29:
-01
-00
x16
512
15
_
14
_
13
_
12
_
_
_
2A:
2B:
-09
-00
2Ah
2Ch
2
1
“n” such that maximum number of bytes in write buffer = 2n
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or more contiguous
same-size erase blocks.
2C:
See Table Below
See Table Below
3. Symmetrically blocked partitions have one blocking region
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
Erase Block Region 1 Information
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
2D
4
4
4
Erase Block Region 2 Information
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
31h
35h
See Table Below
Reserved for future erase block region information
See Table Below
64-Mbit
128-Mbit
64-Mbit
128-Mbit
Address
Address
-B
-T
-B
-T
-B
-T
-B
-T
27:
28:
29:
2A
-17
-01
-00
-09
-00
-02
-03
-00
-80
-17
-01
-00
-09
-00
-02
-3E
-00
-00
-18
-01
-00
-09
-00
-02
-03
-00
-80
-18
-01
-00
-09
-00
-02
-7E
-00
-00
30:
31:
32:
33:
34:
35:
36:
37:
38:
-00
-3E
-00
-00
-02
-00
-00
-00
-00
-02
-03
-00
-80
-00
-00
-00
-00
-00
-00
-7E
-00
-00
-02
-00
-00
-00
-00
-02
-03
-00
-80
-00
-00
-00
-00
-00
2B
2C:
2D:
2E:
2F:
Datasheet
64
Jul 2011
Order Number: 208034-04
P33-65nm SBC
A.1.5
Numonyx-Specific Extended Query Table
Table 34: Primary Vendor-Specific Extended Query:
Offset
P=10Ah
Description
(Optional flash features and commands)
Hex
Code
Length
Add.
Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
10A:
10B:
10C:
10D:
10E:
10F:
-50
-52
-49
-31
-35
-E6
-01
-00
-00
“P”
“R”
“I”
Primary extended query table
Unique ASCII string “PRI”
3
1
1
4
Major version number, ASCII
“1”
“5”
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 10-31 are reserved; undefined bits are “0”. If bit 31
“1”then another 31 bit field of Optional features follows at
the end of the bit-30 field.
110(1)
111:
:
112:
bit 0 Chip erase supported
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 0
bit 8 = 1
bit 9 = 0
bit 10 = 0
bit 11 = 0
bit 12 = 0
bit 30 = 0
bit 31 = 0
No
Yes
Yes
No
No
Yes
Yes
Yes
No
Yes
No
No
No
No
No
No
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
TSOP
BGA
bit 8 Synchronous read supported
bit 9 Simultaneous operations supported
bit 10 Extended Flash Array Blocks supported
bit 11 Permanent Block Locking of up to Full Main Array supported
bit 12 Permanent Block Locking of up to Partial Main Array supported
bit 30 CFI Link(s) to follow
bit 31 Another "Optional Features" field to follow
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1-7 reserved; undefined bits are “0”
(P+9)h
1
2
113:
-01
bit 0 Program supported after erase suspend
Block Status Register mask
bit 0 = 1
Yes
(P+A)h
(P+B)h
114:
115:
-03
-00
bits 2-15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status Register active
bit 1 Block Lock-Down Bit Status active
bit 4 EFA Block Lock-Bit Status Register active
bit 0 = 1
Yes
Yes
No
bit 1 = 1
bit 4 = 0
Datasheet
65
Jul 2011
OrderNumber:208034-04
P33-65nm
Offset
P=10Ah
Description
(Optional flash features and commands)
Hex
Code
Length
Add.
Value
bit 5 EFA Block Lock-Down Bit Status active
bit 5 = 0
No
VCC logic supply highest performance program/erase voltage
bits 0-3 BCD value in 100 mV
bits 4-7 BCD value in volts
(P+C)h
(P+D)h
1
1
116:
117:
-30
-90
3.0V
9.0V
VPP optimum program/erase supply voltage
bits 0-3 BCD value in 100 mV
bits 4-7 HEX value in volts
Note:
1.
Address 0x110 for TSOP: -00; Address 0x110 for BGA: -01.
Table 35: OTP Register Information
Offset(1)
Length
Description
(Optional flash features and commands)
Hex
Code
Add.
Value
P=10Ah
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
(P+E)h
1
118:
-02
2
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
(P+F)h
(P+10)h
(P+11)h
(P+12)h
119:
11A:
11B:
11C:
-80
-00
-03
-03
80h
00h
8 byte
8 byte
4
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
11D:
11E:
11F:
120:
-89
-00
-00
-00
89h
00h
00h
00h
Protection Field 2: Protection Description
Bits 0–31 point to the Protection register physical Lock-word
address in the Jedec-plane.
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
(P+19)h
(P+1A)h
(P+1B)h
(P+1C)h
Following bytes are factory or user-programmable.
bits 32–39 = “n” such that n = factory pgm'd groups (low byte)
bits 40–47 = “n” such that n = factory pgm'd groups (high
byte)
121:
122:
123:
-00
-00
-00
0
0
0
10
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n” such that n = user pgm'd groups (low byte)
bits 64–71 = “n” such that n = user pgm'd groups (high byte)
bits 72–79 = “n” such that 2n = user programmable bytes/
group
124:
125:
126:
-10
-00
-04
16
0
16
Datasheet
66
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 36: Burst Read Information
Offset
P=10Ah
Description
(Optional flash features and commands)
Hex
Code
Length
Add.
Value
Page Mode Read capability
bits 0-7 = “n” such that 2n HEX value represents the number
of read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+1D)h
1
1
127:
128:
-04
-04
16 Byte
4
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
(P+1E)h
Synchronous mode read capability configuration 1
Bits 3-7 = Reserved
bits 0-2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0-2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
(P+1F)h
1
129:
-01
4
(P+20)h
(P+21)h
(P+22)h
1
1
1
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
12A:
12B:
12C:
-02
-03
-07
8
16
Cont
Table 37: Partition and Erase Block Region Information
Offset(1)
P = 10Ah
Bottom Top
See table below
Address
Description
(Optional flash features and commands)
Bot
Top
Len
Number of device hardw are-partition regions w ithin the device.
x = 0: a single hardw are partition device (no fields follow ).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
12D:
12D:
(P+23)h (P+23)h
Datasheet
67
Jul 2011
OrderNumber:208034-04
P33-65nm
Table 38: Partition Region 1 Information (Sheet 1 of 2)
Offset(1)
See table below
Address
P = 10Ah
Bottom Top
Description
Bot
Top
12E
12F
130:
131:
132:
(Optional flash features and commands)
Len
(P+24)h (P+24)h Data size of this Parition Region Information field
(P+25)h (P+25)h (# addressable locations, including this field)
(P+26)h (P+26)h Number of identical partitions w ithin the partition region
(P+27)h (P+27)h
(P+28)h (P+28)h Number of program or erase operations allow ed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
2
12E:
12F
130:
131:
132:
2
1
(P+29)h (P+29)h Simultaneous programor erase operations allow ed in other partitions w hile a
partition in this region is in Program mode
1
1
1
133:
134:
135:
133:
134:
135:
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+2A)h (P+2A)h Simultaneous programor erase operations allow ed in other partitions w hile a
partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+2B)h (P+2B)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w / contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Datasheet
68
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 39: Partition Region 1 Information (Sheet 2 of 2)
Offset(1)
See table below
Address
P = 10Ah
Bottom Top
Description
(Optional flash features and commands)
Bot
Top
136:
137:
138:
139:
13A:
13B:
13C:
Len
(P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information
4
136:
137:
138:
139:
13A:
13B:
13C:
(P+2D)h (P+2D)h
(P+2E)h (P+2E)h
(P+2F)h (P+2F)h
(P+30)h (P+30)h Partition 1 (Erase Block Type 1)
(P+31)h (P+31)h Block erase cycles x 1000
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2
1
(P+32)h (P+32)h Partition 1 (erase block Type 1) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+33)h (P+33)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities
defined in Table 10.
1
6
13D:
13D:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition Region 1 (Erase Block Type 1) Programming Region Information
(P+34)h (P+34)h
(P+35)h (P+35)h
(P+36)h (P+36)h
(P+37)h (P+37)h
(P+38)h (P+38)h
(P+39)h (P+39)h
bits 0–7 = x, 2^x = Programming Region aligned size (
)
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
bytes
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode
bits 24-31 = Reserved
size in bytes
valid
bits 32-39 = z = Control Mode
size in bytes
invalid
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
(P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information
4
(P+3B)h (P+3B)h
(P+3C)h (P+3C)h
(P+3D)h (P+3D)h
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+3E)h (P+3E)h Partition 1 (Erase Block Type 2)
(P+3F)h (P+3F)h Block erase cycles x 1000
2
1
(P+40)h (P+40)h Partition 1 (erase block Type 2) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+41)h (P+41)h Partition 1 (erase block Type 2) page mode and synchronous mode capabilities
defined in Table 10.
1
6
14B:
14B:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
Partition Region 1 (Erase Block Type 2) Programming Region Information
(P+42)h (P+42)h
(P+43)h (P+43)h
(P+44)h (P+44)h
(P+45)h (P+45)h
(P+46)h (P+46)h
(P+47)h (P+47)h
bits 0–7 = x, 2^x = Programming Region aligned size (
)
14C:
14D:
14E:
14F:
150:
151:
bytes
14C:
14D:
14E:
14F:
150:
151:
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode
bits 24-31 = Reserved
size in bytes
valid
bits 32-39 = z = Control Mode
size in bytes
invalid
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
Datasheet
69
Jul 2011
OrderNumber:208034-04
P33-65nm
Table 40: Partition and Erase Block Region Information
64-Mbit
128-Mbit
Add
-B
-T
-B
-T
12D:
12E:
12F:
130:
131:
132:
133:
134:
135:
136:
137:
138:
139:
13A:
13B:
13C:
13D:
13E:
13F:
140:
141:
142
-01
-24
-00
-01
-00
-11
-00
-00
-02
-03
-00
-80
-00
-64
-00
-02
-03
-00
-80
-00
-00
-00
-80
-3E
-00
-00
-02
-64
-00
-02
-03
-00
-80
-00
-00
-00
-80
-01
-24
-00
-01
-00
-11
-00
-00
-02
-3E
-00
-00
-02
-64
-00
-02
-03
-00
-80
-00
-00
-00
-80
-03
-00
-80
-00
-64
-00
-02
-03
-00
-80
-00
-00
-00
-80
-01
-24
-00
-01
-00
-11
-00
-00
-02
-03
-00
-80
-00
-64
-00
-02
-03
-00
-80
-00
-00
-00
-80
-7E
-00
-00
-02
-64
-00
-02
-03
-00
-80
-00
-00
-00
-80
-01
-24
-00
-01
-00
-11
-00
-00
-02
-7E
-00
-00
-02
-64
-00
-02
-03
-00
-80
-00
-00
-00
-80
-03
-00
-80
-00
-64
-00
-02
-03
-00
-80
-00
-00
-00
-80
143:
144:
145:
146:
147:
148:
149:
14A:
14B:
14C:
14D:
14E:
14F:
150:
151:
Datasheet
70
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 41: CFI Link Information
Description
(Optional flash features and commands)
Hex
Code
Length
Add.
Value
CFI Link Field bit definitions
152:
153:
154:
155:
Bits 0-9 = Address offset (within 32Mbit segment) of referenced CFI table
Bits 10-27 = nth 32Mbit segment of referenced CFI table
Bits 28-30 = Memory Type
4
1
-FF
Bit 31 = Another CFI Link field immediately follows
CFI Link Field Quantity Subfield definitions
Bits 0-3 = Quantity field (n such that n+1 equals quantity)
Bit 4 = Table & Die relative location
156:
-FF
Bit 5 = Link Field & Table relative location
Bits 6-7 = Reserved
Datasheet
71
Jul 2011
OrderNumber:208034-04
P33-65nm
A.2
Flowcharts
Figure 29: Word Program Flowchart
Start
Command Cycle
- Issue Program Command
- Address = location to program
- Data = 0x40
Data Cycle
- Address = location to program
- Data = Data to program
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal D7
No
No
Program Suspend
See Suspend/
Resume Flowchart
No
D7 = '1'
?
Suspend
?
Errors
?
Yes
Yes
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
Error-Handler
User Defined Routine
End
Datasheet
72
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 30: Program Suspend/Resume Flowchart
PROGRAM SUSPEND /RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read Status
Read
Data= 70h
Write
Write
Status Addr= Block to suspend(BA)
Write70h
Any Address
Program Data= B0h
Suspend Addr= X
Program Suspend
Write B0h
Any Address
Status register data
Initiate a read cycle to update Status
register
Read
Read Status
Register
Addr= Suspended block (BA)
Check SR.7
Standby
Standby
1= WSM ready
0= WSM busy
0
0
SR.7=
1
Check SR.2
1= Program suspended
0= Program completed
Program
Completed
SR.2 =
1
Read
Array
Data= FFh
Addr= Block address to read(BA)
Write
Read
Write
Read Array
Write FFh
Any Address
Read array data from block other than
the one being programmed
Read Array
Data
Program Data= D0h
Resume Addr= Suspended block (BA)
Done
No
Reading
Yes
Program Resume
Read Array
Write FFh
Write D0h
Any Address
Program
Resumed
Read Array
Data
Read Status
Write70h
Any Address
PGM_SUS. WMF
Datasheet
73
Jul 2011
OrderNumber:208034-04
P33-65nm
Figure 31: Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Bus
Operation
Command
Comments
Write 0x70,
Any device Address
(Read Status)
Read
Status
Data = 0x70
Addr = Any device address
Write
Write
Read
Write 0xB0,
Any device
address
Erase
Data = 0xB0
(Erase Suspend)
Suspend Addr = Any device address
Status Register data .
None
Addr = Any device address
Read Status
Register
Check SR[7]:
Idle
None
None
1 = WSM ready
0 = WSM busy
0
SR[7] =
1
Check SR[6]:
1 = Erase suspended
0 = Erase completed
Idle
0
Erase
Completed
SR[6] =
1
Data = 0xFF or 0x40
Addr = Any address within the
suspended device
Read Array
or Program
Write
Read or
Write
Read array or program data from /to
block other than the one being erased
Read
Program
None
Read or
Program?
Read Array
Data
Program
Loop
Erase
Data = 0xD0
Write
No
Resume Addr = Any device address
Done
Yes
If the suspended partition was placed in
Read Array mode or a Program Loop :
Read
Status
Return device to Status mode :
Data = 0x70
Write
Write 0xD0,
Any Address
(Erase Resume)
Register Addr = Any device Address
Write 0xFF,
Any device
Address
Erase
(Read Array)
Resumed(1)
Note:
Read Array
Data
1. The tERS/SUSP timing between the initial block erase or erase
resume command and a subsequent erase suspend command
should be followed .
Write 0x70,
Any device
Address
(Read Status)
Datasheet
74
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 32: Buffer Program Flowchart
Start
Bus
Operation
Command
Comments
Data=E8H
Write to
Buffer
Write
Device
Supports Buffer
Writes?
Addr= Block Address
Use Single Word
Programming
No
SR. 7 = Valid
Addr= Block Address
Read
(Note7)
Yes
Check SR.7
1 = Device WSM is Busy
0 = Device WSM is Ready
Set Timeout or
Loop Counter
Standby
Yes
Data=N- 1 = Word Count
N = 0 corresponds to coun=t1
Addr= Block Address
Write
( Notes1,2)
Clear Status Register
50h
Address within Device
Write
( Notes3,4)
Data= Write Buffer Data
Addr= Start Address
Get Next
Target Address
Write
Data= Write Buffer Data
( Notes5,6)
Addr=Addresswithin buffer range
Issue Write to Buffer
Command E8h
Block Address
Program
Confirm
Data=D0H
Addr= Block Address
Write
Read
Status register Data
CE# and OE# low updates SR
Addr= Block Address
Read Status Register
Block Address
(note7)
Check SR.7
1 = WSM Ready
0 = WSM Busy
No
Standby
Notes:
Timeout
or Count
Expired ?
0 = No
Is WSM Ready?
SR. 7=
Yes
1. Word count values on DQ-DQ15 are loaded into the Count
.
0
register. Count ranges for this device are N=0000h to00FFh.
1 =Yes
2. The device outputs theStatusRegister when read.
Write Word Count
Block Address
3. Write Buffer contents will be programmed at the device start
address or destination flash addres.s
Write Buffer Data
Start Address
X = X +1
4. Align the start address on a Write Buffer boundary for
maximum programming performance(i.e., A8-A1 of the start
address=0).
Write Buffer Data
Addresswithin buffer range
.
X =0
5. The device aborts the Buffered Program command if the
current address is outside the original block addres.s
No
.
6. The Status register indicates an “improper command
Sequence” if the Buffered Program command is aborte.d
Follow this with a Clear Status Register comman.d
No
Abort Bufferred
Program?
X =N?
Yes
Yes
7. The device defaults to output SR data after the Buffered
Programming Setup Command(E8h) is issued. CE# or OE#
must be be toggled to update Status Registe. rDon’t issue the
Read SR command(70h), which would be interpreted by the
internalstate machine as Buffer Word Coun.t
Write Confirm D0h
Block Address
Write to another
Block Address
Buffered Program
Aborted
8. Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation to
reset the device to read array mode.
Read Status Register
No
Suspend
Program
Loop
Yes
Suspend
Program
0
SR. 7=?
1
Full Status
Check if Desired
Yes
Another Buffered
Programming?
No
Program Complete
Datasheet
75
Jul 2011
OrderNumber:208034-04
P33-65nm
Figure 33: BEFP Flowchart
Setup Phase
Start
Program/Verify Phase
Exit Phase
Read Status
Register
Read Status
Register
A
B
Issue BEFP Setup Cmd
(Data = 0x80)
No (SR.0=1)
Buffer Ready ?
No (SR.7=0)
BEFP Exited ?
Issue BEFP Confirm Cmd
(Data = 00D0h)
Yes (SR.0=0)
Write Data Word to Buffer
Yes (SR.7=1)
BEFP
Setup
Delay
Full Status
Register check for
errors
No
Buffer Full ?
Yes
Read Status
Register
Finish
Read Status
Register
Yes (SR.7=0)
BEFP Setup
Done ?
A
No (SR.0=1)
No (SR.7=1)
Program
Done ?
SR Error Handler
(User-Defined)
Yes (SR.0=0)
Exit
Program
Yes
More Data ?
No
Write 0xFFFFh outside Block
B
Datasheet
76
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 34: Block Erase Flowchart
Start
Command Cycle
- Issue Erase command
- Address = Block to be erased
- Data = 0x20
Confirm Cycle
- Issue Confirm command
- Address = Block to be erased
- Data = Erase confirm (0xD0)
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal SR.7
No
No
Erase Suspend
See Suspend/
Resume Flowchart
Yes
No
SR.7 = '1'
?
Suspend
?
Errors
?
Yes
Yes
Error-Handler
User Defined Routine
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
End
Datasheet
77
Jul 2011
OrderNumber:208034-04
P33-65nm
Figure 35: Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Bus
Operation
Start
Command
Comments
Lock Setup
Write 60h
Block Address
Lock
Setup
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Write
Write
Lock,
Unlock, or
Lockdown
Data = 01h (Lock block)
D0h (Unlock block)
Lock Confirm
Write 01,D0,2Fh
Block Address
2Fh (Lockdown block)
Confirm Addr = Block to lock/unlock/lock-down (BA)
Read ID Plane
Write 90h
Write
(Optional)
Read ID Data = 90h
Plane
Addr = Block address offset+2 (BA+2)
Read
(Optional)
Block Lock Block Lock status data
Status Addr = Block address offset+2 (BA+2)
Read Block Lock
Status
Confirm locking change on DQ1, DQ0.
(See Block Locking State Transitions Table
for valid combinations.)
Standby
(Optional)
Locking
Change?
No
Yes
Read
Array
Data = FFh
Addr = Block address (BA)
Write
Read Array
Write FFh
Any Address
Lock Change
Complete
LOCK_OP.WMF
Datasheet
78
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Figure 36: OTP Register Programming Flowchart
Start
OTP Program Setup
- Write 0xC0
- OTP Address
Confirm Data
- Write OTP Address and Data
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal SR.7
No
SR.7 = '1'
?
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
End
Datasheet
79
Jul 2011
OrderNumber:208034-04
P33-65nm
Figure 37: Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any device address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
No
SR7 = '1'
Yes
Yes
- Set/Reset
by WSM
Erase Suspend
See Suspend/Resume Flowchart
SR6 = '1'
No
Yes
Program Suspend
See Suspend/Resume Flowchart
SR2 = '1'
No
Error
Command Sequence
Yes
Yes
SR5 = '1'
SR4 = '1'
No
No
Error
Erase Failure
Yes
Error
Program Failure
SR4 = '1'
No
- Set by WSM
- Reset by user
- See Clear Status
Register Command
Yes
Error
< VPENLK/PPLK
SR3 = '1'
VPEN/PP
No
Yes
Error
Block Locked
SR1 = '1'
No
End
Datasheet
80
Jul 2011
Order Number: 208034-04
P33-65nm SBC
A.3
Write State Machine
Show here are the command state transitions (Next State Table) based on incoming
commands. Only one partition can be actively programming or erasing at a time. Each
partition stays in its last read state (Read Array, Read Device ID, Read CFI or Read
Status Register) until a new command changes it. The next WSM state does not depend
on the partition’s output state.
Note:
IS refers to Illegal State in the Next State Tables.
Table 42: Next State Table for P3x-65nm (Sheet 1 of 3)
Command Input and Resulting Chip Next State(1)
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
N/A
N/A
N/A
N/A
Ready
Ready
Ready
Ready
(Lock
Error
[Botc
h])
Ready
Ready
(Lock
Block
)
(Lock Ready
down (Set
Block CR)
)
Ready (Lock
Error [Botch])
Ready (Lock Error
[Botch])
Lock/RCR/ECR Setup
Ready (Lock Error [Botch])
Setup
OTP Busy
IS in
OTP Busy
N/A
N/A
OTP Busy
OTP Busy
N/A
Ready
N/A
OTP
IS in OTP
Busy
Illegal State in OTP
Busy
Busy
OTP
OTP Busy
OTP Busy
OTP Busy
OTP
Busy
Busy
OTP Busy
IS in OTP Busy
Setup
OTP Busy
Word Program Busy
N/A
N/A
Pgm Busy
Pgm Busy
IS in
Pgm
Busy
IS in Pgm
Busy
Pgm Pgm
IS in Word Pgm
Busy
Busy
Pgm
Pgm Busy
Word Pgm Busy
Word Pgm Busy
Word Pgm Busy
Busy Susp
Ready
Busy
IS in Pgm Busy
Word
Program
Pgm
IS in
Pgm
Susp
Susp Word
Pgm
Susp
Pgm
Suspend
IS in Pgm
Susp
Pgm
Busy
Illegal State in Pgm
Suspend
Word Program
Suspend
Suspend
Pgm Susp
(Er
Pgm
N/A
Word Pgm Susp
bits Susp
clear)
N/A
N/A
IS in Pgm
Suspend
EFI Setup
Sub-function
Setup
Sub-op-code
Load 1
Word Program Suspend
Sub-function Setup
Sub-op-code Load 1
Sub-function Load 2 if word count >0, else Sub-function confirm
Sub-function
Load 2
Sub-function
Confirm
Sub-function Confirm if data load in program buffer is complete, ELSE Sub-function Load 2
S-fn
Ready (Error [Botch])
Ready (Error [Botch])
Busy
EFI
IS in
S-fn
Busy
Sub-function
S-fn
Illegal State S-fn S-fn
in S-fn Busy Busy Susp
S-fn Busy
S-fn Busy
IS in S-fn Busy
S-fn Busy
S-fn Busy
S-fn Susp
Busy
Busy
Ready
N/A
IS in Sub-
function Busy
Sub-function Busy
S-fn
IS in
Susp
Sub-function
Susp
S-fn
Susp
Illegal State S-fn
in S-fn Busy Busy
S-fn
Suspend
S-fn
S-fn Sub-function
Susp
(Er
bits
clear)
IS in S-fn Susp
S-fn Suspend
N/A
Susp
IS in S-fn Susp
Sub-function Suspend
Datasheet
81
Jul 2011
OrderNumber:208034-04
P33-65nm
Table 42: Next State Table for P3x-65nm (Sheet 2 of 3)
Command Input and Resulting Chip Next State(1)
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
Setup
BP Load 1
BP Load 1
(8)
BP Load 2 if word count >0, else BP confirm
BP Confirm if data
load in program
buffer is
complete, else BP
load 2
Ready
(Error
[Botc
h])
N/A
(8)
BP Load 2
BP Confirm if data load in program buffer is complete, ELSE BP load 2
BP
BP Confirm
Ready (Error [Botch])
Ready (Error [Botch])
Buffer
Busy
Pgm
IS in
BP
Busy
BP
Busy
Illegal State
BP
BP
BP Busy
BP Busy
BP Busy
BP Busy
IS in BP Busy
BP Busy
BP Busy
BP Susp
(BP)
in BP Busy Busy Susp
Ready
N/A
IS in BP Busy
BP Susp
BP
Susp
(Er
IS in
BP
Susp
BP
Susp
Illegal State
in BP Busy Busy
BP
BP
Susp
BP Suspend
BP Suspend
IS in BP Susp
BP Suspend
N/A
bits
clear)
IS in BP Susp
Setup
BP Suspend
Erase
Ready (Err
Botch0])
Ready (Error [Botch])
Ready (Error [Botch])
N/A
N/A
Busy
N/A
IS in
Erase
Busy
IS in Erase Erase Erase
Busy Busy Susp
Busy
Erase Erase Busy
Busy
Erase Busy
IS in Erase Busy
Erase Busy
Ers Busy
IS in Erase Busy
Erase Busy
Ready
Lock/
RCR/
ECR
Erase
Word
Pgm
EFI
Setup
in
BP
Setup
in
Erase
Susp
IS in
Erase
Susp
Erase Setup
IS in Erase Erase
Erase
Erase
Susp
Erase
Susp
Suspend
(Er
bits
Setup
in
Erase Suspend
N/A
N/A
Erase Susp
Susp
in
Erase
Susp
Erase
Susp
Suspend
Busy
Suspend
N/A
N/A
Erase
Susp
clear)
Erase
Susp
Erase Suspend
IS in Erase Susp
Setup
Word Pgm busy in Erase Suspend
Word
Pgm
busy
in
Erase
Susp
Word
Word
Pgm
Pgm
IS in
Pgm
busy
Word Pgm
busy in
IS in Word
Pgm busy in
Ers Susp
busy
in
Word Pgm busy in
Erase Susp
IS in Word Pgm
busy in Ers Susp
Word Pgm busy in
Erase Susp
Erase
Susp
Busy
Susp
in Ers
Susp
in Ers Erase Susp
Susp
Erase
Susp
Illegal state(IS)
IS in
Ers
Word Pgm Busy in
Ers Suspend
in Pgm busy in
Word Pgm busy in Erase Suspend
Word
Word
Erase Suspend
Susp
Pgm in
Erase
Suspend
Suspend
Word
Pgm
Susp
in Ers
Susp
(Er
Word iS in
Pgm pgm
Word Word
Pgm Pgm
susp susp
in Ers in Ers
susp susp
Word
Pgm
susp
in Ers
susp
Pgm
busy
in
Erase
Susp
Word Pgm
iS in pgm
susp in Ers
Susp
iS in Word Pgm
susp in Ers Susp
Word Pgm susp in
Ers susp
susp susp susp in Ers
N/A
in Ers in Ers
susp Susp
susp
N/A
bits
clear)
Illegal State in
Word Program
Suspend in Erase
Suspend
Word Pgm busy in Erase Suspend
BP Load 1 in Erase Suspend
Setup
(8)
BP Load 1
BP Load 2 in Erase Suspend if word count >0, else BP confirm
Ers
Susp
(Error
[Botc
h])
BP Confirm in
Erase Suspend
when count=0,
ELSE BP load 2
N/A
(8)
BP Load 2
BP Confirming Erase Suspend if data load in program buffer is complete, ELSE BP load 2 in Erase Suspend
BP Confirm
Erase Suspend (Error [BotchBP])
IS in
Erase Susp (Error [Botch BP])
IS in BP Busy in
BP Busy in Ers Susp N/A
BP
BP
BP
Busy
in Ers
Susp
BP
Illegal State
in BP Busy in
Ers Susp
Busy
in Ers
Susp
BP Busy in
Erase Susp
Susp
in Ers
Susp
BP Busy in Ers
Susp
Erase
Susp
BP in
Erase
Suspend
BP Busy
Busy
in Ers
Susp
BP Busy in Ers Susp
Erase Suspend
IS in
Ers
Susp
IS in BP Busy
BP Busy in Erase Suspend
BP
IS in
BP
Susp
in Ers
Susp
Susp
BP
BP
BP
BP Suspend Illegal State
in Ers
Susp
in Ers
Susp
Busy BP Susp in
Susp
in Ers
Susp
IS in BP Busy in
Erase Suspend
BP Susp in Ers
Susp
BP Susp
in Erase
Suspend
in BP Busy in
Ers Susp
Susp
(Er
BP Susp in Ers Susp N/A
in Ers
Susp
Ers Susp
N/A
bits
clear)
IS in BP Suspend
BP Suspend in Erase Suspend
Datasheet
82
Jul 2011
Order Number: 208034-04
P33-65nm SBC
Table 42: Next State Table for P3x-65nm (Sheet 3 of 3)
Command Input and Resulting Chip Next State(1)
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
EFI Setup
Sub-function Setup in Erase Suspend
Sub-function
Setup
Sub-op-code Load 1 in Erase Suspend
Sub-op-code
Load 1
Sub-function Load 2 in Erase Suspend if word count >0, else Sub-function confirm in Erase Suspend
Ers
Sub-function
Confirm if data
N/A
Susp load in program
Sub-function
Load 2
Sub-function Confirm in Erase Suspend if data load in program buffer is complete, ELSE Sub-function Load 2
(Error
buffer is
[Botc complete, ELSE
h])
Sub-function
Load 2
Sub-function
Erase Suspend (Error [Botch])
IS in
Erase Suspend (Error [Botch])
Confirm
EFI in
S-fn
Busy
in Ers
Susp
S-fn
Busy
in Ers
Susp
S-fn
Susp
in Ers
Susp
Erase
Suspend
S-fn
Busy
in Ers
Susp
Illegal State
Sub-function
Busy
S-fn Busy in
Ers Suspend
S-fn Busy in Ers
Susp
IS in S-fn Busy in
Ers Susp
S-fn Busy in Ers
S-fn Busy in Ers Erase
in S-fn Busy
in Ers Susp
N/A
Susp
Susp
Susp
IS in
Ers
IS in Sub-
Sub-function Busy in Ers Susp
S-fn
function Busy
Susp
IS in
S-fn
Susp
S-fn
in Ers
Susp IS in S-fn Susp in S-fn Suspend in Ers
S-fn
Susp
in Ers
Susp
S-fn
Busy
in Ers
Susp
S-fn
Illegal State
S-fn
Sub-function
Susp
S-fn Susp in Ers
Susp
Susp Suspend in in S-fn Busy
Suspend in Susp
N/A
in Ers
Susp
Ers Susp
Susp
in Ers
Susp
Ers Susp
in Ers Susp
Ers Susp
(Er
bits
N/A
clear)
IS in Phase-1
Susp
Sub-Function Suspend in Erase Suspend
Ers
Susp
(Un-
lock
Block
)
Ers
Ers
Susp
Blk
Ers
Susp
Blk
Ers
Susp
CR
Lock/RCR/ECR/Lock
EFA Block Setup in
Erase Suspend
Susp
(Error
[Botc
h])
Erase Suspend (Lock Error
[Botch])
Ers Susp (Error
[Botch])
Ers Susp (Lock Error [Botch])
N/A
N/A
N/A
Lk-
Lock
Set
Down
BC
Busy
Ready (Error
[Botch])
Setup
Ready (Error [Botch])
IS in
Ready (Error [Botch])
IS in BC Busy
N/A
Blank
BC
IS in BC
Busy
Blank Check Busy
Check
BC
Busy
BC Busy
Blank Check Busy
BP Busy
BC Busy
Busy
BC Busy
Ready
IS in Blank Check
Busy
BEFP
Load
Data
Setup
Ready (Error [Botch])
Ready (Error [Botch])
N/A
BEFP
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands
treated as data. (7)
BEFP Busy
Ready
BEFP Busy
Ready
Datasheet
83
Jul 2011
OrderNumber:208034-04
P33-65nm
Table 43: Output Next State Table for P3x-65nm
Command Input to Chip and Resulting Output MUX Next State(1)
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
BEFPSetup,
BEFP Pgm & Verify Busy,
Erase Setup,
OTP Setup,
BP Setup, Load 1, Load 2
BP Setup, Load1, Load 2 - in
Erase Susp.
BP Confirm
EFI Sub-function Confirm
WordPgmSetup,
Word Pgm Setup in Erase
Susp,
Status Read
BP Confirm in Erase Suspend,
EFI S-fn Confirm in Ers Susp,
Blank Check Setup,
Blank Check Busy
Lock/RCR/ECR Setup,
Lock/RCR/ECR Setup in Erase
Susp
Status Read
EFI S-fn Setup, Ld 1, Ld 2
EFI S-fn Setup, Ld1, Ld 2 - in
Erase Susp.
Output MUX will not change
BP Busy
BP Busy in Erase Suspend
EFI Sub-function Busy
EFI Sub-fn Busy in Ers Susp
Word Program Busy,
Word Pgm Busy in Erase
Suspend,
Status Read
OTP Busy
Erase Busy
Ready,
Word Pgm Suspend,
BP Suspend,
Erase Suspend,
BP Suspend in Erase Suspend
Status Read
Status Read
Status Read
Notes:
1.
2.
3.
4.
IS refers to Illegal State in the Next State Table.
“Illegal commands” include commands outside of the allowed command set.
The device defaults to "Read Array" on powerup.
If a “Read Array” is attempted when the device is busy, the result will be “garbage” data (we should not tell the user that
it will actually be Status Register data). The key point is that the output mux will be pointing to the “array”, but garbage
data will be output. “Read ID” and "Read Query" commands do the exact same thing in the device. The ID and Query data
are located at different locations in the address map.
The Clear Status command only clears the error bits in the Status Register if the device is not in the following modes:1.
WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes) 2. Suspend states (Erase
Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend).
5.
6.
7.
BEFP writes are only allowed when the Status Register bit #0 = 0 or else the data is ignored.
Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register and Blank Check) perform the
operation and then move to the Ready State.
8.
9.
Buffered programming will botch when a different block address (as compared to the address given on the first data write
cycle) is written during the BP Load1 and BP Load2 states.
All two cycle commands will be considered as a contiguous whole during device suspend states. Individual commands will
not be parsed separately. (I.e. If an erase set-up command is issued followed by a D0h command, the D0h command will
not resume the program operation. Issuing the erase set-up places the CUI in an “illegal state”. A subsequent command
will clear the “illegal state”, but the command will be otherwise ignored.
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Order Number: 208034-04
P33-65nm SBC
Appendix B Conventions - Additional Documentation
B.1
Acronyms
BEFP:
CUI :
CFI :
EFI :
SBC :
OTP :
PLR :
PR :
Buffered Enhanced Factory Programming
Command User Interface
Common Flash Interface
Extended Function Interface
Single Bit per Cell
One-Time Programmable
one-time programmable Lock Register
one-time programmable Register
Read Configuration Register
Reserved for Future Use
Status Register
RCR :
RFU :
SR :
SRD
Status Register Data
WSM
Write State Machine
B.2
Definitions and Terms
VCC :
Signal or voltage connection
VCC
h :
:
Signal or voltage level
Hexadecimal number suffix
0b :
0x :
Binary number prefix
hexadecimal number prefix
SR.4 :
Denotes an individual register bit.
Denotes a group of similarly named signals, such as address or data bus.
A[15:0] :
Denotes one element of a signal group membership, such as an individual address
bit.
A5 :
Bit :
Single Binary unit
Byte :
Word :
Kbit :
KByte :
KWord :
Mbit :
MByte :
MWord :
K
Eight bits
Two bytes, or sixteen bits
1024 bits
1024 bytes
1024 words
1,048,576 bits
1,048,576 bytes
1,048,576 words
1,000
M
1,000,000
3.0 V :
9.0 V :
VCC (core) and VCCQ (I/O) voltage range of 2.3 V – 3.6 V
VPP voltage range of 8.5 V – 9.5 V
Datasheet
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P33-65nm
A group of bits, bytes, or words within the flash memory array that erase
simultaneously. The P33-65nm has two block sizes: 32 KByte and 128 KByte.
Block :
An array block that is usually used to store code and/or data. Main blocks are larger
than parameter blocks.
Main block :
An array block that may be used to store frequently changing data or small system
parameters that traditionally would be stored in EEPROM.
Parameter block :
Top parameter device :
Bottom parameter device :
A device with its parameter blocks located at the highest physical address of its
memory map.
A device with its parameter blocks located at the lowest physical address of its
memory map.
Datasheet
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Order Number: 208034-04
P33-65nm SBC
Appendix C Revision History
Date
Revision Description
Jul 2009
01
02
03
Initial release.
Update the buffered program performance, suspend latency, BEFP performance in Table 26,
“Program and Erase Specifications” on page 58
.
Update the 40Mhz spec for TSOP package in Table 24, “AC Read Specifications -” on
page 49
Add tDVWH timing comments in Table 25, “AC Write Specifications” on page 54
Reflect the program performance in CFI in Table 32, “System Interface Information”
.
Apr 2010
Jul 2010
.
on page 63
.
Ordering information update.
Update TSOP lead width “b” symbol.
Clarify CLK, WP#, WE# pin description.
Maximum rating note clarificaiton.
Update Table 14 EOWL of Latency count 2.
Update TSOP CFI on Burst read.
Jul 2011
04
Add invalid commands clarifications on 65nm.
Add a note on reset in Bus Operation to avoid invalid commands.
Update Micron Part catalog link.
Correct some other minor errors.
Datasheet
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Jul 2011
OrderNumber:208034-04
P33-65nm
Datasheet
88
Jul 2011
Order Number: 208034-04
相关型号：
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