RC28F800C3BC70 [INTEL]
Advanced+ Boot Block Flash Memory (C3); 高级+引导块闪存（ C3 ）
| 型号： | RC28F800C3BC70 |
| 厂家： | 
INTEL |
| 描述： | Advanced+ Boot Block Flash Memory (C3) |
| 文件： | 总68页 (文件大小：1132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
£
Intel Advanced+ Boot Block Flash
Memory (C3)
28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16)
Datasheet
Product Features
■ Flexible SmartVoltage Technology
—2.7 V– 3.6 V Read/Program/Erase
—12 V for Fast Production Programming
■ 128-bit Protection Register
—64 bit Unique Device Identifier
—64 bit User Programmable OTP Cells
■ 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option
■ Extended Cycling Capability
—Minimum 100,000 Block Erase Cycles
—Reduces Overall System Power
■ Software
■ High Performance
—Intel® Flash Data Integrator (FDI)
—Supports Top or Bottom Boot Storage,
Streaming Data (e.g., voice)
—Intel Basic Command Set
—Common Flash Interface (CFI)
—2.7 V– 3.6 V: 70 ns Max Access Time
■ Optimized Architecture for Code Plus
Data Storage
—Eight 4 Kword Blocks, Top or Bottom
Parameter Boot
■ Standard Surface Mount Packaging
—48-Ball µBGA*/VFBGA
—Up to One Hundred-Twenty-Seven 32
Kword Blocks
—Fast Program Suspend Capability
—Fast Erase Suspend Capability
—64-Ball Easy BGA Packages
—48-Lead TSOP Package
■ ETOX™ VIII (0.13 µm) Flash
■ Flexible Block Locking
Technology
—Lock/Unlock Any Block
—Full Protection on Power-Up
—WP# Pin for Hardware Block Protection
—16, 32 Mbit
■ ETOX™ VII (0.18 µm) Flash Technology
—16, 32, 64 Mbit
■ Low Power Consumption
—9 mA Typical Read
■ ETOX™ VI (0.25 µm) Flash Technology
—8, 16 and 32 Mbit
—7 A Typical Standby with Automatic
Power Savings Feature (APS)
■ Extended Temperature Operation
—–40 °C to +85 °C
The Intel® Advanced+ Book Block Flash Memory (C3) device, manufactured on Intel’s latest
0.13 µm and 0.18 µm technologies, represents a feature-rich solution for low-power applications.
The C3 device incorporates low-voltage capability (3 V read, program, and erase) with high-
speed, low-power operation. Flexible block locking allows any block to be independently locked
or unlocked. Add to this the Intel® Flash Data Integrator (FDI) software and you have a cost-
effective, flexible, monolithic code plus data storage solution. Intel® Advanced+ Boot Block Flash
Memory (C3) products will be available in 48-lead TSOP, 48-ball CSP, and 64-ball Easy BGA
packages. Additional information on this product family can be obtained by accessing the Intel®
Flash website: http://www.intel.com/design/flash.
Notice: This specification is subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
Order Number: 290645-017
October 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2003
*Third-party brands and names are the property of their respective owners.
2
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................7
1.1
1.2
1.3
Document Purpose...............................................................................................................7
Nomenclature .......................................................................................................................7
Conventions..........................................................................................................................7
2.0 Device Description ........................................................................................................................8
2.1
2.2
2.3
2.4
2.5
Product Overview .................................................................................................................8
Ballout Diagram ....................................................................................................................8
Signal Descriptions .............................................................................................................13
Block Diagram ....................................................................................................................14
Memory Map.......................................................................................................................15
3.0 Device Operations.......................................................................................................................17
3.1
Bus Operations ...................................................................................................................17
3.1.1 Read ......................................................................................................................17
3.1.2 Write ......................................................................................................................17
3.1.3 Output Disable .......................................................................................................17
3.1.4 Standby..................................................................................................................18
3.1.5 Reset .....................................................................................................................18
4.0 Modes of Operation.....................................................................................................................19
4.1
Read Mode .........................................................................................................................19
4.1.1 Read Array.............................................................................................................19
4.1.2 Read Identifier .......................................................................................................19
4.1.3 CFI Query ..............................................................................................................20
4.1.4 Read Status Register.............................................................................................20
4.1.4.1 Clear Status Register.............................................................................21
Program Mode ....................................................................................................................21
4.2.1 12-Volt Production Programming...........................................................................21
4.2.2 Suspending and Resuming Program.....................................................................22
Erase Mode ........................................................................................................................22
4.3.1 Suspending and Resuming Erase .........................................................................23
4.2
4.3
5.0 Security Modes ............................................................................................................................27
5.1
Flexible Block Locking ........................................................................................................27
5.1.1 Locking Operation..................................................................................................28
5.1.1.1 Locked State ..........................................................................................28
5.1.1.2 Unlocked State.......................................................................................28
5.1.1.3 Lock-Down State....................................................................................28
Reading Block-Lock Status.................................................................................................28
Locking Operations during Erase Suspend ........................................................................29
Status Register Error Checking ..........................................................................................29
128-Bit Protection Register.................................................................................................29
5.5.1 Reading the Protection Register............................................................................30
5.5.2 Programming the Protection Register....................................................................30
5.5.3 Locking the Protection Register.............................................................................30
5.2
5.3
5.4
5.5
5.6
V
PP Program and Erase Voltages ......................................................................................30
Datasheet
3
Contents
5.6.1 Program Protection................................................................................................ 31
6.0 Power Consumption.................................................................................................................... 32
6.1
6.2
6.3
6.4
6.5
Active Power (Program/Erase/Read).................................................................................. 32
Automatic Power Savings (APS) ........................................................................................32
Standby Power ................................................................................................................... 32
Deep Power-Down Mode.................................................................................................... 32
Power and Reset Considerations .......................................................................................33
6.5.1 Power-Up/Down Characteristics............................................................................33
6.5.2 RP# Connected to System Reset.......................................................................... 33
6.5.3 VCC, VPP and RP# Transitions ............................................................................33
Power Supply Decoupling................................................................................................... 34
6.6
7.0 Thermal and DC Characteristics................................................................................................ 34
7.1
7.2
7.3
7.4
Absolute Maximum Ratings................................................................................................ 34
Operating Conditions.......................................................................................................... 35
DC Current Characteristics................................................................................................. 35
DC Voltage Characteristics................................................................................................. 38
8.0 AC Characteristics ...................................................................................................................... 39
8.1
8.2
8.3
8.4
8.5
8.6
AC Read Characteristics .................................................................................................... 39
AC Write Characteristics..................................................................................................... 43
Erase and Program Timings............................................................................................... 47
Reset Specifications ........................................................................................................... 48
AC I/O Test Conditions....................................................................................................... 49
Device Capacitance............................................................................................................49
Appendix A Write State Machine States.............................................................................................50
Appendix B Flow Charts ......................................................................................................................52
Appendix C Common Flash Interface.................................................................................................58
Appendix D Mechanical Specifications..............................................................................................64
Appendix E Additional Information ....................................................................................................67
Appendix F Ordering Information.......................................................................................................68
4
Datasheet
Contents
Revision History
Date of
Version
Revision
Description
05/12/98
-001
Original version
48-Lead TSOP package diagram change
µBGA package diagrams change
32-Mbit ordering information change (Section 6)
CFI Query Structure Output Table Change (Table C2)
CFI Primary-Vendor Specific Extended Query Table Change for Optional
Features and Command Support change (Table C8)
Protection Register Address Change
07/21/98
-002
I
test conditions clarification (Section 4.3)
PPD
µBGA package top side mark information clarification (Section 6)
Byte-Wide Protection Register Address change
V
V
Specification change (Section 4.3)
Maximum Specification change (Section 4.3)
test conditions clarification (Section 4.3)
IH
IL
10/03/98
12/04/98
-003
-004
I
CCS
Added Command Sequence Error Note (Table 7)
Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash
Memory Family.
Added t
/t
and t
(Section 4.6)
BHWH BHEH
QVBL
Programming the Protection Register clarification (Section 3.4.2)
12/31/98
02/24/99
-005
-006
Removed all references to x8 configurations
Removed reference to 40-Lead TSOP from front page
Added Easy BGA package (Section 1.2)
Removed 1.8 V I/O references
Locking Operations Flowchart changed (Appendix B)
06/10/99
-007
Added t
(Section 4.6)
WHGL
CFI Primary Vendor-Specific Extended Query changed (Appendix C)
Max I changed to 25 µA
CCD
03/20/00
04/24/00
-008
-009
Table 10, added note indicating V Max = 3.3 V for 32-Mbit device
CC
Added specifications for 0.18 micron product offerings throughout document
Added 64-Mbit density
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the
faster product offering.
10/12/00
-010
Changed VccMax=3.3V reference to indicate that the affected product is the
0.25µm 32Mbit device.
Minor text edits throughout document.
Added 1.8v I/O operation documentation where applicable
Added TSOP PCN ‘Pin-1’ indicator information
Changed references in 8 x 8 BGA pinout diagrams from ‘GND’ to ‘Vssq’
Added ‘Vssq’ to Pin Descriptions Information
7/20/01
-011
Removed 0.4 µm references in DC characteristics table
Corrected 64Mb package Ordering Information from 48-uBGA to 48-VFBGA
Corrected ‘bottom’ parameter block sizes to on 8Mb device to 8 x 4KWords
Minor text edits throughout document
10/02/01
2/05/02
-012
-013
Added specifications for 0.13 micron product offerings throughout document
Corrected Iccw / Ippw / Icces /Ippes values.
Added mechanicals for 16Mb and 64Mb
Minor text edits throughout document.
Datasheet
5
Contents
Date of
Revision
Version
Description
Updated 64Mb product offerings.
Updated 16Mb product offerings.
4/05/02
-014
Revised and corrected DC Characteristics Table.
Added mechanicals for Easy BGA.
Minor text edits throughout document.
3/06/03
10/03
-016
-017
Complete technical update.
Corrected information in the Device Geometry Details table, address 0x34.
6
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
1.0
Introduction
1.1
Document Purpose
This datasheet contains the specifications for the Intel® Advanced+ Boot Block Flash Memory
(C3) device family. These flash memories add features such as instant block locking and protection
registers that can be used to enhance the security of systems.
1.2
Nomenclature
0x
0b
Hexadecimal prefix
Binary prefix
Byte
Word
Kword
Mword
Kb
8 bits
16 bits
1024 words
1,048,576 words
1024 bits
KB
1024 bytes
Mb
MB
1,048,576 bits
1,048,576 bytes
APS
CUI
OTP
PR
PRD
PLR
RFU
SR
Automatic Power Savings
Command User Interface
One Time Programmable
Protection Register
Protection Register Data
Protection Lock Register
Reserved for Future Use
Status Register
SRD
WSM
Status Register Data
Write State Machine
1.3
Conventions
The terms pin and signal are often used interchangeably to refer to the external signal connections
on the package. (ball is the term used for CSP).
Group Membership Brackets: Square brackets will be used to designate group membership or to
define a group of signals with similar function (i.e. A[21:1], SR[4:1])
Set: When referring to registers, the term set means the bit is a logical 1.
Clear: When referring to registers, the term clear means the bit is a logical 0.
Block: A group of bits (or words) that erase simultaneously with one block erase instruction.
Main Block: A block that contains 32 Kwords.
Parameter Block: A block that contains 4 Kwords.
Datasheet
7
£
Intel Advanced+ Boot Block Flash Memory (C3)
2.0
Device Description
This section provides an overview of the Intel® Advanced+ Boot Block Flash Memory (C3) device
features, packaging, signal naming, and device architecture.
2.1
Product Overview
The C3 device provides high-performance asynchronous reads in package-compatible densities
with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data
storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of
the device’s memory map. The rest of the memory array is grouped into 32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase
and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC and VPP can be tied
together for a simple, ultra-low-power design. In addition to I/O voltage flexibility, the dedicated
VPP input provides complete data protection when VPP ≤ VPPLK
.
The device features a 128-bit protection register enabling security techniques and data protection
schemes through a combination of factory-programmed and user-programmable OTP data
registers. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. Additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
A command User Interface(CUI) serves as the interface between the system processor and internal
operation of the device. A valid command sequence issued to the CUI initiates device automation.
An internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS), standby
mode, and deep power-down mode. The device automatically enters APS mode following read
cycle completion. Standby mode begins when the system deselects the flash memory by
deasserting CE#. The deep power-down mode begins when RP# is asserted, which deselects the
memory and places the outputs in a high-impedance state, producing ultra-low power savings.
Combined, these three power-savings features significantly enhanced power consumption
flexibility.
2.2
Ballout Diagram
The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball µBGA, and Easy BGA
packages. (Refer to Figure 1 on page 9, Figure 3 on page 11, and Figure 4 on page 12,
respectively.)
8
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 1. 48-Lead TSOP Package
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
A8
64 M
32 M
A21
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
Advanced+ Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
16 M
A2
A1
NOTES:
1. For lower densities, upper address should be treated as NC. For example, a 16-Mbit device will have NC on
Pins 9 and 10.
Datasheet
9
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 2. Mark for Pin-1 indicator on 48-Lead 8Mb, 16Mb and 32Mb TSOP
Current Mark:
New Mark:
£
Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Intel Advanced and Advanced + Boot Block
48L TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the
white triangle will continue to use a dimple as a Pin 1 indicator. There are no other changes in
package size, materials, functionality, customer handling, or manufacturability. Product will
continue to meet Intel stringent quality requirements. Products affected are Intel Ordering Codes
shown in Table 1.
Table 1. 48-Lead TSOP
Extended 64 Mbit
Extended 32 Mbit
Extended 16 Mbit
Extended 8 Mbit
TE28F800C3TA90
TE28F160C3TD70
TE28F160C3BD70
TE28F640C3TC80
TE28F640C3BC80
TE28F320C3TD70
TE28F320C3BD70
TE28F800C3BA90
TE28F160C3TC80
TE28F160C3BC80
TE28F800C3TA110
TE28F800C3BA110
TE28F320C3TC70
TE28F320C3BC70
TE28F320C3TC90
TE28F320C3BC90
TE28F160C3TA90
TE28F160C3BA90
TE28F320C3TA100
TE28F320C3BA100
TE28F160C3TA110
TE28F160C3BA110
TE28F320C3TA110
TE28F320C3BA110
10
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 3. 48-Ball µBGA* and 48-Ball Very Fine Pitch BGA (VF BGA) Chip Size Package
(Top View, Ball Down)1,2,3
1
2
3
4
5
6
7
8
16M
A
B
C
D
E
F
A13
A11
A8
VPP
WP#
A19
A7
A4
A14
A15
A10
A12
D14
D15
D7
WE#
A9
RP#
A21
D11
D12
D4
A18
A20
D2
A17
A6
A5
A3
A2
A1
64M
32M
A16
D5
D8
CE#
D0
A0
VCCQ
GND
D6
D3
D9
GND
OE#
D13
VCC
D10
D1
NOTES:
1. Shaded connections indicate the upgrade address connections. Routing is not recommended in this area.
2. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
3. Unused address balls are not populated.
Datasheet
11
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 4. 64-Ball Easy BGA Package1,2
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
C
A
B
C
A1
A6 A18 VPP VCC GND A10 A15
A15 A10 GND VCC VPP A18 A6
A1
(1)
(1)
(1)
(1)
A2 A17 A19 RP# DU A20
A11 A14
A12 A13
A14 A11 A20
DU RP# A19
A17 A2
(1)
(1)
A3
A4
A7 WP# WE# DU A21
A13 A12 A21
DU WE# WP# A7
A3
D
D
A5 DU DU DU DU A8 A9
A9
A8 DU DU DU DU A5 A4
E
F
E
F
DQ DQ DQ DQ DQ DQ DU DU
DU DU DQ DQ DQ DQ DQ DQ
8
1
9
3
12
6
6
12
3
9
1
8
CE# DQ DQ DQ DQ DQ DU DU
DU DU DQ DQ DQ DQ
DQ
10
CE#
0
10
11
5
14
14
5
11
0
G
H
G
H
SSQ
SSQ
A0 VSSQ DQ DQ DQ DQ
V
A16
A16
V
D15 D13 DQ DQ VSSQ A0
4 2
2
4
13
15
(2)
(2)
A22 OE# VCCQ VCC VSSQ DQ VCCQ DU
DU VCCQ D7 VSSQ VCC VCCQ OE# A22
Bottom View - Ball Side
7
Top View
- Ball Side
NOTES:
1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
2. Unused address balls are not populated.
12
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
2.3
Signal Descriptions
Table 2 lists the active signals used and provides a brief description of each.
Table 2. Signal Descriptions
Symbol
Type
Name and Function
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
cycle.
8 Mbit: AMAX= A18
16 Mbit: AMAX = A19
32 Mbit: AMAX = A20
64 Mbit: AMAX = A21
A[MAX:0]
DQ[15:0]
INPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read
cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
OUTPUT internally latched. The data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
INPUT/
CHIP ENABLE: Active-low input. Activates the internal control logic, input buffers, decoders and sense
amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption
to standby levels.
CE#
OE#
INPUT
INPUT
OUTPUT ENABLE: Active-low input. Enables the device’s outputs through the data buffers during a
Read operation.
RESET/DEEP POWER-DOWN: Active-low input.
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to
High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
RP#
INPUT
INPUT
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to
logic-high, the device resets all blocks to locked and defaults to the read array mode.
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
the rising edge of the WE# pulse.
WE#
WRITE PROTECT: Active-low input.
When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot
be unlocked through software.
WP#
INPUT
When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are
now locked and can be unlocked and locked through software. After WP# goes low, any blocks
previously marked lock-down revert to the lock-down state.
See Section 5.0, “Security Modes” on page 27 for details on block locking.
PROGRAM/ERASE POWER SUPPLY: Operates as an input at logic levels to control complete device
protection. Supplies power for accelerated Program and Erase operations in 12 V ± 5% range. This pin
cannot be left floating.
Lower VPP ≤ VPPLK to protect all contents against Program and Erase commands.
INPUT/
POWER
Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can
drop as low as 1.65 V to allow for resistor or diode drop from the system supply.
VPP
Apply VPP to 12 V ± 5% for faster program and erase in a production environment. Applying 12 V ± 5%
to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the
boot blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 5.6 for
details on VPP voltage configurations.
VCC
VCCQ
GND
DU
POWER DEVICE CORE POWER SUPPLY: Supplies power for device operations.
OUTPUT POWER SUPPLY: Output-driven source voltage. This ball can be tied directly to VCC if
operating within VCC range.
POWER
POWER GROUND: For all internal circuitry. All ground inputs must be connected.
DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
-
NC
-
NO CONNECT: Pin must be left floating.
Datasheet
13
£
Intel Advanced+ Boot Block Flash Memory (C3)
2.4
Block Diagram
DQ 0-DQ15
V
CCQ
Output Buffer
Input Buffer
Identifier
Register
Status
Register
I/O Logic
CE#
WE#
OE#
Command
User
Interface
Power
Reduction
Control
Data
Comparator
RP#
WP#
Y-Decoder
Y-Gating/Sensing
Write State
Machine
Program/Erase
Voltage Switch
A[MAX:MIN]
Input Buffer
V
PP
Address
Latch
X-Decoder
V
CC
GND
Address
Counter
14
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
2.5
Memory Map
The C3 device is asymmetrically blocked, which enables system code and data integration within a
single flash device. The bulk of the array is divided into 32 Kword main blocks that can store code
or data, and 4 Kword boot blocks to facilitate storage of boot code or for frequently changing small
parameters. See Table 3, “Top Boot Memory Map” on page 15 and Table 4, “Bottom Boot Memory
Map” on page 16 for details.
Table 3. Top Boot Memory Map
8-Mbit
16-Mbit
Memory
Addressing
(HEX)
32-Mbit
Memory
Addressing
(HEX)
64-Mbit Memory
Addressing
(HEX)
Size
(KW)
Memory
Size
(KW)
Size
(KW)
Size
(KW)
Blk
Blk
Blk
Blk
Addressing
(HEX)
7F000-
7FFFF
1FF000-
1FFFFF
4
4
22
21
20
19
18
17
16
15
14
13
12
11
4
4
38
37
36
35
34
33
32
31
30
29
28
27
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
4
4
70
69
68
67
66
65
64
63
62
61
60
59
4
4
134
133
132
131
130
129
128
127
126
125
124
123
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
7E000-
7EFFF
1FE000-
1FEFFF
7D000-
7DFFF
1FD000-
1FDFFF
4
4
4
4
7C000-
7CFFF
1FC000-
1FCFFF
4
4
4
4
7B000-
7BFFF
1FB000-
1FBFFF
4
4
4
4
7A000-
7AFFF
1FA000-
1FAFFF
4
4
4
4
1F9000-
1F9FFF
4
79000-79FFF
78000-78FFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
4
4
4
1F8000-
1F8FFF
4
4
4
4
1F0000-
1F7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1E8000-
1EFFFF
1E0000-
1E7FFF
1D8000-
1DFFFF
...
32
32
32
...
2
...
...
...
2
...
...
...
2
...
...
...
2
...
10000-17FFF
8000-0FFFF
0000-07FFF
32
32
32
10000-17FFF
08000-0FFFF
00000-07FFF
32
32
32
10000-17FFF
08000-0FFFF
00000-07FFF
32
32
32
10000-17FFF
08000-0FFFF
00000-07FFF
1
1
1
1
0
0
0
0
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 4. Bottom Boot Memory Map
8-Mbit
Memory
Addressing
(HEX)
16-Mbit
Memory
Addressing
(HEX)
32-Mbit
Memory
Addressing
(HEX)
64-Mbit Memory
Addressing
(HEX)
Size
(KW)
Size
(KW)
Size
(KW)
Size
(KW)
Blk
Blk
Blk
Blk
32
32
32
32
...
32
32
32
4
22
21
20
19
...
10
9
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
...
32
32
32
32
...
32
32
32
4
38
37
36
35
...
10
9
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
...
32
32
32
32
...
32
32
32
4
70
69
68
67
...
10
9
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
...
32
32
32
32
.
134
133
132
131
...
10
9
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
...
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
32
32
32
4
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
8
8
8
8
7
7
7
7
4
6
4
6
4
6
4
6
4
5
4
5
4
5
4
5
4
4
4
4
4
4
4
4
4
3
4
3
4
3
4
3
4
2
4
2
4
2
4
2
4
1
4
1
4
1
4
1
4
0
4
0
4
0
4
0
16
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
3.0
Device Operations
The C3 device uses a CUI and automated algorithms to simplify Program and Erase operations.
The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and
programming.
The internal WSM completely automates Program and Erase operations while the CUI signals the
start of an operation and the status register reports device status. The CUI handles the WE#
interface to the data and address latches, as well as system status requests during WSM operation.
3.1
Bus Operations
The C3 device performs read, program, and erase operations in-system via the local CPU or
microcontroller. Four control pins (CE#, OE#, WE#, and RP#) manage the data flow in and out of
the flash device. Table 5 on page 17 summarizes these bus operations.
Table 5. Bus Operations
Mode
RP#
CE#
OE#
WE#
DQ[15:0]
Read
Write
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
X
VIL
VIH
VIH
X
VIH
VIL
VIH
X
DOUT
DIN
Output Disable
Standby
High-Z
High-Z
High-Z
Reset
X
X
NOTE: X = Don’t Care (VIL or VIH
)
3.1.1
Read
When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted.
CE# is the device selection control; when active low, it enables the flash memory device. OE# is
the data output control; when low, data is output on DQ[15:0]. See Figure 8, “Read Operation
Waveform” on page 42.
3.1.2
Write
A write cycle occurs when both CE# and WE# are low; RP# and OE# are high. Commands are
issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory
location. Address and data are latched on the rising edge of the WE# or CE# pulse, whichever
occurs first. See Figure 9, “Write Operations Waveform” on page 47.
3.1.3
Output Disable
With OE# at a logic-high level (V ), the device outputs are disabled. DQ[15:0] are placed in a
IH
high-impedance state.
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
3.1.4
3.1.5
Standby
Deselecting the device by bringing CE# to a logic-high level (V ) places the device in standby
IH
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during a Program or Erase operation, the device continues to consume active power
until the Program or Erase operation is complete.
Reset
From read mode, RP# at V for time t
impedance state, and turns off all internal circuits. After return from reset, a time t
deselects the memory, places output drivers in a high-
IL
PLPH
is required
PHQV
until the initial read-access outputs are valid. A delay (t
or t
) is required after return from
PHWL
PHEL
reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored.
The CUI resets to read-array mode, the status register is set to 0x80, and all blocks are locked. See
Figure 10, “Reset Operations Waveforms” on page 48.
If RP# is taken low for time t
during a Program or Erase operation, the operation will be
PLPH
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process which takes time
t
to complete.
PLRH
2. After time t
enter reset mode (if RP# is deasserted after t
on page 48.
, the part will either reset to read-array mode (if RP# is asserted during t
) or
PLRH
PLRH
). See Figure 10, “Reset Operations Waveforms”
PLRH
In both cases, after returning from an aborted operation, the relevant time t
must be observed before a Read or Write operation is initiated, as discussed in the previous
or t
/t
PHWL PHEL
PHQV
paragraph. However, in this case, these delays are referenced to the end of t
RP# goes high.
rather than when
PLRH
As with any automated device, it is important to assert RP# during a system reset. When the system
comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or Block-Erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the
flash memory may be providing status information instead of array data. Intel® Flash memories
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
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Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
4.0
Modes of Operation
4.1
Read Mode
The flash memory has four read modes (read array, read identifier, read status, and CFI query), and
two write modes (program and erase). Three additional modes (erase suspend to program, erase
suspend to read, and program suspend to read) are available only during suspended operations.
Table 7, “Command Bus Operations” on page 24 and Table 8, “Command Codes and
Descriptions” on page 25 summarize the commands used to reach these modes. Appendix A,
“Write State Machine States” on page 50 is a comprehensive chart showing the state transitions.
4.1.1
Read Array
When RP# transitions from V (reset) to V , the device defaults to read-array mode and will
IL
IH
respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
When the device is in read array mode, four control signals control data output.
• WE# must be logic high (V )
IH
• CE# must be logic low (V )
IL
• OE# must be logic low (V )
IL
• RP# must be logic high (V )
IH
In addition, the address of the desired location must be applied to the address pins. If the device is
not in read-array mode, as would be the case after a Program or Erase operation, the Read Array
command (0xFF) must be issued to the CUI before array reads can occur.
4.1.2
Read Identifier
The read-identifier mode outputs three types of information: the manufacturer/device identifier, the
block locking status, and the protection register. The device is switched to this mode by issuing the
Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 6
retrieve the specified information. To return to read-array mode, issue the Read Array command
(0xFF).
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 6. Device Identification Codes
Address1
Item
Data
Description
Base
Offset
Manufacturer ID
Block
0x00
0x0089
0x88C0
8-Mbit Top Boot Device
8-Mbit Bottom Boot Device
16-Mbit Top Boot Device
16-Mbit Bottom Boot Device
32-Mbit Top Boot Device
32-Mbit Bottom Boot Device
64-Mbit Top Boot Device
64-Mbit Bottom Boot Device
Block is unlocked
0x88C1
0x88C2
0x88C3
Device ID
Block
0x01
0x02
0x88C4
0x88C5
0x88CC
0x88CD
DQ0 = 0b0
DQ0 = 0b1
DQ1 = 0b0
DQ1 = 0b1
Lock Data
Block Lock Status2
Block
Block is locked
Block is not locked-down
Block is locked down
Block Lock-Down Status2
Block
Block
0x02
0x80
Protection Register Lock Status
Multiple reads required to read
Register Data the entire 128-bit Protection
Register.
0x81 -
0x88
Protection Register
Block
NOTES:
1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status
for block number 38 in a bottom boot device, set the address to 0x0F8000 plus the offset (0x02), i.e.
0x0F8002. Then examine DQ0 of the data to determine if the block is locked.
2. See Section 5.2, “Reading Block-Lock Status” on page 28 for valid lock status.
4.1.3
4.1.4
CFI Query
The CFI query mode outputs Common Flash Interface (CFI) data after issuing the Read Query
Command (0x98). The CFI data structure contains information such as block size, density,
command set, and electrical specifications. Once in this mode, read cycles from addresses shown in
Appendix C, “Common Flash Interface,” retrieve the specified information. To return to read-array
mode, issue the Read Array command (0xFF).
Read Status Register
The status register indicates the status of device operations, and the success/failure of that
operation. The Read Status Register (0x70) command causes subsequent reads to output data from
the status register until another command is issued. To return to reading from the array, issue a
Read Array (0xFF) command.
The status-register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 0x00 when a
Read Status Register command is issued.
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Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
The contents of the status register are latched on the falling edge of OE# or CE# (whichever occurs
last) which prevents possible bus errors that might occur if Status Register contents change while
being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register
will not indicate completion of a Program or Erase operation.
When the WSM is active, SR[7] will indicate the status of the WSM; the remaining bits in the
status register indicate whether the WSM was successful in performing the preferred operation (see
Table 9, “Status Register Bit Definition” on page 26).
4.1.4.1
Clear Status Register
The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7; but, the WSM
cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error
conditions, these bits can be cleared only through the Clear Status Register (0x50) command. By
allowing the system software to control the resetting of these bits, several operations may be
performed (such as cumulatively programming several addresses or erasing multiple blocks in
sequence) before reading the status register to determine if an error occurred during that series.
Clear the status register before beginning another command or sequence. The Read Array
command must be issued before data can be read from the memory array. Resetting the device also
clears the Status Register.
4.2
Program Mode
Programming is executed using a two-write cycle sequence. The Program Setup command (0x40)
is issued to the CUI followed by a second write which specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program preferred
bits of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If users attempt
to program “1”s, the memory cell contents do not change and no error occurs.
The Status Register indicates programming status. While the program sequence executes, status bit
7 is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the
only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the program-status bits should be checked. If the programming
operation was unsuccessful, bit SR[4] of the Status Register is set to indicate a program failure. If
SR[3] is set, then V was not within acceptable limits, and the WSM did not execute the program
PP
command. If SR[1] is set, a program operation was attempted on a locked block and the operation
was aborted.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, to prevent inadvertent status-register reads, be
sure to reset the CUI to read-array mode.
4.2.1
12-Volt Production Programming
When V is between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC
PP
pin. Note that if V is driven by a logic signal, V min = 1.65 V. That is, V must remain above
PP
IH
PP
1.65 V to perform in-system flash modifications. When V is connected to a 12 V power supply,
PP
the device draws program and erase current directly from the VPP pin. This eliminates the need for
an external switching transistor to control V . Figure 7 on page 31 shows examples of how the
PP
flash power supplies can be configured for various usage models.
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
The 12 V V mode enhances programming performance during the short period of time typically
PP
found in manufacturing processes; however, it is not intended for extended use. 12 V may be
applied to VPP during Program and Erase operations for a maximum of 1000 cycles on the main
blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80
hours maximum. Stressing the device beyond these limits may cause permanent damage.
4.2.2
Suspending and Resuming Program
The Program Suspend command halts an in-progress program operation so that data can be read
from other locations of memory. Once the programming process starts, issuing the Program
Suspend command to the CUI requests that the WSM suspend the program sequence at
predetermined points in the program algorithm. The device continues to output status-register data
after the Program Suspend command is issued. Polling status-register bits SR[7] and SR[2] will
determine when the program operation has been suspended (both will be set to “1”). t
/
WHRH1
t
specify the program-suspend latency.
EHRH1
A Read-Array command can now be issued to the CUI to read data from blocks other than that
which is suspended. The only other valid commands while program is suspended are Read Status
Register, Read Identifier, CFI Query, and Program Resume.
After the Program Resume command is issued to the flash memory, the WSM will continue with
the programming process and status register bits SR[2] and SR[7] will automatically be cleared.
The device automatically outputs status register data when read (see Figure 14, “Program Suspend
/ Resume Flowchart” on page 53) after the Program Resume command is issued. V must remain
PP
at the same V level used for program while in program-suspend mode. RP# must also remain at
PP
V .
IH
4.3
Erase Mode
To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
When the status register indicates that erasure is complete, check the erase-status bit to verify that
the Erase operation was successful. If the Erase operation was unsuccessful, SR[5] of the status
register will be set to a “1,” indicating an erase failure. If V was not within acceptable limits after
PP
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,
SR[5] of the status register is set to indicate an erase error, and SR[3] is set to a “1” to identify that
V
supply voltage was not within acceptable limits.
PP
After an Erase operation, clear the status register (0x50) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status-
register reads, it is advisable to place the flash in read-array mode after the erase is complete.
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Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
4.3.1
Suspending and Resuming Erase
Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in order to read data from—or program data to—
another block in memory. Once the erase sequence is started, issuing the Erase Suspend command
to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status
register will indicate if/when the Erase operation has been suspended. Erase-suspend latency is
specified by t
/t
.
WHRH2 EHRH2
A Read Array or Program command can now be issued to the CUI to read/program data from/to
blocks other than that which is suspended. This nested Program command can subsequently be
suspended to read yet another location. The only valid commands while Erase is suspended are
Read Status Register, Read Identifier, CFI Query, Program Setup, Program Resume, Erase
Resume, Lock Block, Unlock Block, and Lock-Down Block. During erase-suspend mode, the chip
can be placed in a pseudo-standby mode by taking CE# to V , which reduces active current
IH
consumption.
Erase Resume continues the erase sequence when CE# = V . Similar to the end of a standard
IL
Erase operation, the status register should be read and cleared before the next instruction is issued.
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 7. Command Bus Operations
First Bus Cycle
Addr
Second Bus Cycle
Command
Notes
Oper
Data
Oper
Addr
Data
Read Array
1,3
1,3
1,3
1,3
1,3
Write
Write
Write
Write
Write
X
X
X
X
X
0xFF
0x90
0x98
0x70
0x50
Read Identifier
Read
Read
Read
IA
QA
X
ID
QD
CFI Query
Read Status Register
Clear Status Register
SRD
0x40/
0x10
Program
2,3
Write
X
Write
Write
PA
BA
PD
Block Erase/Confirm
Program/Erase Suspend
Program/Erase Resume
Lock Block
1,3
1,3
1,3
1,3
1,3
1,3
1,3
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
X
0x20
0xB0
0xD0
0x60
0x60
0x60
0xC0
D0H
Write
Write
Write
Write
BA
BA
BA
PA
0x01
0xD0
0x2F
PD
Unlock Block
Lock-Down Block
Protection Program
X = "Don’t Care"
PA = Prog Addr
PD = Prog Data
BA = Block Addr
IA = Identifier Addr. QA = Query Addr.
SRD = Status Reg.
Data
ID = Identifier Data QD = Query Data
NOTES:
1. Following the Read Identifier or CFI Query commands, read operations output device identification data or
CFI query information, respectively. See Section 4.1.2 and Section 4.1.3.
2. Either 0x40 or 0x10 command is valid, but the Intel standard is 0x40.
3. When writing commands, the upper data bus [DQ8-DQ15] should be either VIL or VIH, to minimize current
draw.
Bus operations are defined in Table 5, “Bus Operations” on page 17.
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 8. Command Codes and Descriptions
Code
(HEX)
Device Mode
Command Description
This command places the device in read-array mode, which outputs array data on the data
pins.
FF
Read Array
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The
second cycle latches addresses and data information and initiates the WSM to execute the
Program algorithm. The flash outputs status-register data when CE# or OE# is toggled. A Read
Array command is required after programming to read array data. See Section 4.2, “Program
Mode” on page 21.
40
20
Program Set-Up
This is a two-cycle command. Prepares the CUI for the Erase Confirm command. If the next
command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of
the status register to a “1,” (b) place the device into the read-status-register mode, and (c) wait
for another command. See Section 4.3, “Erase Mode” on page 22.
Erase Set-Up
Erase Confirm
If the previous command was an Erase Set-Up command, then the CUI will close the address
and data latches and begin erasing the block indicated on the address pins. During program/
erase, the device will respond only to the Read Status Register, Program Suspend and Erase
Suspend commands, and will output status-register data when CE# or OE# is toggled.
D0
Program/Erase
Resume
If a Program or Erase operation was previously suspended, this command will resume that
operation.
If the previous command was Block Unlock Set-Up, the CUI will latch the address and unlock
the block indicated on the address pins. If the block had been previously set to Lock-Down, this
operation will have no effect. (See Section 5.1)
Unlock Block
Issuing this command will begin to suspend the currently executing Program/Erase operation.
The status register will indicate when the operation has been successfully suspended by
setting either the program-suspend SR[2] or erase-suspend SR[6] and the WSM status bit
SR[7] to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input-control pins except RP#, which will immediately shut down the WSM and the
remainder of the chip if RP# is driven to VIL. See Sections 3.2.5.1 and 3.2.6.1.
Program Suspend
Erase Suspend
B0
70
This command places the device into read-status-register mode. Reading the device will
output the contents of the status register, regardless of the address presented to the device.
The device automatically enters this mode after a Program or Erase operation has been
initiated. See Section 4.1.4, “Read Status Register” on page 20.
Read Status
Register
The WSM can set the block-lock status SR[1], VPP Status SR[3], program status SR[4], and
erase-status SR[5] bits in the status register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
Clear Status
Register
50
90
Puts the device into the read-identifier mode so that reading the device will output the
manufacturer/device codes or block-lock status. See Section 4.1.2, “Read Identifier” on
page 19.
Read
Identifier
Block Lock, Block
Unlock, Block
Lock-Down Set-
Up
Prepares the CUI for block-locking changes. If the next command is not Block Unlock, Block
Lock, or Block Lock-Down, then the CUI will set both the program and erase-status-register
bits to indicate a command-sequence error. See Section 5.0, “Security Modes” on page 27.
60
If the previous command was Lock Set-Up, the CUI will latch the address and lock the block
indicated on the address pins. (See Section 5.1)
01
2F
98
Lock-Block
Lock-Down
If the previous command was a Lock-Down Set-Up command, the CUI will latch the address
and lock-down the block indicated on the address pins. (See Section 5.1)
CFI
Query
Puts the device into the CFI-Query mode so that reading the device will output Common Flash
Interface information. See Section 4.1.3 and Appendix C, “Common Flash Interface”.
This is a two-cycle command. The first cycle prepares the CUI for a program operation to the
protection register. The second cycle latches addresses and data information and initiates the
WSM to execute the Protection Program algorithm to the protection register. The flash outputs
status-register data when CE# or OE# is toggled. A Read Array command is required after
programming to read array data. See Section 5.5.
Protection
Program
Set-Up
C0
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 8. Command Codes and Descriptions
Code
Device Mode
(HEX)
Command Description
10
00
Alt. Prog Set-Up
Operates the same as Program Set-up command. (See 0x40/Program Set-Up)
Invalid/
Reserved
Unassigned commands should not be used. Intel reserves the right to redefine these codes for
future functions.
NOTE: See Appendix A, “Write State Machine States” for mode transition information.
Table 9. Status Register Bit Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
R
0
NOTES:
SR[7] WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine Word Program
or Block Erase completion, before checking program or erase-
status bits.
SR[6] = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until
an Erase Resume command is issued.
SR[5] = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max. number
of erase pulses to the block and is still unable to verify
successful block erasure.
SR[4] = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
The VPP status bit does not provide continuous indication of
V
PP level. The WSM interrogates VPP level only after the
SR[3] = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
Program or Erase command sequences have been entered,
and informs the system if VPP has not been switched on. The
VPP is also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report accurate
feedback between VPPLK and VPP1Min.
SR[2] = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
SR[1] = BLOCK LOCK STATUS
1 = Prog/Erase attempted on a locked block; Operation
aborted.
If a Program or Erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read status
mode.
0 = No operation to locked blocks
This bit is reserved for future use and should be masked out
when polling the status register.
SR[0] = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTE: A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set.
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Intel Advanced+ Boot Block Flash Memory (C3)
5.0
Security Modes
5.1
Flexible Block Locking
The C3 device offers an instant, individual block-locking scheme that allows any block to be
locked or unlocked with no latency, enabling instant code and data protection.
This locking scheme offers two levels of protection. The first level allows software-only control of
block locking (useful for data blocks that change frequently), while the second level requires
hardware interaction before locking can be changed (useful for code blocks that change
infrequently).
The following sections will discuss the operation of the locking system. The term “state [abc]” will
be used to specify locking states; e.g., “state [001],” where a = value of WP#, b = bit D1 of the
Block Lock status register, and c = bit D0 of the Block Lock status register. Figure 5, “Block
Locking State Diagram” on page 27 displays all of the possible locking states.
Figure 5. Block Locking State Diagram
Locked-
Down4,5
Hardware
Locked5
Locked
Power-Up/Reset
[X01]
[011]
[011]
WP# Hardware Control
Software
Locked
Unlocked
Unlocked
[111]
[110]
[X00]
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)
Software Block Lock-Down (0x60/0x2F)
WP# hardware control
Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.
2. D1 indicates block Lock-down status. D1 = ‘0’, Lock-down has not been issued to
this block. D1 = ‘1’, Lock-down has been issued to this block.
3. D0 indicates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked.
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked by system software to determine difference
between Hardware Locked and Locked-Down states.
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
5.1.1
Locking Operation
The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which
will be described in the following sections. See Figure 5, “Block Locking State Diagram” on
page 27 and Figure 17, “Locking Operations Flowchart” on page 56.
The following concisely summarizes the locking functionality.
5.1.1.1
Locked State
The default state of all blocks upon power-up or reset is locked (states [001] or [101]). Locked
blocks are fully protected from alteration. Any Program or Erase operations attempted on a locked
block will return an error on bit SR[1] of the Status Register. The state of a locked block can be
changed to Unlocked or Lock Down using the appropriate software commands. An Unlocked
block can be locked by writing the Lock command sequence, 0x60 followed by 0x01.
5.1.1.2
5.1.1.3
Unlocked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks
return to the Locked state when the device is reset or powered down. The status of an unlocked
block can be changed to Locked or Locked Down using the appropriate software commands. A
Locked block can be unlocked by writing the Unlock command sequence, 0x60 followed by 0xD0.
Lock-Down State
Blocks that are Locked-Down (state [011]) are protected from Program and Erase operations (just
like Locked blocks), but their protection status cannot be changed using software commands alone.
A Locked or Unlocked block can be Locked Down by writing the Lock-Down command sequence,
0x60 followed by 0x2F. Locked-Down blocks revert to the Locked state when the device is reset or
powered down.
The Lock-Down function depends on the WP# input pin. When WP# = 0, blocks in Lock Down
[011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-Down
function is disabled ([111]) and Locked-Down blocks can be individually unlocked by software
command to the [110] state, where they can be erased and programmed. These blocks can then be
relocked [111] and unlocked [110] as required while WP# remains high. When WP# goes low,
blocks that were previously Locked Down return to the Lock-Down state [011], regardless of any
changes made while WP# was high. Device reset or power-down resets all blocks, including those
in Lock-Down, to Locked state.
5.2
Reading Block-Lock Status
The Lock status of each block can be read in read-identifier mode of the device by issuing the read-
identifier command (0x90). Subsequent reads at Block Address + 0x00002 will output the Lock
status of that block. The Lock status is represented by DQ0 and DQ1. DQ0 indicates the Block
Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also
automatically set when entering Lock Down. DQ1 indicates Lock-Down status, and is set by the
Lock-Down command. It cannot be cleared by software—only by device reset or power-down. See
Table 6, “Device Identification Codes” on page 20 for block-status information.
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Intel Advanced+ Boot Block Flash Memory (C3)
5.3
Locking Operations during Erase Suspend
Changes to block-lock status can be performed during an erase-suspend by using the standard
locking command sequences to Unlock, Lock, or Lock Down a block. This is useful in the case
when another block needs to be updated while an Erase operation is in progress.
To change block locking during an Erase operation, first issue the Erase Suspend command (0xB0),
then check the status register until it indicates that the Erase operation has been suspended. Next,
write the preferred Lock command sequence to a block and the Lock status will be changed. After
completing any preferred Lock, Read, or Program operations, resume the Erase operation with the
Erase Resume command (0xD0).
If a block is Locked or Locked Down during a Suspended Erase of the same block, the locking
status bits will be changed immediately. But when the Erase is resumed, the Erase operation will
complete.
Locking operations cannot be performed during a Program Suspend. Refer to Appendix A, “Write
State Machine States” on page 50 for detailed information on which commands are valid during
Erase Suspend.
5.4
Status Register Error Checking
Using nested-locking or program-command sequences during Erase Suspend can introduce
ambiguity into status register results.
Since locking changes are performed using a two-cycle command sequence, e.g., 0x60 followed by
0x01 to lock a block, following the Block Lock, Block Unlock, or Block Lock-Down Setup
command (0x60) with an invalid command will produce a Lock-Command error (SR[4] and SR[5]
will be set to 1) in the Status Register. If a Lock-Command error occurs during an Erase Suspend,
SR[4] and SR[5] will be set to 1 and will remain at 1 after the Erase is resumed. When Erase is
complete, any possible error during the Erase cannot be detected via the status register because of
the previous Lock-Command error.
A similar situation happens if an error occurs during a Program-Operation error nested within an
Erase Suspend.
5.5
128-Bit Protection Register
The C3 device architecture includes a 128-bit protection register than can be used to increase the
security of a system design. For example, the number contained in the protection register can be
used to “match” the flash component with other system components, such as the CPU or ASIC,
preventing device substitution. The Intel application note, AP-657 Designing with the Advanced+
Boot Block Flash Memory Architecture, contains additional application information.
The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other
segment is left blank for customer designs to program, as preferred. Once the customer segment is
programmed, it can be locked to prevent further programming.
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
5.5.1
5.5.2
Reading the Protection Register
The protection register is read in the read-identifier mode. The device is switched to this mode by
issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown
in Figure 6, “Protection Register Mapping” retrieve the specified information. To return to read-
array mode, issue the Read Array command (0xFF).
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time. First, issue the Protection Program Setup
command, 0xC0. The next write to the device will latch in address and data, and program the
specified location. The allowable addresses are shown in Table 6, “Device Identification Codes” on
page 20. See Figure 18, “Protection Register Programming Flowchart” on page 57. Attempts to
address Protection Program commands outside the defined protection register address space should
not be attempted. Attempting to program to a previously locked protection register segment will
result in a Status Register error (Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1).
5.5.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming bit 1 of the
PR-LOCK location to 0. See Figure 6, “Protection Register Mapping” on page 30. Bit 0 of this
location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set
using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these
bits have been programmed, no further changes can be made to the values stored in the protection
register. Protection Program commands to a locked section will result in a Status Register error
(Program Error bit SR[4] and Lock Error bit SR[1] will be set to 1). Protection register lockout
state is not reversible.
Figure 6. Protection Register Mapping
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Intel Factory-Programmed)
0x81
0x80
PR Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
5.6
VPP Program and Erase Voltages
The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range. For fast
production programming, 12 V programming can be used. Refer to Figure 7, “Example Power
Supply Configurations” on page 31.
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Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
5.6.1
Program Protection
In addition to the flexible block locking, the V programming voltage can be held low for absolute
PP
hardware write protection of all blocks in the flash device. When V is below or equal to V
,
PP
PPLK
any Program or Erase operation will result in an error, prompting the corresponding status-register
bit (SR[3]) to be set.
Figure 7. Example Power Supply Configurations
System Supply
System Supply
VCC
VPP
VCC
12 V Supply
VPP
Prot#
(Logic Signal)
10
≤ KΩ
12 V Fast Programming
Low-Voltage Programming
Absolute Write Protection With V
≤
VPPLK
Absolute Write Protection via Logic Signal
PP
System Supply
(Note 1)
System Supply
VCC
VCC
VPP
VPP
12 V Supply
Low Voltage and 12 V Fast Programming
Low-Voltage Programming
0645_06
NOTE:
1. A resistor can be used if the VCC supply can sink adequate current based on resistor value. See AP-657
Designing with the Advanced+ Boot Block Flash Memory Architecture for details.
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
6.0
Power Consumption
Intel Flash devices have a tiered approach to power savings that can significantly reduce overall
system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby
mode, where current consumption is even lower. If RP# is deasserted, the flash enter deep power-
down mode for ultra-low current consumption. The combination of these features can minimize
memory power consumption, and therefore, overall system power consumption.
6.1
6.2
6.3
Active Power (Program/Erase/Read)
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer
to the DC Characteristic tables for I current values. Active power is the largest contributor to
CC
overall system power consumption. Minimizing the active current could have a profound effect on
system power consumption, especially for battery-operated devices.
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the memory array and the address lines are idle, APS circuitry places the device in a mode where
typical current is comparable to I
new location is read.
. The flash stays in this static state with outputs valid until a
CCS
Standby Power
When CE# is at a logic-high level (V ), the flash memory is in standby mode, which disables
IH
much of the device’s circuitry and substantially reduces power consumption. Outputs are placed in
a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-
high level during Erase or Program operations, the device will continue to perform the operation
and consume corresponding active power until the operation is completed.
System engineers should analyze the breakdown of standby time versus active time, and quantify
the respective power consumption in each mode for their specific application. This approach will
provide a more accurate measure of application-specific power and energy requirements.
6.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = V . During read modes, RP# going low de-
IL
selects the memory and places the outputs in a high-impedance state. Recovery from deep power-
down requires a minimum time of t
operations.
for Read operations, and t
/t
for Write
PHQV
PHWL PHEL
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Intel Advanced+ Boot Block Flash Memory (C3)
During program or erase modes, RP# transitioning low will abort the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid as
the data integrity has been compromised by the abort. During deep power-down, all internal
circuits are switched to a low-power savings mode (RP# transitioning to V or turning off power
IL
to the device clears the status register).
6.5
Power and Reset Considerations
6.5.1
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is
recommended to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power-
down together.
It is also recommended to power-up VPP with or after VCC has reached VCC . Conversely, VPP
min
must powerdown with or slightly before VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCC before
min
applying VCCQ and VPP. Device inputs should not be driven before supply voltage reaches
VCC
.
min
Power supply transitions should only occur when RP# is low.
6.5.2
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RP# to the
system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V voltages are above V
. Because
CC
LKO
both WE# and CE# must be low for a command write, driving either signal to V will inhibit
IH
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to V , regardless of the state of its control inputs.
IH
By holding the device in reset during power-up/down, invalid bus conditions during power-up can
be masked, providing yet another level of memory protection.
6.5.3
VCC, VPP and RP# Transitions
The CUI latches commands as issued by system software and is not altered by V or CE#
PP
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
V
transitions above V
(Lockout voltage), is read-array mode.
CC
LKO
After any program or Block-Erase operation is complete (even after V transitions down to
PP
V
), the CUI must be reset to read-array mode via the Read Array command if access to the
PPLK
flash-memory array is desired.
Datasheet
33
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Intel Advanced+ Boot Block Flash Memory (C3)
6.6
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System
designers should consider the following three supply current issues:
• Standby current levels (I
• Read current levels (I
)
CCS
)
CCR
• Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-
line control and proper decoupling capacitor selection will suppress these transient voltage peaks.
Each flash device should have a 0.1 µF ceramic capacitor connected between each V and GND,
CC
and between its V and VSS. These high- frequency, inherently low-inductance capacitors should
PP
be placed as close as possible to the package leads.
7.0
Thermal and DC Characteristics
7.1
Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended,
and extended exposure beyond the “Operating Conditions” may affect device reliability.
.
NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have
the latest datasheet before finalizing a design.
Parameter
Extended Operating Temperature
Maximum Rating
Notes
During Read
–40 °C to +85 °C
During Block Erase and Program
Temperature under Bias
–40 °C to +85 °C
–40 °C to +85 °C
–65 °C to +125 °C
–0.5 V to +3.7 V
Storage Temperature
Voltage On Any Pin (except VCC and VPP) with Respect to GND
1
VPP Voltage (for Block Erase and Program) with Respect to GND –0.5 V to +13.5 V
1,2,3
V
CC and VCCQ Supply Voltage with Respect to GND
–0.2 V to +3.6 V
100 mA
Output Short Circuit Current
4
NOTES:
1. Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level may
undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC
+0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns.
3. VPP Program voltage is normally 1.65 V–3.6 V. Connection to a 11.4 V–12.6 V supply can be
done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter
blocks during program/erase. VPP may be connected to 12 V for a total of 80 hours maximum.
4. Output shorted for no more than one second. No more than one output shorted at a time.
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Intel Advanced+ Boot Block Flash Memory (C3)
7.2
Operating Conditions
Table 10. Temperature and Voltage Operating Conditions
Symbol
TA
Parameter
Notes
Min
Max
Units
Operating Temperature
VCC Supply Voltage
–40
2.7
+85
3.6
3.6
3.6
2.5
2.5
3.6
12.6
°C
VCC1
1, 2
1, 2
1
Volts
VCC2
3.0
VCCQ1
VCCQ2
VCCQ3
VPP1
2.7
I/O Supply Voltage
Supply Voltage
1.65
1.8
Volts
1
1, 3
3
1.65
11.4
100,000
Volts
Volts
VPP2
Cycling
Block Erase Cycling
Cycles
NOTES:
1. VCC and VCCQ must share the same supply when they are in the VCC1 range.
2. VCCMax = 3.3 V for 0.25µm 32-Mbit devices.
3. Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on
the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of
80 hours maximum.
7.3
DC Current Characteristics
Table 11. DC Current Characteristics (Sheet 1 of 3)
V
2.7 V–3.6 V 2.7 V–2.85 V
2.7 V–3.6 V 1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Test
Conditions
Sym
Parameter
V
Unit
CCQ
Note
Typ Max
Typ
Max
Typ
Max
VCC
CCMax
VCCQ
=
V
=
ILI
Input Load Current
1,2
± 1
± 1
± 1
µA
VCCQMax
V
IN = VCCQ
or GND
VCC
CCMax
VCCQ
=
V
Output Leakage
Current
=
ILO
1,2
± 10
± 10
± 10
µA
V
CCQMax
VIN = VCCQ
or GND
Datasheet
35
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 11. DC Current Characteristics (Sheet 2 of 3)
V
2.7 V–3.6 V 2.7 V–2.85 V
2.7 V–3.6 V 1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Test
Conditions
Sym
Parameter
V
Unit
CCQ
Note
Typ Max
Typ
Max
Typ
Max
VCC Standby Current
for 0.13 and 0.18
Micron Product
VCC
=
1
7
15
25
20
50
150
250
µA
VCCMax
CE# = RP#
= VCCQ
or during
Program/
Erase
ICCS
VCC Standby Current
for 0.25 Micron
Product
1
10
20
50
150
250
µA Suspend
WP# =
VCCQ or
GND
VCC Power-Down
Current for 0.13 and
0.18 Micron Product
VCC
=
1,2
1,2
7
7
9
15
25
18
7
7
8
20
25
15
7
7
9
20
25
15
µA
µA
mA
V
CCMax
VCCQ
=
V
CCQMax
ICCD
VIN = VCCQ
VCC Power-Down
or GND
RP# = GND
0.2 V
Current for 0.25
Product
VCC Read Current for
0.13 and 0.18 Micron
Product
VCC
CCMax
VCCQ
CCQMax
=
1,2,3
V
=
V
OE# = VIH
CE# =VIL
f = 5 MHz,
,
ICCR
VCC Read Current for
0.25 Micron Product
1,2,3
1
10
18
8
15
9
15
mA
µA
IOUT=0 mA
Inputs = VIL
or VIH
RP# = GND
0.2 V
VPP ≤ VCC
VPP Deep Power-
Down Current
IPPD
0.2
18
5
0.2
18
5
0.2
18
5
VPP =VPP1,
mA Program in
Progress
55
55
55
ICCW
VCC Program Current
1,4
VPP = VPP2
(12v)
Program in
Progress
8
16
8
22
45
15
10
21
16
30
45
45
10
21
16
30
45
45
mA
VPP = VPP1,
mA Erase in
Progress
ICCE
VCC Erase Current
1,4
VPP = VPP2
(12v) ,
Erase in
mA
Progress
VCC Erase Suspend
Current for 0.13 and
0.18 Micron Product
7
15
25
50
50
200
200
50
50
200
200
µA
µA
CE# = VIH,
Erase
Suspend in
Progress
ICCES
/
1,4,5
ICCWS
VCC Erase Suspend
Current for 0.25
Micron Product
10
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Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 11. DC Current Characteristics (Sheet 3 of 3)
V
2.7 V–3.6 V 2.7 V–2.85 V
2.7 V–3.6 V 1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Test
Conditions
Sym
Parameter
V
Unit
CCQ
Note
Typ Max
Typ
Max
Typ
Max
2
±15
2
±15
2
±15
µA VPP ≤ VCC
IPPR
VPP Read Current
1,4
50
200
50
200
50
200
µA VPP > VCC
VPP =VPP1,
mA Program in
Progress
0.05
8
0.1
22
0.05
8
0.1
22
0.05
8
0.1
22
IPPW
VPP Program Current
1,4
1,4
VPP = VPP2
(12v)
Program in
Progress
mA
VPP = VPP1,
mA Erase in
Progress
0.05
8
0.1
22
0.05
16
0.1
45
0.05
16
0.1
45
IPPE
VPP Erase Current
VPP = VPP2
(12v) ,
Erase in
mA
Progress
V
PP = VPP1,
Program or
µA Erase
Suspend in
Progress
0.2
50
5
0.2
50
5
0.2
50
5
IPPES
IPPWS Current
/
VCC Erase Suspend
1,4
VPP = VPP2
(12v) ,
Program or
Erase
200
200
200
µA
Suspend in
Progress
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 °C.
2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or
CCQ voltage listed at the top of each column. VCCMax = 3.3 V for 0.25µm 32-Mbit devices.
V
3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS
inputs).
4. Sampled, not 100% tested.
5. ICCES or ICCWS is specified with device de-selected. If device is read while in erase suspend, current draw
is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS
and ICCR
.
Datasheet
37
£
Intel Advanced+ Boot Block Flash Memory (C3)
7.4
DC Voltage Characteristics
Table 12. DC Voltage Characteristics
V
2.7 V–3.6 V
2.7 V–3.6 V
2.7 V–2.85 V
1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
CC
Sym
Parameter
V
Unit Test Conditions
CCQ
Note
Min
Max
Min
Max
Min
Max
Input Low
Voltage
VCC *
VIL
–0.4
2.0
–0.4
0.4
–0.4
0.4
V
V
0.22 V
Input High
Voltage
VCCQ
+0.3V
VCCQ
0.4V
–
–
VCCQ
+0.3V
VCCQ
0.4V
–
–
VCCQ
+0.3V
VIH
CC = VCCMin
Output Low
Voltage
VOL
–0.1
0.1
-0.1
0.1
-0.1
0.1
V
V
V
CC = VCCMin
Output High
Voltage
VCCQ
–0.1V
VCCQ
0.1V
VCCQ
0.1V
VOH
V
I
CCQ = VCCQMin
OH = –100 µA
VPP Lock-
Complete Write
Protection
VPPLK
VPP1
VPP2
1
1
1.0
3.6
1.0
3.6
1.0
3.6
V
V
Out Voltage
VPP during
Program /
Erase
1.65
11.4
1.65
11.4
1.65
11.4
1,2
12.6
12.6
12.6
V
Operations
VCC Prog/
Erase
Lock
VLKO
1.5
1.2
1.5
1.2
1.5
1.2
V
Voltage
VCCQ Prog/
Erase
Lock
VLKO2
V
Voltage
NOTES:
1. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2
.
2. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum.
38
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
8.0
AC Characteristics
8.1
AC Read Characteristics
Table 13. Read Operations—8 Mbit Density
Density
Product
8 Mbit
90 ns
3.0 V – 3.6 V 2.7 V – 3.6 V
110 ns
3.0 V – 3.6 V 2.7 V – 3.6 V
#
Sym
Parameter
Unit
V
CC
Note
Min
Max
Min
Max
Min
Max
Min
Max
R1
tAVAV Read Cycle Time
3,4
80
90
100
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
R2
R3
R4
R5
R6
R7
R8
R9
tAVQV Address to Output Delay
tELQV CE# to Output Delay
tGLQV OE# to Output Delay
tPHQV RP# to Output Delay
tELQX CE# to Output in Low Z
tGLQX OE# to Output in Low Z
tEHQZ CE# to Output in High Z
tGHQZ OE# to Output in High Z
Output Hold from
3,4
80
80
90
90
100
100
30
110
110
30
1,3,4
1,3,4
3,4
30
30
150
150
150
150
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
0
0
0
0
20
20
20
20
20
20
20
20
Address, CE#, or OE#
Change, Whichever
R10
tOH
2,3,4
0
0
0
0
ns
Occurs First
NOTES:
1. OE# may be delayed up to tELQV– GLQV
2. Sampled, but not 100% tested.
3. See Figure 8, “Read Operation Waveform” on page 42.
t
after the falling edge of CE# without impact on tELQV.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
Datasheet
39
£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 14. Read Operations—16 Mbit Density
Density
16 Mbit
90 ns
Product
70 ns
80 ns
110 ns
Para-
Sym mete
r
#
Unit Notes
V
2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6V 2.7 V–3.6V
Min Max Min Max Min Max Min Max Min Max Min Max
CC
R1
R2
t
Read Cycle Time
ns
ns
3,4
3,4
70
80
80
90
100
110
AVAV
t
Address to
Output Delay
AVQ
V
70
70
80
80
80
80
90
90
100
100
30
110
110
30
t
CE# to Output
Delay
ELQ
V
R3
R4
R5
R6
R7
R8
R9
ns
ns
ns
ns
ns
ns
ns
1,3,4
1,3,4
3,4
t
t
OE# to Output
Delay
GLQ
V
20
20
30
30
RP# to Output
Delay
PHQ
V
150
150
150
150
150
150
t
CE# to Output in
Low Z
ELQ
X
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
0
0
0
0
0
0
0
0
t
t
OE# to Output in
Low Z
GLQ
X
CE# to Output in
High Z
EHQ
Z
20
20
20
20
20
20
20
20
20
20
20
20
t
OE# to Output in
High Z
GHQ
Z
Output Hold from
Address, CE#, or
OE# Change,
Whichever
R10
t
ns
2,3,4
0
0
0
0
0
0
OH
Occurs First
NOTES:
1. OE# may be delayed up to tELQV– GLQV
2. Sampled, but not 100% tested.
3. See Figure 8, “Read Operation Waveform” on page 42.
t
after the falling edge of CE# without impact on tELQV.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
40
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 15. Read Operations—32 Mbit Density
Density
32 Mbit
Product
70 ns
90 ns
100 ns
110 ns
Para-
meter
#
Sym
Unit Notes
V
2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V 3.0 V–3.3 V 2.7 V–3.3 V
Min Max Min Max Min Max Min Max Min Max Min Max
CC
R1
R2
t
Read Cycle Time
ns
ns
3,4
3,4
70
90
90
100
100
110
AVAV
t
Address to Output
Delay
AVQ
V
70
70
90
90
90
90
100
100
30
100
100
30
110
110
30
t
CE# to Output
Delay
ELQ
V
R3
R4
R5
R6
R7
R8
R9
ns
ns
ns
ns
ns
ns
ns
1,3,4
1,3,4
3,4
t
t
OE# to Output
Delay
GLQ
V
20
20
30
RP# to Output
Delay
PHQ
V
150
150
150
150
150
150
t
CE# to Output in
Low Z
ELQ
X
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
0
0
0
0
0
0
0
0
t
t
OE# to Output in
Low Z
GLQ
X
CE# to Output in
High Z
EHQ
Z
20
20
20
20
20
20
20
20
20
20
20
20
t
OE# to Output in
High Z
GHQ
Z
Output Hold from
Address, CE#, or
OE# Change,
Whichever
R10
t
ns
2,3,4
0
0
0
0
0
0
OH
Occurs First
NOTES:
1. OE# may be delayed up to tELQV– GLQV
2. Sampled, but not 100% tested.
3. See Figure 8, “Read Operation Waveform” on page 42.
t
after the falling edge of CE# without impact on tELQV.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable
input slew rate.
Datasheet
41
£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 16. Read Operations — 64 Mbit Density
Density
Product
64 Mbit
70 ns
2.7 V–3.6 V
80 ns
#
Sym
Parameter
Unit
V
2.7 V–3.6 V
CC
Note
Min
Max
Min
Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
tAVAV Read Cycle Time
3,4
3,4
70
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV Address to Output Delay
tELQV CE# to Output Delay
tGLQV OE# to Output Delay
tPHQV RP# to Output Delay
tELQX CE# to Output in Low Z
tGLQX OE# to Output in Low Z
tEHQZ CE# to Output in High Z
tGHQZ OE# to Output in High Z
70
70
80
80
1,3,4
1,3,4
3,4
20
20
150
150
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
20
20
20
20
Output Hold from Address, CE#, or OE#
Change, Whichever Occurs First
R10
tOH
2,3,4
0
0
ns
NOTES:
1. OE# may be delayed up to tELQV– GLQV
2. Sampled, but not 100% tested.
3. See Figure 8, “Read Operation Waveform” on page 42.
t
after the falling edge of CE# without impact on tELQV.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and
maximum allowable input slew rate.
Figure 8. Read Operation Waveform
R1
R2
R3
Address [A]
CE# [E]
R8
R4
R9
OE# [G]
WE# [W]
R7
R6
R10
Data [D/Q]
RST# [P]
R5
42
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
8.2
AC Write Characteristics
Table 17. Write Operations—8 Mbit Density
Density
Product
3.0 V – 3.6 V
2.7 V – 3.6 V
Note
4,5
8 Mbit
90 ns
110 ns
100
#
Sym
Parameter
80
Unit
V
CC
90
110
Min
Min
Min
Min
tPHWL
/
W1
W2
W3
W4
W5
W6
W7
W8
W9
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
150
150
0
150
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHEL
tELWL
tWLEL
/
4,5
4,5
0
50
50
50
0
0
70
60
70
0
tWLWH
tELEH
/
60
50
60
0
70
60
70
0
tDVWH
tDVEH
/
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
2,4,5
2,4,5
4,5
tAVWH
tAVEH
/
tWHEH
tEHWH
/
/
/
tWHDX
tEHDX
2,4,5
2,4,5
2,4,5
0
0
0
0
tWHAX
tEHAX
0
0
0
0
tWHWL /
tEHEL
30
30
30
30
tVPWH
tVPEH
/
W10
W11
W12
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200
0
200
0
ns
ns
ns
tQVVL
tBHWH
tBHEH
/
WP# Setup to WE# (CE#) Going High
3,4
0
0
0
0
W13
W14
tQVBL
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
ns
ns
tWHGL
WE# High to OE# Going Low
30
30
30
30
NOTES:
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever
goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or
WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
t
WPH = tWHWL = tEHEL = tWHEL = tEHWL.
2. Refer to Table 7, “Command Bus Operations” on page 24 for valid AIN or DIN
3. Sampled, but not 100% tested.
.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
5. See Figure 9, “Write Operations Waveform” on page 47.
Datasheet
43
£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 18. Write Operations—16 Mbit Density
Density
Product
16 Mbit
90 ns
80
70 ns
80 ns
110 ns
100
#
Sym
Parameter
3.0 V – 3.6 V
2.7 V – 3.6 V
Unit
V
CC
70
80
90
110
Min
Note
Min
Min
Min Min
Min
tPHWL
tPHEL
/
RP# High Recovery to WE# (CE#) Going
Low
W1
4,5
150
0
150
0
150 150
150
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tELWL
tWLEL
/
W2
W3
W4
W5
W6
W7
W8
W9
CE# (WE#) Setup to WE# (CE#) Going Low 4,5
0
50
50
50
0
0
60
50
60
0
0
70
60
70
0
tWLWH
tELEH
/
WE# (CE#) Pulse Width
1,4,5
2,4,5
2,4,5
4,5
45
40
50
0
50
40
50
0
70
60
70
0
tDVWH
tDVEH
/
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
tAVWH
tAVEH
/
tWHEH
tEHWH
/
/
/
CE# (WE#) Hold Time from WE# (CE#)
High
tWHDX
tEHDX
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
2,4,5
2,4,5
1,4,5
0
0
0
0
0
0
tWHAX
tEHAX
0
0
0
0
0
0
tWHWL /
tEHEL
25
30
30
30
30
30
tVPWH
tVPEH
/
W10
W11
W12
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200 200
200
0
200
0
ns
ns
ns
tQVVL
0
0
0
0
tBHWH
tBHEH
/
WP# Setup to WE# (CE#) Going High
3,4
0
0
0
0
W13
tQVBL
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
0
0
ns
ns
W14
tWHGL
WE# High to OE# Going Low
30
30
30
30
30
30
NOTES:
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined
from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
t
WPH = tWHWL = tEHEL = tWHEL = tEHWL.
2. Refer to Table 7, “Command Bus Operations” on page 24 for valid AIN or DIN
3. Sampled, but not 100% tested.
.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
5. See Figure 9, “Write Operations Waveform” on page 47.
44
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 19. Write Operations—32 Mbit Density
Density
Product
32 Mbit
70 ns
90 ns
100 ns
110 ns
100
#
Sym
Parameter
3.0 V – 3.6 V6
2.7 V – 3.6 V
Note
90
Unit
V
CC
70
90
100
Min
110
Min
Min
Min
Min
Min
tPHWL
tPHEL
/
RP# High Recovery to WE# (CE#)
Going Low
W1
W2
4,5
4,5
150
0
150
0
150
150
0
150
150
0
ns
ns
tELWL
tWLEL
/
CE# (WE#) Setup to WE# (CE#)
Going Low
0
0
tWLWH
/
W3
WE# (CE#) Pulse Width
1,4,5
45
60
60
70
70
70
ns
tELEH
tDVWH
tDVEH
/
/
/
/
/
W4
W5
W6
W7
W8
W9
W10
Data Setup to WE# (CE#) Going High
2,4,5
2,4,5
4,5
40
50
0
40
60
0
50
60
0
60
70
0
60
70
0
60
70
0
ns
ns
ns
ns
ns
ns
tAVWH
tAVEH
Address Setup to WE# (CE#) Going
High
tWHEH
tEHWH
CE# (WE#) Hold Time from WE#
(CE#) High
tWHDX
tEHDX
Data Hold Time from WE# (CE#)
High
2,4,5
2,4,5
1,4,5
0
0
0
0
0
0
tWHAX
tEHAX
Address Hold Time from WE# (CE#)
High
0
0
0
0
0
0
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
25
30
30
30
30
30
tVPWH
tVPEH
/
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200
0
200
0
200
0
200
0
ns
ns
ns
W11 tQVVL
tBHWH
W12
/
WP# Setup to WE# (CE#) Going
High
3,4
0
0
0
0
0
0
tBHEH
W13 tQVBL
W14 tWHGL
NOTES:
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
0
0
ns
ns
WE# High to OE# Going Low
30
30
30
30
30
30
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever
goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or
WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
t
WPH = tWHWL = tEHEL = tWHEL = tEHWL.
2. Refer to Table 7, “Command Bus Operations” on page 24 for valid AIN or DIN
3. Sampled, but not 100% tested.
.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
5. See Figure 9, “Write Operations Waveform” on page 47.
6. VCCMax = 3.3 V for 32-Mbit 0.25 Micron product.
Datasheet
45
£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 20. Write Operations—64Mbit Density
Density
64 Mbit
80 ns
Min
#
Sym
Parameter
Product
Unit
V
2.7 V – 3.6 V Note
CC
tPHWL
tPHEL
/
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
4,5
4,5
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tELWL
tWLEL
/
tWLWH
tELEH
/
1,4,5
2,4,5
2,4,5
4,5
60
40
60
0
tDVWH
tDVEH
/
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
tAVWH
tAVEH
/
tWHEH
tEHWH
/
/
/
tWHDX
tEHDX
2,4,5
2,4,5
1,4,5
0
tWHAX
tEHAX
0
tWHWL /
tEHEL
30
tVPWH
tVPEH
/
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
ns
ns
ns
W11 tQVVL
tBHWH
W12
/
WP# Setup to WE# (CE#) Going High
3,4
0
tBHEH
W13 tQVBL
W14 tWHGL
NOTES:
WP# Hold from Valid SRD
3,4
3,4
0
ns
ns
WE# High to OE# Going Low
30
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or
WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH
.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes
high first) to CE# or WE# going low (whichever goes low last). Hence,
t
WPH = tWHWL = tEHEL = tWHEL = tEHWL.
2. Refer to Table 7, “Command Bus Operations” on page 24 for valid AIN or DIN
3. Sampled, but not 100% tested.
.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and
maximum allowable input slew rate.
5. See Figure 9, “Write Operations Waveform” on page 47.
46
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 9. Write Operations Waveform
W5
W8
W6
Address [A]
CE# [E]
W3
W2
W9
WE# [W]
OE# [G]
W4
W7
Data [D/Q]
W1
RP# [P]
W10
Vpp [V]
8.3
Erase and Program Timings
Table 21. Erase and Program Timings
V
1.65 V–3.6 V
11.4 V–12.6 V
PP
Symbol
Parameter
Unit
Note
Typ
Max
Typ
Max
4-KW Parameter Block
Word Program Time
tBWPB
tBWMB
1, 2, 3
0.10
0.30
0.03
0.12
s
s
32-KW Main Block
Word Program Time
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0.8
12
22
0.5
1
2.4
200
200
4
0.24
8
1
185
185
4
Word Program Time for 0.13
and 0.18 Micron Product
µs
µs
s
t
t
WHQV1 / tEHQV1
Word Program Time for 0.25
Micron Product
8
4-KW Parameter Block
Erase Time
WHQV2 / tEHQV2
WHQV3 / tEHQV3
WHRH1 / tEHRH1
0.4
0.6
32-KW Main Block
Erase Time
t
t
5
5
s
Program Suspend Latency
Erase Suspend Latency
1,3
1,3
5
5
10
20
5
5
10
20
µs
µs
tWHRH2 / tEHRH2
NOTES:
1. Typical values measured at TA= +25 °C and nominal voltages.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
Datasheet
47
£
Intel Advanced+ Boot Block Flash Memory (C3)
8.4
Reset Specifications
Table 22. Reset Specifications
V
2.7 V – 3.6 V
Max
CC
Symbol
Parameter
Notes
Unit
Min
RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not
applicable)
tPLPH
1, 2
100
ns
tPLRH1
RP# Low to Reset during Block Erase
RP# Low to Reset during Program
3
3
22
12
µs
µs
tPLRH2
NOTES:
1. If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
2. If RP# is asserted while a Block Erase or Word Program operation is not executing, the reset will complete
within 100 ns.
3. Sampled, but not 100% tested.
Figure 10. Reset Operations Waveforms
V
IH
RP# (P)
tPHQV
tPHWL
tPHEL
VIL
t PLPH
(A) Reset during Read Mode
Abort
Complete
t PLRH
tPHQV
tPHWL
tPHEL
VIH
VIL
RP# (P)
t PLPH
t PLPH
t PLRH
<
(B) Reset during Program or Block Erase,
Abort Deep
Complete Power-
tPHQV
tPHWL
tPHEL
Down
t PLRH
VIH
VIL
RP# (P)
t PLPH
(C) Reset Program or Block Erase,
>
t PLPH t PLRH
48
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
8.5
AC I/O Test Conditions
Figure 11. AC Input/Output Reference Waveform
VCCQ
Test Points
Input
V
CCQ/2
VCCQ/2
Output
0V
NOTE: Input timing begins, and output timing ends, at V
/2. Input rise and fall times (10% to 90%) < 5 ns.
CCQ
Worst case speed conditions are when V = V Min.
CC
CC
Figure 12. Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
NOTE: See Table 17 for component values.
Table 23. Test Configuration Component Values for Worst Case Speed Conditions
Test Configuration
Min Standard Test
C
(pF)
R
(kΩ)
R (kΩ)
2
L
1
V
50
25
25
CCQ
NOTE: C includes jig capacitance.
L
8.6
Device Capacitance
T = 25 °C, f = 1 MHz
A
Symbol
Parameter§
Typ
Max
Unit
Condition
V = 0.0 V
IN
C
C
Input Capacitance
Output Capacitance
6
8
8
pF
pF
IN
12
V
= 0.0 V
OUT
OUT
§Sampled, not 100% tested.
Datasheet
49
£
Intel Advanced+ Boot Block Flash Memory (C3)
Appendix A Write State Machine States
This table shows the command state transitions based on incoming commands.
Command Input (and Next State)
Data
When
Read
Program
Setup (10/
40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0)
Clear
Status
(50H)
Read Array
(FFH)
Read Status
(70H)
Current State
SR.7
Read Array
Read Status
Read Config.
Read Query
“1”
“1”
“1”
“1”
Array
Status
Config
CFI
Read Array
Read Array
Read Array
Read Array
Prog. Setup
Prog. Setup
Prog. Setup
Prog. Setup
Ers. Setup
Ers. Setup
Ers. Setup
Ers. Setup
Read Array
Read Array
Read Array
Read Array
Read Sts.
Read Sts.
Read Sts.
Read Sts.
Read Array
Read Array
Read Array
Read Array
Lock
Cmd. Error
Lock
(Done)
Lock Setup
“1”
Status
Lock Command Error
Lock (Done)
Lock Cmd. Error
Lock Cmd. Error
Lock Oper. (Done)
Prot. Prog. Setup
“1”
“1”
“1”
Status
Status
Status
Read Array
Read Array
Prog. Setup
Prog. Setup
Ers. Setup
Ers. Setup
Read Array
Read Array
Read Sts.
Read Sts.
Read Array
Read Array
Protection Register Program
Protection Register Program (Not Done)
Ers. Setup Read Array
Program
Prot. Prog.
(Not Done)
“0”
Status
Prot. Prog. (Done)
Prog. Setup
“1”
“1”
Status
Status
Read Array
Prog. Setup
Read Sts.
Read Array
Prog. Sus.
Status
Program (Not Done)
Prog. Susp. Status
“0”
“1”
“1”
“1”
Status
Status
Array
Program (Not Done)
Program (Not Done)
Prog. Sus.
Read Array
Program Suspend
Read Array
Prog. (Not
Done)
Prog. Sus. Rd.
Array
Program
Prog. Sus.
Status
Prog. Sus.
Rd. Array
(Not Done)
Prog. Susp. Read
Array
Prog. Sus.
Read Array
Program Suspend
Read Array
Prog. (Not
Done)
Prog. Sus. Rd.
Array
Program
(Not Done)
Prog. Sus.
Status
Prog. Sus.
Rd. Array
Prog. Susp. Read
Config
Prog. Sus.
Read Array
Program Suspend
Read Array
Prog. (Not
Done)
Prog. Sus. Rd.
Array
Program
(Not Done)
Prog. Sus.
Status
Prog. Sus.
Rd. Array
Config
Prog. Susp. Read
Query
Prog. Sus.
Read Array
Program Suspend
Read Array
Prog. (Not
Done)
Prog. Sus. Rd.
Array
Program
Prog. Sus.
Status
Prog. Sus.
Rd. Array
“1”
“1”
“1”
“1”
“0”
CFI
(Not Done)
Program (Done)
Erase Setup
Status
Status
Status
Status
Read Array
Prog. Setup
Ers. Setup
Read Array
Read Status
Read Array
Erase
(Not Done)
Erase Cmd.
Error
Erase
(Not Done)
Erase Command Error
Erase Command Error
Erase Cmd. Error
Erase (Not Done)
Read Array
Prog. Setup
Ers. Setup
Read Array
Read Status
Read Array
Erase Sus.
Status
Erase (Not Done)
Erase (Not Done)
Erase Sus.
Read Array
Ers. Sus.
Rd. Array
Ers. Sus. Rd.
Array
Erase Sus.
Status
Ers. Sus.
Rd. Array
Ers. Susp. Status
Erase Susp. Array
“1”
“1”
“1”
Status
Array
Prog. Setup
Prog. Setup
Prog. Setup
Erase
Erase
Erase
Erase
Erase
Erase
Erase
Erase
Erase Sus.
Read Array
Ers. Sus.
Rd. Array
Ers. Sus. Rd.
Array
Erase Sus.
Status
Ers. Sus.
Rd. Array
Ers. Susp. Read
Config
Erase Sus.
Read Array
Ers. Sus.
Rd. Array
Ers. Sus. Rd.
Array
Erase Sus.
Status
Ers. Sus.
Rd. Array
Config
Ers. Susp. Read
Query
Erase Sus.
Read Array
Ers. Sus.
Rd. Array
Ers. Sus. Rd.
Array
Erase Sus.
Status
Ers. Sus.
Rd. Array
“1”
“1”
CFI
Prog. Setup
Prog. Setup
Erase (Done)
Status
Read Array
Ers. Setup
Read Array
Read Sts.
Read Array
50
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Command Input (and Next State)
Lock Setup
(60H)
Lock Down
Confirm
(2FH)
Read Config
(90H)
Read Query
(98H)
Prot. Prog.
Setup (C0H)
Lock Confirm
(01H)
Unlock Confirm
(D0H)
Current State
Read Array
Read Status
Read Config.
Read Query
Lock Setup
Read Config.
Read Config.
Read Config.
Read Config.
Read Query
Read Query
Read Query
Read Query
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Prot. Prog. Setup
Prot. Prog. Setup
Prot. Prog. Setup
Prot. Prog. Setup
Read Array
Read Array
Read Array
Read Array
Locking Command Error
Lock Operation (Done)
Read Array
Lock Cmd. Error
Read Config.
Read Config.
Read Query
Read Query
Lock Setup
Lock Setup
Prot. Prog. Setup
Prot. Prog. Setup
Lock Oper.
(Done)
Read Array
Prot. Prog. Setup
Protection Register Program
Prot. Prog.
(Not Done)
Protection Register Program (Not Done)
Prot. Prog.
(Done)
Read Config.
Read Query
Lock Setup
Prot. Prog. Setup
Program
Read Array
Prog. Setup
Program
(Not Done)
Program (Not Done)
Prog. Susp.
Status
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Program Suspend Read Array
Prog. Susp.
Read Array
Prog. Susp.
Prog. Susp.
Read Query
Program
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Read Config.
(Not Done)
Prog. Susp.
Read Config.
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Prog. Susp.
Read Query.
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Program
(Done)
Read Config.
Read Config.
Read Query
Read Query
Lock Setup
Prot. Prog. Setup
Read Array
Read Array
Erase
Setup
Erase
(Not Done)
Erase Command Error
Erase Cmd.
Error
Lock Setup
Prot. Prog. Setup
Erase (Not Done)
Erase
(Not Done)
Erase Susp.
Status
Ers. Susp. Read
Config.
Erase Suspend
Read Query
Erase
Lock Setup
Lock Setup
Lock Setup
Erase Suspend Read Array
(Not Done)
Erase Suspend
Array
Ers. Susp. Read
Config.
Erase Suspend
Read Query
Erase
(Not Done)
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Array
Eras Sus. Read
Config
Erase Suspend
Read Config.
Erase Suspend
Read Query
Erase
(Not Done)
Eras Sus. Read
Query
Erase Suspend
Read Config.
Erase Suspend
Read Query
Erase
(Not Done)
Lock Setup
Lock Setup
Ers.(Done)
Read Config.
Read Query
Prot. Prog. Setup
Read Array
Datasheet
51
£
Intel Advanced+ Boot Block Flash Memory (C3)
Appendix B Flow Charts
Figure 13. Word Program Flowchart
WORD PROGRAM PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0x40
Write
Write
Read
Write 0x40,
Word Address
Setup
Addr = Location to program
(Setup)
Data = Data to program
Addr = Location to program
Data
Write Data,
Word Address
(Confirm)
Status register data: Toggle CE# or
OE# to update Status Register
None
None
Program
Suspend
Loop
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Idle
No
Suspend?
Yes
0
SR[7] =
Repeat for subsequent Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
1
Full Status
Check
(if desired)
Write 0xFF after the last operation to set to the Read Array
state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = PP Error
Idle
Idle
None
V
1
1
1
VPP Range
Error
SR[3] =
0
Check SR[4]:
1 = Data Program Error
None
Program
Error
Check SR[1]:
1 = Block locked; operation aborted
SR[4] =
0
Idle
None
SR[3] MUST be cleared before the Write State Machine will
allow further program attempts.
Device
SR[1] =
0
Protect Error
If an error is detected, clear the Status Register before
continuing operations - only the Clear Staus Register
command clears the Status Register error bits.
Program
Successful
52
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 14. Program Suspend / Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read
Status
Data = 0x70
Addr = Any address
Write
Write
Write 0xB0
Any Address
(Program Suspend)
(Read Status)
Program Data = 0xB0
Suspend Addr = Any address
Write 0x70
Any Address
Status register data
Toggle CE# or OE# to update Status
register
Read
None
Read Status
Register
Addr = Any address
Check SR[7]:
Idle
Idle
None
None
1 = WSM ready
0 = WSM busy
0
SR[7] =
1
Check SR[2]:
1 = Program suspended
0 = Program completed
0
Program
Completed
SR[2] =
1
Read
Array
Data = 0xFF
Addr = Any address
Write
Read
Write
Write 0xFF
(Read Array)
Read array data from block other than
the one being programmed
None
Read Array
Data
(Read
Array)
Write 0xFF
Program Data = 0xD0
Resume Addr = Any address
Read Array
Data
Done
Reading
No
Yes
Write 0xD0
Any Address
(Program Resume)
Program
Resumed
Datasheet
53
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 15. Erase Suspend / Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Read
Status
Data = 0x70
Addr = Any address
Write
Write
Write 0xB0,
Any Address
(Erase Suspend)
(Read Status)
Erase
Data = 0xB0
Suspend Addr = Any address
Write 0x70,
Any Address
Status Register data. Toggle CE# or
OE# to update Status register;
Addr = Any Address
Read
Idle
None
None
None
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
0
SR[7] =
1
Check SR[6]:
1 = Erase suspended
0 = Erase completed
Idle
0
Erase
Completed
SR[6] =
1
Read Array Data = 0xFF or 0x40
or Program Addr = Any address
Write
Write 0xFF
Read or
Write
Read array or program data from/to
block other than the one being erased
None
Read Array
Data
Program Data = 0xD0
Resume Addr = Any address
Write
(Read Array)
Done
0
Reading
1
Write 0xD0,
Any Address
(Erase Resume)
(Read Array)
Write 0xFF
Erase
Resumed
Read Array
Data
54
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 16. Block Erase Flowchart
BLOCK ERASE PROCEDURE
Bus
Operation
Start
Command
Comments
Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write
Write 0x20,
(Block Erase)
Block Address
Erase Data = 0xD0
Confirm Addr = Block to be erased (BA)
Write
Read
Write 0xD0,
(Erase Confirm)
Block Address
Status Register data. Toggle CE# or
None
OE# to update Status register data
Suspend
Erase
Loop
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
None
No
Suspend
Erase
0
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Write 0xFF after the last operation to enter read array mode.
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = PP Range Error
Idle
Idle
Idle
None
None
None
V
1
VP P Range
Error
SR[3] =
0
Check SR[4,5]:
Both 1 = Command Sequence Error
1,1
1
Command
Sequence Error
Check SR[5]:
1 = Block Erase Error
SR[4,5] =
0
Check SR[1]:
1 = Attempted erase of locked block;
erase aborted.
Block Erase
Error
Idle
None
SR[5] =
0
SR[1,3] must be cleared before the Write State Machine will
allow further erase attempts.
1
Block Locked
Error
SR[1] =
0
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
Block Erase
Successful
Datasheet
55
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 17. Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Bus
Command
Comments
Operation
Write 0x60,
Block Address
Lock
Setup
Data = 0x60
Addr = Any Address
(Lock Setup)
Write
Lock,
Unlock, or
Lock-Down
Data = 0x01 (Block Lock)
0xD0 (Block Unlock)
Write either
0x01/0xD0/0x2F,
Block Address
(Lock Confirm)
Write
Write
0x2F (Lock-Down Block)
Confirm Addr = Block to lock/unlock/lock-down
Read Data = 0x90
(Optional) Device ID Addr = Any Address
Write 0x90
(Read Device ID)
Read
(Optional)
Block Lock Block Lock status data
Read Block
Lock Status
Status
Addr = Block address + offset 2
Idle
(Optional)
None
Confirm locking change on D[1,0] .
Locking
No
Change?
Yes
Read
Array
Data = 0xFF
Addr = Any address
Write
Write 0xFF
Any Address
(Read Array)
Lock Change
Complete
56
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 18. Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 0xC0
PR Setup Addr = First Location to Program
Write
Write
Read
Write 0xC0,
PR Address
(Program Setup)
(Confirm Data)
Protection Data = Data to Program
Program Addr = Location to Program
Write PR
Address & Data
Status Register Data. Toggle CE# or
None
OE# to Update Status Register Data
Read Status
Register
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Idle
None
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
0
SR[7] =
1
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
Bus
Operation
Command
Comments
Check SR[1], SR[3], SR[4]:
0,1,1 = VPP Range Error
Idle
Idle
Idle
None
1
SR[3], SR[4] =
0
VPP Range Error
Program Error
Check SR[1], SR[3], SR[4]:
0,0,1 = Programming Error
None
None
Check SR[1], SR[3], SR[4]:
1,0,1 = Block locked; operation aborted
1
1
SR[3], SR[4] =
SR[3] must be cleared before the Write State Machine will
allow further program attempts.
0
Only the Clear Staus Register command clears SR[1, 3, 4].
Register Locked;
Program Aborted
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
SR[3], SR[4] =
0
Program
Successful
Datasheet
57
£
Intel Advanced+ Boot Block Flash Memory (C3)
Appendix C Common Flash Interface
This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,
and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.
C.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query data are presented on the lowest-order data outputs (DQ0-DQ7) only. The numerical offset
value is the address relative to the maximum bus width supported by the device. On this family of
devices, the Query table device starting address is a 0x10, which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on
the low byte at word addresses 0x10 and 0x11. This CFI-compliant device outputs 0x00 data on
upper bytes. The device outputs ASCII “Q” in the low byte (DQ0-DQ7) and 0x00 in the high byte
(DQ8-DQ15).
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“0x00,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 0x00 on the upper byte in this mode.
Table 24. Summary of Query Structure Output as a Function of Device and Mode
Device
Hex Offset
Hex Code
ASCII Value
00010:
00011:
00012:
51
52
59
"Q"
"R"
"Y"
Device Addresses
Table 25. Example of Query Structure Output of x16 Devices (Sheet 1 of 2)
Word Addressing:
Offset
A[X-0]
Hex Code
Value
DQ[16:0]
0x00010
0x00011
0x00012
0x00013
0051
0052
"Q"
"R"
0059
"Y"
P_IDLO
PrVendor
58
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 25. Example of Query Structure Output of x16 Devices (Sheet 2 of 2)
0x00014
0x00015
0x00016
0x00017
0x00018
...
P_IDHI
PLO
ID #
PrVendor
TblAdr
AltVendor
ID #
PHI
A_IDLO
A_IDHI
...
...
C.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are summarized
below.
Table 26. Query Structure
Description1
Offset
Sub-Section Name
0x00000
Manufacturer Code
Device Code
0x00001
0x(BA+2)2
Block Status register
Reserved
Block-specific information
0x00004-0xF
Reserved for vendor-specific information
CFI query identification
string
0x00010
Command set ID and vendor data offset
System interface
information
0x0001B
0x00027
P3
Device timing & voltage information
Flash device layout
Device geometry definition
Primary Intel-specific
Extended Query Table
Vendor-defined additional information specific to the Primary
Vendor Algorithm
NOTES:
1. Refer to the Query Structure Output section and offset 0x28 for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is
32K-word).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
C.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations.
Block Erase Status (BSR[1]) allows system software to determine the success of the last block
erase operation. BSR[1] can be used just after power-up to verify that the VCC supply was not
accidentally removed during an erase operation.
Datasheet
59
£
Intel Advanced+ Boot Block Flash Memory (C3)
Table 27. Block Status Register
Offset
Length
Description
Block Lock Status Register
Add.
Value
BA+2 --00 or --01
BSR[0] Block lock status
0 = Unlocked
BA+2 (bit 0): 0 or 1
1 = Locked
0x(BA+2)1
1
BSR[1] Block lock-down status
0 = Not locked down
BA+2 (bit 1): 0 or 1
BA+2 (bit 2-7): 0
1 = Locked down
BSR[7:2]: Reserved for future use
NOTES:
1. BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is
32K-word).
C.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s).
Table 28. CFI Identification
Offset
Length
Description
Add.
Hex Code
Value
10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
0x10
3
Query-unique ASCII string “QRY“
Primary vendor command set and control interface ID code
16-bit ID code for vendor-specified algorithms
13:
14:
--03
--00
0x13
0x15
0x17
0x19
2
2
2
2
15:
16:
--35
--00
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code
0x0000 means no second vendor-specified algorithm exists
17:
18:
--00
--00
Secondary algorithm Extended Query Table address
0x0000 means none exists
19:
1A:
--00
--00
Table 29. System Interface Information
Offset
Length
Description
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
Add.
Hex Code
Value
V
V
V
CC
0x1B
0x1C
0x1D
1
1B:
--27
2.7 V
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1
1
1C:
1D:
--36
--B4
3.6 V
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
11.4 V
60
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
Offset
Length
Description
Add.
Hex Code
Value
V
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
0x1E
1
1E:
--C6
12.6 V
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
1
1
1
1
1
1
1
1
“n” such that typical single word program time-out =2n µs
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
1F:
20:
21:
22:
23:
24:
25:
26:
--05
--00
--0A
--00
--04
--00
--03
--00
32 µs
NA
1 s
“n” such that typical full chip erase time-out = 2n ms
NA
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
512µs
NA
8s
NA
C.5
Device Geometry Definition
Table 30. Device Geometry Definition
Hex
Code
Offset
0x27
Length
Description
Add.
Value
1
2
“n” such that device size = 2n in number of bytes
27
See Table 31
x8 async
x16 async
x8/x16 async
28:
29:
--01
--00
0x28
Flash device interface:
x16
0
28:00,29:00 28:01,29:00 28:02,29:00
2A:
2B:
--00
--00
0x2A
0x2C
2
“n” such that maximum number of bytes in write buffer = 2n
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions
with one or more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
1
2C:
--02
2
Erase Block Region 1 Information
2D:
2E:
2F:
30:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
0x2D
0x2D
4
See Table 31
See Table 31
Erase Block Region 2 Information
31:
32:
33:
34:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
14
Datasheet
61
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 31. Device Geometry Details
16 Mbit
32 Mbit
64 Mbit
Address
-B
-T
-B
-T
-B
-T
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
--15
--01
--00
--00
--00
--02
--07
--00
--20
--00
--1E
--00
--00
--01
-15
--01
--00
--00
--00
--02
--1E
--00
--00
--01
--07
--00
--20
--00
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
-16
--01
-00
--17
--01
-00
--17
--01
-00
-00
-00
-00
-00
-00
-00
--02
--3E
-00
--02
--07
-00
--02
--7E
-00
-00
--20
--00
--7E
-00
--00
--01
--07
-00
--01
--07
-00
--20
--00
--00
--01
--20
--00
C.6
Intel-Specific Extended Query Table
Certain flash features and commands are optional. The Intel-Specific Extended Query table
specifies this and other similar types of information.
Table 32. Primary-Vendor Specific Extended Query (Sheet 1 of 2)
Offset1
P = 0x15
Description
(Optional Flash Features and Commands)
Length
Address
Hex Code
Value
0x(P+0)
0x(P+1)
0x(P+2)
35:
36:
37:
--50
--52
--49
“P”
“R”
“I”
Primary extended query table
Unique ASCII string “PRI”
3
0x(P+3)
0x(P+4)
1
1
Major version number, ASCII
Minor version number, ASCII
38:
39:
--31
--30
“1”
“0”
Optional feature and command support (1=yes,
0=no)
bits 9–31 are reserved; undefined bits are “0.” If bit
31 is “1” then another 31 bit field of optional
features follows at the end of the bit-30 field.
3A:
3B:
3C:
3D:
--66
--00
--00
--00
0x(P+5)
0x(P+6)
0x(P+7)
0x(P+8)
bit 0 Chip erase supported
bit 0 = 0
No
Yes
Yes
No
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
4
No
Yes
Yes
No
bit 7 Page mode read supported
bit 8 Synchronous read supported
No
62
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
Table 32. Primary-Vendor Specific Extended Query (Sheet 2 of 2)
Offset1
P = 0x15
Description
(Optional Flash Features and Commands)
Length
Address
Hex Code
Value
Supported functions after suspend: Read Array,
Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
3E:
--01
0x(P+9)
1
bit 0 Program supported after erase suspend
bit 0 = 1
Yes
3F:
40:
--03
--00
Block status register mask
0x(P+A)
0x(P+B)
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status Register active
bit 1 Block Lock-Down Bit Status active
2
bit 0 = 1
Yes
Yes
bit 1 = 1
V
logic supply highest performance program/
CC
erase voltage
0x(P+C)
1
1
41:
42:
--33
--C0
3.3 V
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
V
optimum program/erase supply voltage
PP
0x(P+D)
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
12.0 V
NOTES:
1. The variable P is a pointer which is defined at CFI offset 0x15.
Table 33. Protection Register Information
Offset1
P = 0x35
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Address
Value
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
0x(P+E)
1
43:
--01
01
0x(P+F)
0x(P+10)
(0xP+11)
44:
45:
46:
--80
--00
--03
80h
00h
8 byte
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device-
unique serial numbers. Others are user programmable. Bits 0–15
point to the Protection register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-
programmable.
4
0x(P+12)
47:
48:
--03
8 byte
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JEDEC -plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
0x(P+13)
Reserved for future use
NOTES:
1. The variable P is a pointer which is defined at CFI offset 0x15.
Datasheet
63
£
Intel Advanced+ Boot Block Flash Memory (C3)
Appendix D Mechanical Specifications
Figure 19. µBGA* and VF BGA Package Drawing & Dimensions
R0
Ball A1
Corner
Ball A1
Corner
D
S1
S2
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2 1
A
B
C
D
A
B
C
E
D
E
F
e
E
F
b
Top View - Bump Side down
Bottom View -Bump side up
A
1
A2
A
Seating
Plan
Y
Side View
Note: Drawing not to scale
Millimeters
Nom
Inches
Nom
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length 8M (.25)
Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13)
Package Body Length 64M (.18)
Package Body Width 8M (.25)
Package Body Width 16M (.25/.18/.13) 32M (.18/.13)
Package Body Width 32M (.25)
Package Body Width 64M (.18)
Symbol
A
A1
A2
b
D
D
D
E
E
E
E
e
Min
Max
Min
Max
0.0394
1.000
0.150
0.0059
0.0128
0.665
0.375
7.910
7.286
7.700
6.500
6.964
10.850
9.000
0.750
46
0.0262
0.0148
0.325
7.810
7.186
7.600
6.400
6.864
0.425
8.010
7.386
7.800
6.600
7.064
10.860
9.100
0.0167
0.2829
0.2992
0.2520
0.2702
0.4232
0.3504
0.2868
0.3031
0.2559
0.2742
0.4272
0.3543
0.0295
46
0.2908
0.3071
0.2598
0.2781
0.4276
0.3583
10.750
8.900
Pitch
Ball (Lead) Count 8M, 16M
N
Ball (Lead) Count 32M
N
47
47
Ball (Lead) Count 64M
N
48
48
Seating Plane Coplanarity
Y
0.100
1.430
1.118
1.325
1.475
1.707
3.650
2.725
0.0039
0.0563
0.0440
0.0522
0.0581
0.0672
0.1437
0.1073
Corner to Ball A1 Distance Along D 8M (.25)
Corner to Ball A1 Distance Along D 16M (.25/.18/.13) 32M (.18/.13)
Corner to Ball A1 Distance Along D 64M (.18)
Corner to Ball A1 Distance Along E 8M (.25)
Corner to Ball A1 Distance Along E 16M (.25/.18/.13) 32M (.18/.13)
Corner to Ball A1 Distance Along E 32M (.25)
Corner to Ball A1 Distance Along E 64M (.18)
S1
S1
S1
S2
S2
S2
S2
1.230
0.918
1.125
1.275
1.507
3.450
2.525
1.330
1.018
1.225
1.375
1.607
3.550
2.625
0.0484
0.0361
0.0443
0.0502
0.0593
0.1358
0.0994
0.0524
0.0401
0.0482
0.0541
0.0633
0.1398
0.1033
64
Datasheet
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Intel Advanced+ Boot Block Flash Memory (C3)
Figure 20. TSOP Package Drawing & Dimensions
Z
A
2
See Notes 1, 2, 3 and 4
Pin 1
e
See Detail B
E
Y
D
1
A
1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
b
0
L
A5568-02
Dimensions
Family: Thin Small Ou-tLine Package
Symbol
Millimeters
Nom
Inches
Nom
Min
Max
1.200
Notes
Min
Max
Notes
Package Height
Standoff
A
A1
A2
b
0.047
0.050
0.002
Package Body Thickness
Lead Width
0.950 1.000 1.050
0.150 0.200 0.300
0.100 0.150 0.200
18.200 18.400 18.600
11.800 12.000 12.200
0.500
0.037 0.039 0.041
0.006 0.008 0.012
0.004 0.006 0.008
0.717 0.724 0.732
0.465 0.472 0.480
0.0197
Lead Thickness
c
Plastic Body Length
Package Body Width
Lead Pitch
D1
E
e
Terminal Dimension
Lead Tip Length
Lead Count
D
19.800 20.000 20.200
0.500 0.600 0.700
48
0.780 0.787 0.795
0.020 0.024 0.028
48
L
N
Lead Tip Angle
Ø
Y
0°
3°
5°
0°
3°
5°
Seating Plane Coplanarity
Lead to Package Offset
0.100
0.004
Z
0.150 0.250 0.350
0.006 0.010 0.014
1. One dimple on package denotes Pin 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
4. Pin 1 will always supersede above pin one notes.
Datasheet
65
£
Intel Advanced+ Boot Block Flash Memory (C3)
Figure 21. Easy BGA Package Drawing & Dimension
Ball A1
Corner
Ball A1
Corner
D
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
A
B
C
D
E
b
e
E
F
F
G
H
G
H
Top View - Ball side down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Side View
Note: Drawing not to scale
Dimensions Table
Millimeters
Min
Inches
Min
Symbol
A
Nom
Max Notes
1.200
Nom
Max
Package Height
0.0472
1
Ball Height
A
A
0.250
0.0098
2
Package Body Thickness
Ball (Lead) Width
Package Body Width
Package Body Length
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
0.780
0.430
10.000
13.000
1.000
64
0.0307
0.0169
0.3937
0.5118
0.0394
64
b
D
E
[e]
N
Y
0.330
9.900
12.900
0.530
10.100
13.100
0.0130
0.3898
0.5079
0.0209
0.3976
0.5157
1
1
0.100
1.600
3.100
0.0039
0.0630
0.1220
1
S
S
1.400
2.900
1.500
3.000
1
1
0.0551
0.1142
0.0591
0.1181
2
Note: (1) Package dimensions are for reference only. These dimensions are estimates based
on die size, and are subject to change.
66
Datasheet
£
Intel Advanced+ Boot Block Flash Memory (C3)
Appendix E Additional Information
Order Number
Document/Tool
297938
292216
3 Volt Advanced+ Boot Block Flash Memory Specification Update
AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory
AP-657 Designing with the Advanced+ Boot Block Flash Memory
Architecture
292215
Contact your Intel
Representative
Intel® Flash Data Integrator (FDI) Software Developer’s Kit
297874
IFDI Interactive: Play with Intel® Flash Data Integrator on Your PC
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at ‘http://www.intel.com/design/flash’ for technical
documentation and tools.
Datasheet
67
£
Intel Advanced+ Boot Block Flash Memory (C3)
Appendix F Ordering Information
Figure 22. Component Ordering Information
T E 2 8 F 3 2 0 C 3 T C 7 0
Access Speed (ns)
(70, 80, 90, 100, 110)
Package
TE = 48-Lead TSOP
GT = 48-Ball µBGA* CSP
GE = VF BGA CSP
RC = Easy BGA
Lithography
A = 0.25 µm
C = 0.18 µm
D = 0.13 µm
Product line designator
for all Intel® Flash products
T = Top Parameter Boot
B = Bottom Parameter Boot
Device Density
640 = x16 (64 Mbit)
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
800 = x16 (8 Mbit)
Product Family
C3 = 3 Volt Advanced+ Boot Block
VCC = 2.7 V–3.6 V
VPP = 2.7 V–3.6 V or
11.4 V–12.6 V
VALID COMBINATIONS (All Extended Temperature)
48-Lead TSOP
48-Ball µBGA* CSP
48-Ball VF BGA
Easy BGA
Extended
64 Mbit
TE28F640C3TC80
TE28F640C3BC80
GE28F640C3TC80
GE28F640C3BC80
RC28F640C3TC80
RC28F640C3BC80
TE28F320C3TD70
TE28F320C3BD70
RC28F320C3TD70
RC28F320C3BD70
TE28F320C3TC70
TE28F320C3BC70
TE28F320C3TC90
TE28F320C3BC90
TE28F320C3TA100
TE28F320C3BA100
GE28F320C3TD70
GE28F320C3BD70
GE28F320C3TC70
GE28F320C3BC70
GE28F320C3TC90
GE28F320C3BC90
RC28F320C3TD90
RC28F320C3BD90
RC28F320C3TC90
RC28F320C3BC90
RC28F320C3TA100
RC28F320C3BA100
GT28F320C3TA100
GT28F320C3BA100
GT28F320C3TA110
GT28F320C3BA110
Extended
32 Mbit
TE28F320C3TA110
TE28F320C3BA110
RC28F320C3TA110
RC28F320C3BA110
TE28F160C3TD70
TE28F160C3BD70
RC28F160C3TD70
RC28F160C3BD70
TE28F160C3TC70
RC28F160C3TC70
GE28F160C3TD70
GE28F160C3BD70
GE28F160C3TC70
GE28F160C3BC70
GE28F160C3TC80
GE28F160C3BC80
GE28F160C3TC90
GE28F160C3BC90
TE28F160C3BC70
RC28F160C3BC70
TE28F160C3TC80
TE28F160C3BC80
TE28F160C3TC90
TE28F160C3BC90
TE28F160C3TA90
TE28F160C3BA90
TE28F160C3TA110
TE28F160C3BA110
GT28F160C3TA90
GT28F160C3BA90
GT28F160C3TA110
GT28F160C3BA110
RC28F160C3TC80
RC28F160C3BC80
RC28F160C3TC90
RC28F160C3BC90
RC28F160C3TA90
RC28F160C3BA90
RC28F160C3TA110
RC28F160C3BA110
Extended
16 Mbit
TE28F800C3TA90
TE28F800C3BA90
TE28F800C3TA110
TE28F800C3BA110
GE28F800C3TA70
GE28F800C3BA70
GE28F800C3TA90
GE28F800C3BA90
RC28F800C3TA90
RC28F800C3BA90
RC28F800C3TA110
RC28F800C3BA110
Extended
8 Mbit
NOTE: The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples
only, the first character signifies either “E” for engineering samples or “S” for silicon daisy chain
samples. All other assembly codes without an “E” or “S” as the first character are production units.
68
Datasheet
相关型号：
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