JS29F02G08AANB3 [NUMONYX]
Flash, 256MX8, 18ns, PDSO48, LEAD FREE, PLASTIC, TSOP1-48;
| 型号： | JS29F02G08AANB3 |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 256MX8, 18ns, PDSO48, LEAD FREE, PLASTIC, TSOP1-48 光电二极管 内存集成电路 |
| 文件： | 总54页 (文件大小：1681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VCC
VSS
I/O [7:0]
I/O [15:0]
I/O
Control
Address Register
Status Register
Command Register
CE#
CLE
Column Decode
ALE
WE#
Control
Logic
RE#
WP#
Data Register
Cache Register
R/B#
Blocks
BA[16:6]
0
0
0
1
1
1
2
2
2
2,047
•
•
•
•
•
•
•
•
•
•
•
• • • • • • •
Pages
PA[5:0]
63
Bytes
CA[11:0]
2,047 • • • 2,111
Spare area
•
•
• • • • • • • • • • • • • •
2,112 bytes
I/O 0
I/O 7
Cache Register
Data Register
2,048
2,048
64
64
64 pages = 1 block
(128K + 4K) bytes
1 Block
2,048 blocks
per device
1 page
1 block
=
(2K + 64) bytes
=
=
(2K + 64) bytes x 64 pages
(128K + 4K) bytes
1 device
=
=
(2K + 64) bytes x 64 pages
x 2,048 blocks
2,112Mb
Blocks
BA[16:6]
0
0
0
1
1
1
2
2
2
2,047
•
•
•
•
•
•
•
•
•
•
•
• • • • • • •
Pages
PA[5:0]
63
Words
CA[10:0]
1,023 • • • 1,055
Spare area
•
•
• • • • • • • • • • • • • •
1,056 words
1,024
I/O 0
I/O 15
Cache Register
Data Register
32
32
1,024
64 pages = 1 block
(64K + 2K) words
1 Block
2,048 blocks
per device
1 page
1 block
=
(1K + 32) words
=
=
(1K + 32) words x 64 pages
(64K + 2K) words
1 device
=
=
(1K + 32) words x 64 pages
x 2,048 blocks
2,112Mb
x16
x8
x8
x16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VSS
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
1 l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
NC
DNU or Vss DNU or Vss
VCC
VCC
VCC
VCC
VSS
VSS
NC
NC
NC
VSS
NC
NC
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
CLE
ALE
WE#
WP#
DNU
DNU
DNU
NC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
CLE
ALE
WE#
WP#
DNU
DNU
DNU
NC
NC
NC
NC
NC
VSS
NC
.
PLASTIC PACKAGE MATERIAL: NOVOLAC EPOXY
PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100% Sn
20.00 ±0.25
18.40 ±0.08
PACKAGE WIDTH AND LENGTH DO NOT
INCLUDE MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE.
0.25
0.50 TYP
PIN #1 INDEX
12.00 ±0.08
0.20 ±0.05
0.25
GAGE
PLANE
0.10
+0.03
-0.02
0.15
SEE DETAIL A
1.20 MAX
+0.10
-0.05
0.10
0.50 ±0.1
0.80
DETAIL A
3V device: ≈ 2.5V
1.8V device: ≈ 1.5V
3V device: ≈ 2.5V
1.8V device: ≈ 1.5V
Vcc
WP#
WE#
R/B#
HIGH
10µs
Don’t Care
Undefined
NVB
TC = R * C
where R = R (resistance of pull-up resistor), and C = total capacitive load
p
VCC (MAX) – VOL (MAX)
1.85V
Rp (MIN, 1.8V part) =
Rp (MIN, 3.3V part) =
=
=
IOL + ΣIL
3mA + ΣIL
VCC (MAX) – VOL (MAX)
3.2V
IOL + ΣIL
8mA + ΣIL
Where ΣIL is the sum of the input currents
of all devices tied to the R/B# pin.
Rp
VCC
R/B#
Open drain output
IOL
GND
Device
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
t
t
Fall
Rise
V
-1
0
2
4
0
2
4
6
TC
Vcc 3.3
Vcc 1.8
≈
≈
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
T (µs)
0
2,000
4,000
6,000
8,000
10,000
12,000
Rp (Ω)
IOL at 3.60V (mA)
IOL at 1.95V (mA)
CLE
CE#
t
CLR
t
WC
WE#
ALE
t
WB
t
AR
t
t
t
R
RHZ
RC
RE#
t
t
RR
RP
D
D
OUT
N
OUT
N + 1
D
OUT
M
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
I/Ox
00h
30h
Busy
R/B#
Don’t Care
t
R
R/B#
RE#
Address
(5 cycles)
Address
(2 cycles)
Data output
I/Ox
00h
30h
Data output
05h
E0h
CLE
CE#
WE#
ALE
t
t
t
t
DCBSYR2
R
DCBSYR1
DCBSYR2
R/B#
RE#
I/Ox
00h
Address (5 cycles)
30h
31h
31h
3Fh
Data output
Data output
Data output
(Serial access)
(Serial access)
(Serial access)
Don’t Care
CLE
CE#
WE#
t
AR
ALE
RE#
t
t
REA
WHR
90h
00h
Byte 0
Byte 1
Byte 2
Byte 3
I/Ox
Address, 1 Cycle
CE#
CLE
WE#
RE#
t
CLR
t
REA
70h
Status output
I/Ox
t
PROG
R/B#
I/Ox
80h
Address (5 cycles)
DIN
10h
70h
Status
I/O 0 = 0 PROGRAM successful
I/O 0 = 1 PROGRAM error
t
PROG
R/B#
I/Ox
80h
Address (5 cycles)
DIN
85h
Address (2 cycles)
DIN
10h
70h
Status
1
t
t
t
t
CBSY
CBSY
CBSY
LPROG
R/B#
I/Ox
Address/
data input
Address/
data input
Address/
data input
Address/
data input
80h
15h
80h
15h
80h
15h
80h
10h
A: Without status reads
1
t
t
CBSY
70h
LPROG
R/B#
I/Ox
Address/
data input
Status
output2
Address/
data input
Status
output2
80h
15h
80h
10h
70h
B: With status reads
t
t
PROG
R
R/B#
I/Ox
Address
(5 cycles)
Address
(5 cycles)
00h
35h
85h
10h
70h
Status
t
t
R
PROG
R/B#
I/Ox
Address
(5 cycles)
Address
(5 cycles)
Address
(2 cycles)
00h
35h
85h
Data 85h
Data 10h
70h
Status
Unlimited number
of repetitions
CLE
CE#
WE#
ALE
t
BERS
R/B#
RE#
I/Ox
60h
D0h
70h
Address input (3 cycles)
Status
I/O 0 = 0 ERASE successful
I/O 0 = 1 ERASE error
Don’t Care
CLE
CE#
t
WC
WE#
ALE
t
t
WB PROG
RE#
I/Ox
Col
Add1
Col
Add2
OTP
OTP
DIN
N
DIN
M
A0h
00h
10h
70h
Status
Page1
Page1
OTPDATA INPUT
Command
1 up to m ybtes
Serial Input
PROGRAM
Command
READ STATUS
Command
R/B#
OTP data written
(following "good" status confirmation)
x8 device:
x16 device:
m
m
=
=
2,112 byet s
1,056 wodrs
Don’t Care
CLE
CE#
t
WC
WE#
ALE
t
t
WB PROG
RE#
Col
Col
OTP
DIN
N
DIN
M
I/Ox
A0h
00h
00h
10h
70h
Status
Add 1 Add 2
Page1
OTP DATA INPUT
Command
1 up to m bytes PROGRAM
Serial Input
Command
READ STATUS
Command
R/B#
OTP data written
(following "good" status confirmation)
x8 device: m
x16 device: m
=
=
2,112 bytes
1,056 words
Don’t Care
CLE
CE#
t
WC
WE#
ALE
t
t
PROG
WB
RE#
Col
00h
Col
00h
I/Ox
A5h
01h
00h
00h
10h
70h
Status
OTP DATA PROTECT
Command
PROGRAM
Command
READ STATUS
Command
R/B#
1
OTP data protected
Don’t Care
CLE
CE#
WE#
ALE
t
R
RE#
Col
Add 1
Col
Add 2
OTP
D
OUT
N
D
OUT
N + 1
D
OUT
M
I/Ox
AFh
00h
00h
30h
Page1
Busy
R/B#
Don’t Care
CLE
CE#
t
WB
WE#
R/B#
I/Ox
t
RST
FFh
RESET
command
WE#
I/Ox
WP#
R/B#
t
WW
60h
D0h
WE#
I/Ox
WP#
R/B#
t
WW
60h
80h
80h
D0h
10h
10h
WE#
I/Ox
WP#
R/B#
t
WW
WE#
I/Ox
WP#
R/B#
t
WW
CLE
CE#
t
t
CLH
CLS
t
t
CH
CS
t
WP
WE#
ALE
t
t
ALH
DH
ALS
t
t
DS
I/Ox
Command
Don’t Care
CLE
t
CLS
t
CS
t
WC
CE#
t
t
WH
WP
t
WE#
ALS
t
ALH
ALE
I/Ox
t
t
DS
DH
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
Undefined
Don’t Care
CLE
t
CLH
CE#
ALE
t
ALS
t
CH
t
WC
t
t
t
WP
WP
WP
WE#
I/Ox
t
WH
t
t
t
t
t
t
DS DH
DIN 0
DS DH
DS DH
1
DIN 1
DIN Final
Don’t Care
t
CEA
CE#
RE#
t
t
t
REA
t
CHZ
REA
REA
t
t
t
RP
REH
OH
t
t
RHZ
RHZ
OH
t
I/Ox
R/B#
D
OUT
DOUT
DOUT
t
t
RR
RC
Don’t Care
t
CLR
CLE
t
t
CLS CLH
t
CS
CE#
t
t
CH
WP
WE#
t
t
CEA
CHZ
t
t
t
OH
WHR
RP
RE#
t
t
RHZ
OH
t
t
t
IR
t
DS DH
REA
Status output
70h
I/Ox
Don’t Care
CLE
CE#
t
CLR
t
WC
WE#
ALE
t
WB
t
AR
t
t
t
R
RHZ
RC
RE#
t
t
RR
RP
D
D
OUT
N
OUT
N + 1
D
OUT
M
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
I/Ox
00h
30h
Busy
R/B#
Don’t Care
CLE
CE#
RE#
ALE
t
R
R/B#
WE#
I/Ox
00h
Address (5 Ccycles)
30h
Data output
t
CEA
CE#
t
REA
RE#
Don’t Care
Out
I/Ox
CLE
CE#
t
CLR
WE#
ALE
t
WB
t
WHR
t
AR
t
t
RC
R
t
REA
RE#
t
RR
DOUT
DOUT
N + 1
DOUT
DOUT
Col
add 1
Col
add 2
Row
add1
Row
add 2
Row
add 3
Col
add 1
Col
add 2
I/Ox
00h
30h
05h
E0h
N
M
M + 1
Column address N
Column address M
Busy
R/B#
Don’t Care
CLE
CE#
t
t
t
CLS CLH
t
CH
CS
t
WC
WE#
ALE
t
CEA
t
t
RC
t
RE#
R
t
t
t
WB
WB
WB
REA
t
t
DS DH
t
RR
Col
add
Col
add
Row
Row
add
Row
add 3
DOUT
0
DOUT
1
DOUT
0
00h
30h
31h
31h
I/Ox
1
2
add
1
2
Column address
00h
Page address
Page address
Page address
M + 1
M
M
t
t
DCBSYR2
DCBSYR1
R/B#
Column address 0
Column address 0
1
Continued to
of next page
1
Don’t Care
Undefined
CLE
t
t
t
CLS CLH
t
CS
CH
CE#
WE#
ALE
RE#
t
CEA
t
RC
t
WB
t
RR
t
t
WB
WB
t
t
t
DS DH
31h
REA
D
OUT
0
D
OUT
1
D
OUT
0
D
OUT
1
D
OUT
0
D
OUT
1
31h
3Fh
I/Ox
R/B#
t
t
t
DCBSYR2
Page address
M + 1
Page address
M + 2
Page address
M + x
DCBSYR2
DCBSYR2
Column address 0
Column address 0
Column address 0
Don’t Care
1
Undefined
Continued from
of previous page
1
CLE
CE#
t
t
t
CLS CLH
t
CH
CS
t
WC
WE#
ALE
t
CEA
t
RC
RE#
t
REA
t
t
DS DH
Col
add
Col
add
Row
Row
add
Row
add 3
D
OUT
0
D
OUT
1
D
OUT
0
00h
30h
70h
Status
31h
70h
Status
00h
DOUT
31h
70h
Status
00h
I/Ox
1
2
add
1
2
Column address
00h
Page address
M
Page address
M
Page address
M + 1
I/O 5 = 0, Busy
I/O 6 = 0, Cache busy
I/O 6 = 0, Cache busy
=
1, Ready
=
1, Cache ready
=
1, Cache ready
Column address 0
Column address 0
1
Don’t Care
Continued to
of next page
1
CLE
CE#
t
t
t
CLS
CLH
t
CS
CH
WE#
ALE
t
CEA
t
RC
RE#
t
t
t
DS DH
REA
D
OUT
0
D
OUT
1
D
OUT
0
D
OUT
1
D
OUT
0
D
OUT
1
I/Ox
DOUT
31h
70h
Status
00h
DOUT
31h
70h
Status
00h
DOUT
3Fh
70h
Status
00h
DOUT
Page address
M + 1
Page address
M + 2
Page address
M + x
I/O 6 = 0, Cache busy
1, Cache ready
I/O 6 = 0, Cache busy
1, Cache ready
I/O 6 = 0, Cache busy
1, Cache ready
=
=
=
Column address 0
Column address 0
Column address 0
1
Don’t Care
Continued from
of previous page
1
CLE
CE#
WE#
t
AR
ALE
RE#
t
t
REA
WHR
90h
00h
Byte 0
Byte 1
Byte 2
Byte 3
I/Ox
Address, 1 Cycle
CLE
CE#
t
t
WC
ADL
WE#
ALE
t
t
PROG
WB
RE#
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
DIN
N
DIN
M
I/Ox
80h
10h
70h
Status
SERIAL DATA
INPUT command
1 up to m bytes
serial input
PROGRAM
command
READ STATUS
command
R/B#
x8 device: m = 2,112 byte
Don’t Care
CLE
CE#
WE#
ALE
I/Ox
80h
Address (5 cycles)
Data
input
Data
input
10h
t
t
CH
CS
CE#
t
WP
WE#
Don’t Care
CLE
CE#
t
t
t
ADL
WC
ADL
WE#
ALE
t
t
PROG
WB
RE#
Col
Col
Row
Row
Row
D
IN
N
D
IN
N+1
Col
Col
D
IN
N
DIN
80h
85h
Status
I/Ox
10h
70h
add 1 add 2 add 1 add 2 add 3
add 1 add 2
N+1
SERIAL DATA
INPUT command
Serial input
RANDOM Column address
DATA INPUT
Serial input
PROGRAM
command
READ STATUS
command
command
R/B#
Don’t Care
CLE
CE#
t
t
ADL
WC
WE#
ALE
t
t
t
t
WHR
WB
WB PROG
RE#
t
R
Col
Col
Row
Row
Row
Col Col Row Row Row
add 1 add 2 add 1 add 2 add 3
Data
Data
I/Ox
00h
35h
85h
10h
70h
Status
add 1 add 2 add 1 add 2 add 3
1
N
READ STATUS
command
Busy
Busy
R/B#
INTERNAL
DATA MOVE
Don’t Care
CLE
CE#
t
t
ADL
WC
WE#
ALE
t
t
t
t
t
WB CBSY
WB LPROG
WHR
RE#
Col
Col
Row Row Row
add 1 add 2 add 3
D
IN
D
IN
Col
Col
Row Row Row
D
IN
DIN
80h
15h
Serial input PROGRAM
80h
10h
70h
Status
I/Ox
add 1 add 2
N
M
add 1 add 2 add 1 add 2 add 3
N
M
SERIAL DATA
INPUT
PROGRAM
R/B#
Last Page - 1
Last Page
Don’t Care
CLE
CE#
t
t
t
WC
ADL
ADL
WE#
ALE
t
t
WHR
WHR
RE#
Col
Row Row Row
Col
add 1
Col
Row
Row
Row
Col
D
IN
D
IN
D
IN
DIN
M
80h
70h Status
15h
70h
Status
70h
Status
15h
80h
I/Ox
N
M
add 1 add 2 add 1 add 2 add 3
N
add 2 add 1 add 2 add 3
SERIAL DATA
INPUT
Serial Input PROGRAM
PROGRAM
Last Page – 1
Last Page
Poll status until:
To verify successful completion of the last 2 pages:
I/O6
=
1, Ready I/O5
=
=
=
1, Ready
0, Last page PROGRAM successful
0, Last page – 1 PROGRAM successful
I/O0
I/O1
Don’t Care
CLE
CE#
t
WC
WE#
t
t
WHR
WB
ALE
RE#
t
BERS
Row
Row
Row
add 3
Status
60h
D0h
70h
I/Ox
R/B#
add 1
add 2
Row address
ERASE
command
READ STATUS
command
Busy
AUTO BLOCK
ERASE SETUP
command
I/O0
I/O0
=
=
0, Pass
1, Fail
Don’t Care
CLE
CE#
t
WB
WE#
R/B#
I/Ox
t
RST
FFh
RESET
command
J
S
2
9
F
0
2
G
0
8
A
A
N
B
3
Product Generation / Revisions
1-9 Generations, E = Engineering Samples
M = Mechanical Samples, Q = Qualification Samples
Package Designator
JS = 48-Pin Pb-Free TSOP
Process Identifier
A = 90nm, B = 72 nm, C = 50 nm
Group Designator
Product Technology Type
N = NAND Flash Memory
29F = Intel® Flash Memory
M = MLC NAND Flash Memory
Density
Operating Voltage Range
A = 3.3 V (2.70 – 3.60 V)
B = 1.8 V (1.70 – 1.95 V)
01G = 1Gb
02G = 2Gb
04G = 4Gb
08G = 8Gb
16G = 16Gb
32G = 32Gb
Device Bus Width
08=8 Bits
16 = 16 Bits
Device Configuration
# of Die
# of CE # of R/B
I/O
A
B
C
F
1
2
2
4
1
1
2
2
1
1
1
2
Common
Common
Common
Common
相关型号：
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