JS29F04G08AANB1 [INTEL]
Flash, 512KX8, 20ns, PDSO48, LEAD FREE, TSOP-48;
| 型号： | JS29F04G08AANB1 |
| 厂家： | 
INTEL |
| 描述： | Flash, 512KX8, 20ns, PDSO48, LEAD FREE, TSOP-48 光电二极管 内存集成电路 |
| 文件： | 总70页 (文件大小：1957K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® SD74 NAND Flash Memory
JS29F04G08AANB1, JS29F08G08CANB2, JS29F16G08FANB1
Datasheet
Product Features
Single-level cell (SLC) Technology
Organization:
Command set:
— Industry-standard basic NAND Flash
command set
Advanced Command Set:
— Two-plane commands
— Page size:
x8: 2,112 bytes (2,048 + 64 bytes)
— Block size: 64 pages (128K + 4K bytes)
— Plane size: 2,048 blocks
— Device size: 4Gb: 4,096 blocks; 8Gb: 8,192
blocks; 16Gb: 16,384 blocks
— Interleaved die operation
— READ UNIQUE ID (contact factory)
— Internal Data Move: Operations supported
within the plane from which data is read
Read performance:
— Random read: 25µs (MAX)
— Sequential read: 25ns (MIN)
Write performance:
Operation status byte:
— Provides software method for detecting:
— Operation completion
— Page program: 220µs (TYP)
Block erase: 1.5ms (TYP)
Data Retention:
— Pass/fail condition
— Write-protect status
Ready/busy# (R/B#) signal:
— 10 years
Endurance:
— 100,000 PROGRAM/ERASE cycles
First block (block address 00h):
— Guaranteed to be valid up to 1,000
PROGRAM/ERASE cycles
Vcc:
— Provides a hardware method for detecting
PROGRAM or ERASE cycle completion
WP# signal:
— Write protect entire device
RESET:
— Required after power-up
Package Types:
— 48-pin TSOP Type 1
Configuration:
— 2.7V – 3.6V
Operating Temperature:
— -25 oC to 85 oC
# of Die
# of CE#
# of R/B#
I/O
1
2
4
1
2
2
1
2
2
Common
Common
Common
Order Number: 312774-012US
March 2007
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All Rights Reserved.
Intel® SD74 NAND Flash Memory
Datasheet
2
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Contents
1.0 Introduction..............................................................................................................6
2.0 Functional Overview..................................................................................................6
2.1
2.2
Architecture........................................................................................................6
Memory Map and Addressing ................................................................................7
2.2.1 Memory Map for the SD74 Device...............................................................8
2.2.2 Array Organization and Addressing for JS29F04G08AANB1 and
JS29F08G08CANB2 ..................................................................................8
2.2.3 Array Organization and Addressing for JS29F16G08FANB1 ............................9
3.0 Signal Assignments and Descriptions ...................................................................... 11
4.0 Package Information............................................................................................... 13
5.0 NAND Flash Bus Operations..................................................................................... 14
5.1
5.2
5.3
5.4
5.5
5.6
Control Signals ................................................................................................. 14
Commands....................................................................................................... 14
Address Input................................................................................................... 14
Data Input ....................................................................................................... 15
READs ............................................................................................................. 15
Ready/Busy#.................................................................................................... 15
6.0 Electrical Characteristics ......................................................................................... 19
6.1 Vcc Power Cycling ............................................................................................. 19
7.0 Command Definitions .............................................................................................. 24
7.1
7.2
Command Definitions......................................................................................... 24
READ Operations............................................................................................... 25
7.2.1 PAGE READ 00h–30h .............................................................................. 25
7.2.2 RANDOM DATA READ 05h–E0h................................................................. 26
7.2.3 PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh
26
7.2.4 READ ID 90h ......................................................................................... 27
7.2.5 READ STATUS 70h ................................................................................. 30
PROGRAM Operations ........................................................................................ 31
7.3.1 PROGRAM PAGE 80h–10h........................................................................ 31
7.3.2 SERIAL DATA INPUT 80h......................................................................... 31
7.3.3 RANDOM DATA INPUT 85h....................................................................... 31
7.3.4 PROGRAM PAGE CACHE MODE 80h–15h.................................................... 32
Internal Data Move............................................................................................ 33
7.4.1 READ FOR INTERNAL DATA MOVE 00h–35h ............................................... 33
7.4.2 PROGRAM for INTERNAL DATA MOVE 85h–10h........................................... 33
BLOCK ERASE Operation .................................................................................... 34
7.5.1 BLOCK ERASE 60h–D0h .......................................................................... 34
One-Time Programmable (OTP) Area ................................................................... 35
7.6.1 OTP DATA PROGRAM A0h-10h.................................................................. 36
7.6.2 OTP DATA PROTECT A5h-10h................................................................... 37
7.6.3 OTP DATA READ AFh-30h........................................................................ 37
Two-Plane Operations........................................................................................ 38
7.7.1 TWO-PLANE Addressing .......................................................................... 38
7.7.2 TWO-PLANE PAGE READ 00h-00h-30h ...................................................... 39
7.7.3 TWO-PLANE/MULTIPLE-DIE RANDOM DATA READ 06h-E0h .......................... 39
7.7.4 TWO-PLANE PROGRAM PAGE 80h-11h-80h-10h or 80h-11h-81h-10h ............ 41
7.7.5 TWO-PLANE PROGRAM PAGE CACHE MODE 80h-11h-80h-15h or 80h-11h-81h-
15h ...................................................................................................... 43
7.3
7.4
7.5
7.6
7.7
Intel® SD74 NAND Flash Memory
Datasheet
March 2007
Order Number: 312774-012US
3
Intel® SD74 NAND Flash Memory
7.7.6 TWO-PLANE INTERNAL DATA MOVE 00h-00h-35h/85h-11h-80h-10h .............44
7.7.7 TWO-PLANE READ for INTERNAL DATA MOVE 00h-00h-35h..........................44
7.7.8 TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-80h-10h or 85h-11h-
81h-10h................................................................................................45
7.7.9 TWO-PLANE BLOCK ERASE 60h-60h-D0h...................................................46
7.7.10 TWO-PLANE/MULTIPLE-DIE READ STATUS 78h ...........................................47
Interleaved Die Operations..................................................................................48
7.8.1 Interleaved PROGRAM PAGE Operations.....................................................48
7.8.2 Interleaved PROGRAM PAGE CACHE MODE Operations.................................49
7.8.3 Interleaved TWO-PLANE PROGRAM PAGE Operations...................................50
7.8.4 Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE Operations ...............51
7.8.5 Interleaved BLOCK ERASE Operations........................................................53
7.8.6 Interleaved TWO-PLANE BLOCK ERASE Operations......................................53
RESET Operation ...............................................................................................54
7.9.1 RESET FFh.............................................................................................54
7.8
7.9
7.10 WRITE PROTECT Operation .................................................................................55
8.0 Error Management ...................................................................................................57
9.0 Timing Diagrams......................................................................................................58
10.0 Ordering Information...............................................................................................69
Intel® SD74 NAND Flash Memory
Datasheet
4
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Revision History
Date
Revision Description
March 2007
012
011
•
•
Added missing Test Conditions table.
February 2007
Changed comment for the NVB spec for the 16Gb device. Edited some typos in rev 010.
Deleted line item JS29F08G08CANB1.
Added notes about 81H in second command cycle of dual plane program operations in Section
7.7.4, “TWO-PLANE PROGRAM PAGE 80h-11h-80h-10h or 80h-11h-81h-10h” on page 41.
•
•
February 2007
November 2006
13-Sep-06
010
009
008
•
•
Updated the Table 20, “Intel® NAND Flash Memory Ordering Information” on page 69.
Deleted the OCPL figure in the package section.
•
Updated the R/B# and R/B2# description in Section 3.0, “Signal Assignments and
Descriptions” on page 11.
•
Updated the part number decoder in Section 10.0, “Ordering Information” on page 69.
•
•
Added configuration table to title page.
Updated the ordering information and part number decoder in Section 10.0, “Ordering
Information” on page 69.
8-Sep-06
007
•
Changed the 8 Gb part number from JS29F08G08BANB1 to JS29F08G08CANB1 throughout the
document to reflect the change to 2 CEs.
•
•
•
•
Updated document to reflect 2 CE#s for the dual-die package device.
Section 7.2.4, “READ ID 90h” on page 27: Revised description.
Package diagrams have been updated.
Figure 1, “Intel® SD74 NAND Flash Memory Functional Block Diagram” on page 7: Added “(2
planes)” to the NAND Flash Array.
•
•
•
Table 16, “Two-Plane Command Set” on page 25: Deleted “MULTIPLE-DIE READ STATUS” from
command 06h and updated note 3.
Section 7.7.2, “TWO-PLANE PAGE READ 00h-00h-30h” on page 39: Updated the fourth
paragraph.
Section 7.7.10, “TWO-PLANE/MULTIPLE-DIE READ STATUS 78h” on page 47: Updated first
paragraph and added a new paragraph at the end of the section.
22-Aug-06
006
•
•
Section 7.8, “Interleaved Die Operations” on page 48: Updated final paragraph.
Section 7.9.1, “RESET FFh” on page 54: Added “to all CE#s” and “and OTP operations” to the
last paragraph.
•
Section 6.1, “Vcc Power Cycling” on page 19: Changed 1ms to 10µs in first paragraph; added
“to all CE#s” in last paragraph.
•
•
•
Figure 13, “AC Waveforms During Power Transitions” on page 20: Updated WE# signal.
Table 14, “PROGRAM/ERASE Characteristics” on page 23: Added note 4.
Figure 36, “TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle” on page 48: Added figure
showing all timing parameters.
•
Section 4.0, “Package Information” on page 13: Inserted recently updated versions of package
diagrams.
Updated the Operating Temperature range.
Updated with new product naming convention, and document title change.
1-Aug-06
29-Jun-06
005
004
Corrected typos in Section 6.0, “Electrical Characteristics”.
The maximum number of programming operations before an erase is required has been reduced
from 8 to 4. This change is reflected in Table 14, “PROGRAM/ERASE Characteristics” on page 23 in
the Electrical Characteristics chapter and Section 7.3.1, “PROGRAM PAGE 80h–10h” on page 31.
15-Jun-06
003
•
Adjusted Product Features section on page 1, including Write Performance Page Program
values from to
02-Jun-06
002
001
•
Adjusted electrical specifications. See Section 6.0, “Electrical Characteristics” on page 19 and
the product features section on page 1.
Changes to Section 7.0, “Command Definitions” on page 24.
•
•
March 2006
Initial Release.
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
5
Intel® SD74 NAND Flash Memory
1.0
Introduction
NAND Flash technology provides a cost-effective solution for applications requiring
high-density solid-state storage. The JS29F4G08AANB1 is a 4Gb NAND Flash memory
device. The JS29F08G08CANB2 is a two-die stack that operate as two independent 4Gb
devices, providing a total storage capacity of 8Gb in a single package. The
JS29F16G08FANB1 is a four-die stack that operate as two independent 8Gb devices,
providing a total storage capacity of 16Gb in a single, space-saving package. Intel®
NAND Flash devices include standard NAND Flash features as well as new features
designed to enhance system-level performance.
Intel® NAND Flash device uses a highly multiplexed 8-bit bus (I/O[7:0]) to transfer
data, addresses, and instructions. The five command pins (CLE, ALE, CE#, RE#, WE#)
implement the NAND Flash command bus interface protocol. Additional pins control
hardware write protection (WP#) and monitor device status (R/B#).
This hardware interface creates a low-pin-count device with a standard pinout that is
the same from one density to another, allowing future upgrades to higher densities
without board redesign.
The Intel® SD74 NAND Flash Memory device contains two planes per die. Each plane
consists of 2,048 blocks. Each block is subdivided into 64 programmable pages. Each
page consists of 2,112 bytes. The pages are further divided into a 2,048-byte data
storage region with a separate 64-byte area. The 64-byte area is typically used for
error management functions.
The contents of each page can be programmed in 220µs, and an entire block can be
erased in 1.5ms (TYP). The Intel® SD74 NAND Flash Memory device is a high
performance part with a maximum tPROG specification of 500µs, a maximum tBERS
specification of 2ms, and a maximum tR specification of 25µs. On-chip control logic
automates PROGRAM and ERASE operations to maximize cycle endurance. ERASE/
PROGRAM endurance is specified at 100,000 cycles when using appropriate error
correcting code (ECC) and error management.
2.0
Functional Overview
This section provides an overview of the device in the following sections:
• Section 2.1, “Architecture” on page 6
• Section 2.2, “Memory Map and Addressing” on page 7
2.1
Architecture
These devices use standard NAND Flash electrical and command interfaces. Data,
commands, and addresses are multiplexed onto the same signals and received by I/O
control circuits. This provides a memory device with a low signal count. The commands
received at the I/O control circuits are latched by a command register and are
transferred to control logic circuits for generating internal signals to control device
operations. The addresses are latched by an address register and sent to a row decoder
or a column decoder to select a row address or a column address, respectively.
The data is transferred to or from the NAND Flash memory array, byte by byte through
a data register and a cache register. The cache register is closest to I/O control circuits
and acts as a data buffer for the I/O data, whereas the data register is closest to the
memory array and acts as a data buffer for the NAND Flash memory array operation.
Intel® SD74 NAND Flash Memory
Datasheet
6
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
The NAND Flash memory array is programmed and read in page-based operations and
is erased in block-based operations. During normal page operations, the data and
cache registers are tied together and act as a single register. During cache operations
the data and cache registers operate independently to increase data throughput.
These devices also have a status register that reports the status of device operation.
Figure 1.
Intel® SD74 NAND Flash Memory Functional Block Diagram
VCC
VSS
I/O
Control
I/Ox
Address Register
Status Register
Command Register
CE#
CLE
Column Decode
ALE
WE#
Control
Logic
NAND Flash
Array
RE#
WP#
(2 planes)
Data Register
Cache Register
R/B#
2.2
Memory Map and Addressing
This section includes the following sections describing memory mapping and array
organization for the x8 device.
• Section 2.2.1, “Memory Map for the SD74 Device” on page 8
• Section 2.2.2, “Array Organization and Addressing for JS29F04G08AANB1 and
JS29F08G08CANB2” on page 8
• Section 2.2.3, “Array Organization and Addressing for JS29F16G08FANB1” on
page 9
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
7
Intel® SD74 NAND Flash Memory
2.2.1
Memory Map for the SD74 Device
Figure 2.
Memory Map: SD74 Device
Blocks
4Gb,8Gb:BA[17:6]
16Gb: BA[18:6]
0
0
0
1
1
1
2
2
2
4,095
•
•
•
•
•
•
•
•
•
•
•
• • • • • • •
16Gb:
8,192 blocks per CE#
Pages
PA[5:0]
63
Bytes
CA[11:0]
2,047 • •• 2,111
Spare area
•
•
• • • • •• • ••• • • •
Table 1.
Operational Example: SD74 Device
Block
Page Min Address in Page Max Address in Page
Out of Bounds Addresses in Page
0
0
0
1
0x0000000000
0x0000010000
0x0000020000
…
0x000000083F
0x000001083F
0x000002083F
…
0x0000000840–0x0000000FFF
0x0000010840–0x0000010FFF
0x0000020840–0x0000020FFF
0
2
…
…
4,095
4,095
62
63
0x03FFFE0000
0x03FFFF0000
0x03FFFE083F
0x03FFFF083F
0x03FFFE0840–0x03FFFE0FFF
0x03FFFF0840–0x03FFFF0FFF
Note:
As shown in Table 2, the high nibble of ADDRESS cycle 2 has no assigned address bits;
however, these 4 bits must be held LOW during the ADDRESS cycle to ensure that the
address is interpreted correctly by the NAND Flash device. These extra bits are
accounted for in ADDRESS cycle 2 even though they do not have address bits assigned
to them.
The 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8
device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of
each page are “out of bounds,” do not exist in the device, and cannot be addressed.
2.2.2
Array Organization and Addressing for JS29F04G08AANB1 and
JS29F08G08CANB2
Addresses for JS29F04G08AANB1 and JS29F08G08CANB2 devices are loaded using a
five-cycle sequence. The first two cycles contain the column address, and the last three
cycles contain the page and block addresses. The column address is a 12-bit address.
The page address is a 6-bit address used to address 64 pages in each block, and the
block address is a 12-bit address used to address 4096 blocks per CE# in the device.
Intel® SD74 NAND Flash Memory
Datasheet
8
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Figure 3.
Array Organization: JS29F04G08AANB1 and JS29F08G08CANB2
2,112 bytes
2,112 bytes
I/O7
I/O0
Cache Register
Data Register
2,048
2,048
2,048
64
64
64
64
2,048
1 page
=
(2K + 64 bytes)
1 block
=
=
(2K + 64) bytes x 64 pages
(128K + 4K) bytes
2,048 blocks
per plane
1 Block
1 Block
1 plane
1 device
=
=
(128K + 4K) bytes x 2,048 blocks
2,112Mb
4,096 blocks
per device
=
=
2,112Mb x 2 planes
4,224Mb
Plane of
even-numbered blocks
Plane of
odd-numbered blocks
(0, 2, 4, 6, ..., 4,092, 4,094) (1, 3, 5, 7, ..., 4,093, 4,095)
Note: For the 8Gb JS29F08G08CANB2, the 4Gb array organization shown here applies to each chip enable
(CE1# and CE2#).
Table 2.
Array Addressing: JS29F04G08AANB1 and JS29F08G08CANB2
Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
First
CA7
LOW
BA7
CA6
LOW
BA6
CA5
LOW
PA5
CA4
LOW
PA4
CA3
CA11
PA3
CA2
CA10
PA2
CA1
CA9
PA1
CA0
CA8
PA0
Second
Third
Fourth
Fifth
BA15
LOW
BA14
LOW
BA13
LOW
BA12
LOW
BA11
LOW
BA10
LOW
BA9
BA17
BA8
BA16
Notes:
1.
Definitions:
— CAx = column address
— PAx = page address
— BAx = block address
Block address concatenated with page address = actual page address.
If CA11 = “1” then CA[10:6] must be “0.”
2.
3.
2.2.3
Array Organization and Addressing for JS29F16G08FANB1
Addresses for JS29F16G08FANB1 devices are loaded using a five-cycle sequence. The
first two cycles contain the column address, and the last three cycles contain the page
and block addresses. The column address is a 12-bit address. The page address is a 6-
bit address used to address 64 pages in each block, and the block address is a 13-bit
address used to address 8192 blocks per CE# in the device. The most significant block
address bit is also a die selector.
Intel® SD74 NAND Flash Memory
Datasheet
March 2007
Order Number: 312774-012US
9
Intel® SD74 NAND Flash Memory
Figure 4.
Array Organization: JS29F16G08FANB1
Die 0
Die 1
2,112 bytes
2,112 bytes
2,112 bytes
2,112 bytes
I/O7
I/O0
Cache Register
Data Register
2,048
2,048
2,048
2,048
2,048
64
64
64
64
64
64
64
64
2,048
2,048
2,048
1 page = (2K + 64 bytes)
1 block = (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
2,048 blocks
per plane
1 Block
1 Block
1 Block
1 Block
1 plane = (128K + 4K) bytes x 2,048 blocks
= 2,112Mb
4,096 blocks
per die
1 die
= 2,112Mb x 2 planes
= 4,224Mb
1 device = 4,224Mb x 2 die
= 8,448Mb
Plane 0: even-
numbered blocks
(0, 2, 4, 6, ...,
Plane 1: odd-
numbered blocks
(1, 3, 5, 7, ...,
Plane 0: even-
Plane 1: odd-
numbered blocks
(4096, 4098, ...,
8,188, 8,190)
numbered blocks
(4,097,4,099, ...,
8,189, 8,191)
4,092, 4,094)1
4,093, 4,095)
Notes:
1.
Die 0, Plane 0: BA18 = 0, BA6 = 0
Die 0, Plane 1: BA18 = 0, BA6 = 1
Die 1, Plane 0: BA18 = 1, BA6 = 0
Die 1, Plane 1: BA18 = 1, BA6 = 1
2.
For the JS29F16G08FANB1device, the 8Gb array organization shown here applies to each chip enable
(CE# and CE2#).
Table 3.
Array Addressing: JS29F16G08FANB1
Cycle
I/O7
CA7
I/O6
CA6
I/O5
CA5
I/O4
CA4
I/O3
CA3
I/O2
CA2
I/O1
CA1
I/O0
CA0
First
Second
Third
Fourth
Fifth
LOW
BA7
LOW
BA6
LOW
PA5
LOW
PA4
CA11
PA3
CA10
PA2
CA9
PA1
CA8
PA0
BA15
LOW
BA14
LOW
BA13
LOW
BA12
LOW
BA11
LOW
BA10
BA183
BA9
BA17
BA8
BA16
Note:
1.
Definitions:
— CAx = column address
— PAx = page address
— BAx = block address
If CA11 = “1” then CA[10:6] must be “0.”
Die address boundary: 0 = 0 – 4 Gb, 1 = 4 Gb – 8 Gb.
2.
3.
§ §
Intel® SD74 NAND Flash Memory
Datasheet
10
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
3.0
Signal Assignments and Descriptions
Figure 5.
Signal Assignment (Top View) 48-Pin TSOP
x8
x8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
2
NC
3
NC
4
DNU
NC
NC
1 ●
NC
NC
5
I/O7
I/O6
I/O5
I/O4
NC
NC
DNU or Vss
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
DNU
DNU
R/B2#1
6
R/B#
7
RE#
8
CE#
9
CE2#1
10
NC
11
Vcc
12
Vss
13
NC
14
NC
15
CLE
16
ALE
17
WE#
18
WP#
19
NC
20
NC
21
NC
22
NC
23
NC
24
Note:
1.
CE2# and R/B2# are available on 8Gb and 16Gb devices only. These pins are NC for other
configurations.
Table 4.
Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Description
Address latch enable: During the time ALE is HIGH, address information is
transferred from I/O[7:0] into the on-chip address register on the rising
ALE
Input
edge of WE#
.
When address information is not being loaded, ALE should
be driven LOW.
Chip enable: Gates transfers between the host system and the NAND Flash
device. After the device starts a PROGRAM or ERASE operation, CE# can
be de-asserted. For the 8Gb configuration, CE# controls the first 4Gb of
memory; CE2# controls the second 4Gb of memory. For the 16Gb
configuration, CE# controls the first 8Gb of memory; CE2# controls the
second 8Gb. See the Bus Operation section, starting on page 14, for
additional operational details.
CE#, CE2#
Input
Input
Command latch enable: When CLE is HIGH, information is transferred from
I/O[7:0] to the on-chip command register on the rising edge of WE#.
When command information is not being loaded, CLE should be driven
LOW.
CLE
Read enable: Gates transfers from the NAND Flash device to the host
system.
RE#
Input
Input
Write enable: Gates transfers from the host system to the NAND Flash
device.
WE#
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
11
Intel® SD74 NAND Flash Memory
Table 4.
Signal Descriptions (Sheet 2 of 2)
Symbol
Type
Description
Write protect: Protects against inadvertent PROGRAM and ERASE
operations. All PROGRAM and ERASE operations are disabled when WP# is
LOW.
WP#
Input
Data inputs/outputs: The bidirectional I/Os transfer address, data, and
instruction information. Data is output only during READ operations; at
other times the I/Os are inputs.
I/O[7:0]
I/O
Ready/busy: An open-drain, active-LOW output, that uses an external
pull-up resistor. R/B# is used to indicate when the chip is processing a
PROGRAM or ERASE operation. It is also used during READ operations to
indicate when data is being transferred from the array into the serial data
register. When these operations have completed, R/B# returns to the
high-Z state. In the 8Gb and 16Gb configurations, R/B# is for the memory
enabled by CE#; R/B2# is for the memory enabled by CE2#.
R/B#, R/B2#
Output
VCC
VSS
Supply
Supply
VCC: Power supply.
VSS: Ground connection.
No connect: NCs are not internally connected. They can be driven or left
unconnected.
NC
–
–
DNU
Do not use: DNUs must be left unconnected.
§ §
Intel® SD74 NAND Flash Memory
Datasheet
12
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
4.0
Package Information
Figure 6.
48-pin TSOP
0.25
Mold compound:
Epoxy novolac
Plated lead finish:
100% Sn
for reference only
20.00 ±0.25
18.40 ±0.08
0.50 TYP
for reference
only
48
1
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
12.00 ±0.08
0.27 MAX
0.17 MIN
24
25
0.25
0.10
Gage
plane
+0.03
0.15
See detail A
-0.02
+0.10
0.10
1.20 MAX
-0.05
0.50 ±0.1
0.80
Detail A
Note:
1.
All dimensions are in millimeters.
§ §
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
13
Intel® SD74 NAND Flash Memory
5.0
NAND Flash Bus Operations
The bus on the Intel® SD74 NAND Flash Memory devices is multiplexed. Data I/O,
addresses, and commands all share the same pins, I/O[7:0].
The command sequence normally consists of a COMMAND LATCH cycle, ADDRESS
INPUT cycles, and one or more DATA cycles—either READ or WRITE.
5.1
Control Signals
CE#, WE#, RE#, CLE, ALE and WP# control the NAND Flash device READ and WRITE
operations. On the 16Gb device, CE# and CE2# each control independent 8Gb arrays.
On the 8Gb device, CE# and CE2# each control independent 4Gb arrays. CE2#
functions the same as CE# for its own array; all operations described for CE# also
apply to CE2#.
CE# is used to enable the device. When CE# is LOW and the device is not in the busy
state, the NAND Flash memory will accept command, address, and data information.
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power
consumption. See Figure 62, “READ Operation with CE# “Don’t Care”” on page 62 and
Figure 70, “Program Operation with CE# “Don’t Care”” on page 65 for examples of CE#
“Don’t Care” operations.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same
asynchronous memory bus as other Flash or SRAM devices. Other devices on the
memory bus can then be accessed while the NAND Flash is busy with internal
operations. This capability is important for designs that require multiple NAND Flash
devices on the same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
5.2
Commands
Commands are written to the command register on the rising edge of WE# when:
• CE# and ALE are LOW, and
• CLE is HIGH, and
• The device is not busy
As exceptions, the device accepts the TWO-PLANE/MULTIPLE-DIE READ STATUS, and
RESET commands when busy. Commands are transferred to the command register on
the rising edge of WE# (see Figure 60, “TWO-PLANE/MULTIPLE-DIE READ STATUS
Operation” on page 61). Commands are input on I/O[7:0].
5.3
Address Input
Addresses are written to the address register on the rising edge of WE# when:
• CE# and CLE are LOW, and
• ALE is HIGH
Addresses are input on I/O[7:0]. Bits not part of the address space must be LOW.
Intel® SD74 NAND Flash Memory
Datasheet
14
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
The number of ADDRESS cycles required for each command varies. Refer to the
command descriptions to determine addressing requirements (see Table 15,
“Command Set” on page 24).
5.4
5.5
Data Input
Data is written to the data register on the rising edge of WE# when:
• CE#, CLE, and ALE are LOW, and
• the device is not busy.
Data is input on I/O[7:0]. See Figure 56, “INPUT DATA LATCH Cycle” on page 59 for
additional data input details.
READs
After a READ command is issued, data is transferred from the memory array to the
data register on the rising edge of WE#. R/B# goes LOW for tR and transitions HIGH
after the transfer is complete. When data is available in the data register, it is clocked
out of the part by RE# going LOW. See Figure 61, “PAGE READ Operation” on page 61
for detailed timing information.
The READ STATUS (70h) command, TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command, or the R/B# signal can be used to determine when the device is ready.
If a controller is using a timing of 30ns or longer for tRC, use Figure 57, “SERIAL
ACCESS Cycle After READ” on page 59 for proper timing. If tRC is less than 30ns, use
Figure 58, “SERIAL ACCESS Cycle After READ (EDO Mode)” on page 60 for extended
data output (EDO) timing.
5.6
Ready/Busy#
The R/B# output provides a hardware method of indicating the completion of
PROGRAM, ERASE, and READ operations. The signal requires a pull-up resistor for
proper operation. The signal is typically HIGH, and transitions to LOW after the
appropriate command is written to the device. The signal pin’s open-drain driver
enables multiple R/B# outputs to be OR-tied. The READ STATUS command can be used
in place of R/B#. Typically, R/B# is connected to an interrupt pin on the system
controller (see Figure 9 on page 16).
On the 8Gb JS29F08G08CANB2, R/B# provides a status indication for the 4Gb section
enabled by CE#, and R/B2# does the same for the 4Gb section enabled by CE2#. R/B#
and R/B2# can be tied together, or they can be used separately to provide independent
indications for each 4Gb section.
On the 16Gb JS29F16G08FANB1, R/B# provides a status indication for the 8Gb section
enabled by CE#, and R/B2# does the same for the 8Gb section enabled by CE2#. R/B#
and R/B2# can be tied together, or they can be used separately to provide independent
indications for each 8Gb section. On the 16Gb JS29F16G08FANB1, R/B# and R/B2#
can be tied together, or they can be used separately to provide independent indications
for each 4Gb and 8Gb section, respectively.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# pin. The actual value used for Rp depends on the system timing
requirements. Large values of Rp cause R/B# to be delayed significantly. At the 10- to
90-percent points on the R/B# waveform, rise time is approximately two time
constants (TC).
Intel® SD74 NAND Flash Memory
Datasheet
March 2007
Order Number: 312774-012US
15
Intel® SD74 NAND Flash Memory
Figure 7.
Time Constants
TC = R × C
Where R = Rp and C = total capacitive load
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# pin and the total load capacitance.
Refer to Figure 11 on page 17, and Figure 12 on page 18, which depict approximate Rp
values using a circuit load of 100pF.
The minimum value for Rp is determined by the output drive capability of the R/B#
signal, the output voltage swing, and VCC.
Figure 8.
Minimum Rp
VCC (MAX) - VOL (MAX)
3.2V
Rp (MIN, 3.3V part) =
=
IOL + ΣIL
8mA + ΣIL
Where ΣIL is the sum of the input currents
of all devices tied to the R/B# pin.
Figure 9.
READY/BUSY# Open Drain
Rp
VCC
R/B#
Open drain outp
IOL
GND
Device
Intel® SD74 NAND Flash Memory
Datasheet
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March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Figure 10.
tRise and tFall
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
t
t
Fall Rise
V
–1
0
2
4
0
2
4
6
TC
Vcc 3.3
Notes:
1.
2.
3.
4.
tRise and tFall calculated at 10 percent–90 percent points.
tRise primarily dependent on external pull-up resistor and external capacitive loading.
tFall ª 10ns at 3.3V.
See TC values in Figure 12, “TC vs. Rp” on page 18 for approximate Rp value and TC.
Figure 11.
tIol vs. Rp
3.50ma
3.00ma
2.50ma
2.00ma
I
1.50ma
1.00ma
0.50ma
0.00ma
0
2,000
4,000
6,000
Rp
8,000
10,000
12,000
IOL at 3.60V (MAX)
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
17
Intel® SD74 NAND Flash Memory
Figure 12.
TC vs. Rp
1.20µs
1.00µs
800ns
600ns
400ns
200ns
0ns
T
0
2kΩ
4kΩ
6kΩ
Rp
8kΩ
10kΩ
12kΩ
IOL at 3.60V (MAX)
RC = TC
C = 100pF
Table 5.
Mode Selection
CLE
ALE
CE#
WE#
RE#
WP#1
Mode
Command input
H
L
L
H
H
H
H
H
X
Read mode
L
H
L
H
L
L
L
X
Address input
Command input
Address input
H
Write mode
Data input
H
L
L
H
L
L
H
L
L
L
H
H
X
X
X
X
X
Sequential read and data output
During read (busy)
During program (busy)
During erase (busy)
Write protect
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
X
X
X
X
H
H
L
0V/Vcc1
Standby
Notes:
1.
2.
WP# should be biased to CMOS HIGH or LOW for standby.
Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW;
X = VIH or VIL.
§ §
Intel® SD74 NAND Flash Memory
Datasheet
18
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
6.0
Electrical Characteristics
Table 6.
Absolute Maximum Ratings by Device
Parameter/Condition
Symbol
Min
Max
Unit
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
Voltage input
VIN
–0.6
+4.6
V
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
VCC supply voltage
VCC
–0.6
+4.6
V
Storage temperature
TSTG
–65
–
+150
5
°C
Short circuit output current, I/Os
mA
Note: Voltage on any pin relative to VSS.
Caution:
Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not guaranteed. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Table 7.
Recommended Operating Conditions
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Operating temperature
VCC supply voltage
Commercial
TA
-25
–
+85
oC
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
Vcc
Vss
2.7
0
3.3
0
3.6
0
V
V
Ground supply voltage
6.1
VCC Power Cycling
Intel® NAND Flash devices are designed to prevent data corruption during power
transitions. VCC is internally monitored. When VCC goes below approximately 2.0V,
PROGRAM and ERASE functions are disabled. WP# provides additional hardware
protection. WP# should be kept at VIL during power cycling. When VCC reaches 2.5V,
10 ms should be allowed for the NAND Flash to initialize before executing any
commands (see Figure 13 on page 20).
The RESET command must be issued to all CE#s after power-on. The device will be
busy for a maximum of 1ms.
Intel® SD74 NAND Flash Memory
Datasheet
March 2007
Order Number: 312774-012US
19
Intel® SD74 NAND Flash Memory
Figure 13.
AC Waveforms During Power Transitions
3V device: ≈ 2.5V
3V device: ≈ 2.5V
CLE
VCC
HIGH
10µs
WP#
WE#
FFh
IOx
RESET
1ms
(MAX)
R/B#
Don’t Care
Undefined
Table 8.
3V Device DC and Operating Characteristics (Sheet 1 of 2)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
Notes
tRC = 25ns, CE# = VIL,
IOUT = 0mA
Sequential read current
ICC1
—
25
35
mA
—
Program current
Erase current
–
–
ICC2
ICC3
—
—
25
25
35
35
mA
mA
—
—
—
—
CE# = VIH,
WP# = 0V/VCC
Standby current (TTL)
ISB1
—
—
1
mA
Standby current (CMOS)
—
—
—
10
20
40
50
µA
µA
µA
—
—
—
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
CE# = VCC – 0.2V,
WP# = 0V/VCC
ISB2
100
200
Input leakage current
—
—
—
—
—
—
±10
±20
±40
µA
µA
µA
—
—
—
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
VIN = 0V to VCC
ILI
Output leakage current
—
—
—
—
—
—
±10
±20
±40
µA
µA
µA
—
—
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
VOUT = 0V to VCC
ILO
Intel® SD74 NAND Flash Memory
Datasheet
20
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Table 8.
3V Device DC and Operating Characteristics (Sheet 2 of 2)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
Notes
I/O[7:0],
CE#, CLE, ALE, WE#, RE#,
WP#, R/B#
0.8 x
Vcc
VCC +
0.3
Input high voltage
VIH
–
V
—
0.2 x
Vcc
Input low voltage (all inputs)
–
VIL
–0.3
—
V
—
Output high voltage
Output low voltage
IOH = –400µA
IOL = 2.1mA
VOL = 0.4V
VOH
VOL
2.4
—
8
–
–
V
V
—
—
—
—
10
0.4
—
Output low current (R/B#)
IOL (R/B#)
mA
Table 9.
Valid Blocks
Parameter
Symbol
Device
Min
Max
Unit
Notes
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
4,016
8,032
4,096
8,192
1, 2
Number of valid blocks
NVB
Blocks
1, 2, 3
1, 2, 4
16,064
16,384
Notes:
1.
Invalid blocks are blocks that contain one or more bad bits. The device may contain bad blocks upon shipment.
Additional bad blocks may develop over time; however, the total number of available blocks will not drop below Nvb
during the endurance life of the device. Do not erase or program blocks marked invalid by the factory.
Block 00h (the first block) is guaranteed to be valid and does not require error correction up to 1,000 PROGRAM/ERASE
cycles.
2.
3.
4.
Each die will have a maximum of 80 invalid blocks.
Two die associated with each CE# will have a maximum of 160 invalid blocks. Each device has two CE# signals.
Table 10.
Capacitance
Description
Symbol
Device
Max
Unit
Notes
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
10
20
40
10
20
40
Input capacitance
CIN
pF
1, 2
Input/output capacitance (I/O)
CIO
pF
1, 2
Notes:
1.
2.
These parameters are verified in device characterization and are not 100 percent tested.
Test conditions: Tc = 25°C; f = 1 MHz; VIN = 0V.
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
21
Intel® SD74 NAND Flash Memory
Table 11.
Test Conditions
Parameter
Value
Notes
Input pulse levels
0.0V to VCC
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
Input rise and fall times
5ns
VCC/2
Input and output timing levels
Output load
1 TTL GATE and CL = 50pF
1
Note:
1.
Verified in device characterization; not 100 percent tested.
Table 12.
AC Characteristics: Command, Data, and Address Input
Cache Mode
Standard Mode
Parameter
Symbol
Unit
Notes
Min
Max
Min
Max
ALE to data start
ALE hold time
tADL
tALH
tALS
tCH
70
10
25
10
10
25
35
10
20
45
15
25
30
–
–
–
–
–
–
–
–
–
–
–
–
–
70
5
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
ALE setup time
CE# hold time
10
5
CLE hold time
tCLH
tCLS
tCS
5
CLE setup time
CE# setup time
Data hold time
Data setup time
WRITE cycle time
WE# pulse width HIGH
WE# pulse width
WP# setup time
10
15
5
tDH
tDS
10
25
10
12
30
tWC
tWH
tWP
tWW
1.
Timing for tADL begins in the ADDRESS cycle on the final rising edge of WE# and ends with the first rising edge of WE#
for data input.
Table 13.
AC Characteristics: Normal Operation (Sheet 1 of 2)
Cache Mode
Standard Mode
Parameter
Symbol
Unit
Notes
Min
Max
Min
Max
ALE to RE# delay
tAR
10
–
–
45
45
–
10
–
–
25
30
–
ns
ns
ns
ns
ns
—
1
CE# access time
tCEA
tCHZ
tCLR
tCOH
CE# HIGH to output High-Z
CLE to RE# delay
–
–
2
10
15
10
15
—
—
CE# HIGH to output hold
–
–
Cache busy in page read cache
mode (first 31h)
tDCBSYR1
–
3
–
–
µs
—
Intel® SD74 NAND Flash Memory
Datasheet
22
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Table 13.
AC Characteristics: Normal Operation (Sheet 2 of 2)
Cache Mode
Standard Mode
Parameter
Symbol
Unit
Notes
Min
Max
Min
Max
Cache busy in page read cache
mode (next 31h and 3Fh)
tDCBSYR2
tDCBSYR1
25
–
–
0
–
–
–
µs
ns
µs
—
1
Output High-Z to RE# LOW
tIR
tR
0
–
Data transfer from Flash array
to data register
25
25
—
READ cycle time
tRC
tREA
tREH
tRHOH
tRHW
tRHZ
tRLOH
tRP
50
–
–
30
–
25
–
–
20
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
RE# access time
RE# HIGH hold time
RE# HIGH to output hold
RE# HIGH to WE# LOW
RE# HIGH to output High-Z
RE# LOW to output hold
RE# pulse width
15
22
100
–
10
22
100
–
–
–
–
–
—
2
100
–
100
–
5
5
25
20
–
12
20
–
1
Ready to RE# LOW
tRR
–
–
—
Reset time (READ/PROGRAM/
ERASE/
tRST
–
5/10/500
–
5/10/500
µs
3
Power-On)
WE# HIGH to busy
WE# HIGH to RE# LOW
Notes:
tWB
–
100
–
–
100
–
ns
ns
4
tWHR
60
60
—
1.
2.
3.
4.
For PAGE READ CACHE MODE and PROGRAM PAGE CACHE MODE operations, the Cache Mode cache mode timing
applies.
Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100 percent
tested.
The first time the RESET (FFh) command is issued while the device is idle, the device will go busy for a maximum of
1ms. Thereafter, the device goes busy for maximum 5µs.
Do not issue a new command during tWB, even if R/B# is ready.
Table 14.
PROGRAM/ERASE Characteristics
Parameter
Symbol
Typ
Max
Unit
Notes
Number of partial page programs
NOP
tBERS
tCBSY
tDBSY
tLPROG
—
1.5
3
4
2
Cycles
ms
µs
4
BLOCK ERASE operation time
Busy time for PROGRAM CACHE operation
Busy time for TWO-PLANE PROGRAM PAGE operation
LAST PAGE PROGRAM operation time
500
1
1
—
2
0.5
—
µs
—
–
Busy time for OTP DATA PROGRAM operation if OTP is
protected
tOBSY
tPROG
—
25
µs
µs
—
3
PAGE PROGRAM operation time
220
500
Notes:
1.
2.
tCBSY MAX time depends on timing between internal program completion and data-in.
tLPROG = tPROG (last page) + tPROG (last – 1 page) – cmd load time (last page) – addr load time (last page) – data
load time (last page).
3.
4.
Typical tPROG time may increase for two-plane operations.
Four total partial page programs to the same page.
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
23
Intel® SD74 NAND Flash Memory
7.0
Command Definitions
7.1
Command Definitions
Table 15.
Command Set
Number
Valid
During
Busy
Command
Cycle #1
of
Data Cycles
Required1
Command
Cycle #2
Command
Notes
Address
Cycles
PAGE READ
00h
31h
3Fh
00h
05h
90h
70h
80h
80h
85h
85h
60h
FFh
A0h
A5h
AFh
5
–
–
5
2
1
–
5
5
5
2
3
–
5
5
5
No
No
30h
–
No
No
No
No
No
No
Yes
No
No
No
No
No
Yes
No
No
No
5
2
2
3
4
PAGE READ CACHE MODE
PAGE READ CACHE MODE LAST
READ for INTERNAL DATA MOVE
RANDOM DATA READ
READ ID
No
–
No
35h
E0h
–
No
No
READ STATUS
No
–
PROGRAM PAGE
Yes
Yes
Optional
Yes
No
10h
15h
10h
–
5
PROGRAM PAGE CACHE MODE
PROGRAM for INTERNAL DATA MOVE
RANDOM DATA INPUT
BLOCK ERASE
3
6
5
D0h
–
RESET
No
OTP DATA PROGRAM
OTP DATA PROTECT
OTP DATA READ
Yes
No
10h
10h
30h
No
Notes:
1.
2.
3.
Indicates required data cycles between command cycle 1 and command cycle 2.
Do not cross block address boundaries when using PAGE READ CACHE MODE operations.
Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and PROGRAM for INTERNAL DATA
MOVE. See Table 2 and 3 on page 9 for plane address boundary definitions.
RANDOM DATA READ command limited to use within a single page.
These commands are valid during busy when performing an interleaved die operation. See Section 7.7, “Two-Plane
Operations” on page 38 for additional details.
4.
5.
6.
RANDOM DATA INPUT command limited to use within a single page.
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Table 16.
Two-Plane Command Set
Number
of
Address
Cycles
Number of
Address
Cycles
Valid
During
Busy
Command
Cycle 1
Command
Cycle 2
Command
Cycle 3
Command
Notes
TWO-PLANE PAGE READ
00h
00h
5
5
00h
00h
5
5
30h
35h
No
No
TWO-PLANE READ for
INTERNAL DATA MOVE
1
2
3
4
4
TWO-PLANE RANDOM DATA
READ
06h
78h
80h
80h
5
3
5
5
E0h
–
–
–
5
5
–
No
Yes
No
No
TWO-PLANE/MULTIPLE-DIE
READ STATUS
–
TWO-PLANE PROGRAM
PAGE
11h-80h or
11h-81h
10h
15h
TWO-PLANE PROGRAM
PAGE CACHE MODE
11h-80h or
11h-81h
TWO-PLANE PROGRAM for
INTERNAL DATA MOVE
11h-80h or
11h-81h
85h
60h
5
3
5
3
10h
D0h
No
No
1
4
TWO-PLANE BLOCK ERASE
60h
Notes:
1.
Do not cross plane address boundaries when using TWO-PLANE READ for INTERNAL DATA MOVE and TWO-PLANE
PROGRAM for INTERNAL DATA MOVE. See Table 2 on page 9, and Table 3 on page 10 for plane address boundary
definitions.
2.
3.
TWO-PLANE/MULTIPLE-DIE RANDOM DATA READ command is limited to use within a single page.
The TWO-PLANE/MULTIPLE-DIE READ STATUS command can be used to check status with two-plane and multiple-die
operations, excluding the TWO-PLANE PAGE READ (00h-00h- 30h) command.
These commands are valid during busy when performing interleaved die operations. See “Interleaved Die Operations”
on page 48 for additional details.
4.
7.2
READ Operations
7.2.1
PAGE READ 00h–30h
On initial power up, each device defaults to read mode. To enter the read mode while in
operation, write the 00h command to the command register then write five ADDRESS
cycles, then conclude with the 30h command.
To determine the progress of the data transfer from the NAND Flash array to the data
register (tR), monitor the R/B# signal; or alternately, issue a READ STATUS (70h)
command. If the READ STATUS command is used to monitor the data transfer, the user
must re-issue the READ (00h) command to receive data output from the data register.
See Figure 64, “PAGE READ CACHE MODE Operation, Part 1 of 2” on page 63 and
Figure 65, “PAGE READ CACHE MODE Operation, Part 2 of 2” on page 63 for examples.
After the READ command has been re-issued, pulsing the RE# line will result in
outputting data, starting from the initial column address.
A serial page read sequence outputs a complete page of data. After 30h is written, the
page data is transferred to the data register, and R/B# goes LOW during the transfer.
When the transfer to the data register is complete, R/B# returns HIGH. At this point,
data can be read from the device. Starting from the initial column address to the end of
the page, read the data by repeatedly pulsing RE# at the maximum tRC rate (see
Figure 14).
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Intel® SD74 NAND Flash Memory
Figure 14.
PAGE READ Operation
CLE
CE#
WE#
ALE
t
R
R/B#
RE#
00h
30h
I/Ox
Address (5 cycles)
Data output (serial access)
Don’t Care
7.2.2
RANDOM DATA READ 05h–E0h
The RANDOM DATA READ command enables the user to specify a new column address
so the data at single or multiple addresses can be read. The random read mode is
enabled after a normal PAGE READ (00h-30h) sequence.
Random data can be output after the initial page read by writing an 05h-E0h command
sequence along with the new column address (two cycles).
The RANDOM DATA READ command can be issued without limit within the page.
Only data on the current page can be read. Pulsing the RE# pin outputs data
sequentially (see Figure 15 on page 26).
Figure 15.
Random Data Read Operation
t
R
R/B#
RE#
Address
(5 cycles)
Address
(2 cycles)
Data output
I/Ox
00h
30h
Data output
05h
E0h
7.2.3
PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE
START LAST 3Fh
Intel® NAND Flash devices have a cache register that can be used to increase READ
operation speed when accessing sequential pages in a block.
First, issue a normal PAGE READ (00h–30h) command sequence. See Figure 16 on
page 27 for operation details. The R/B# signal goes LOW for tR during the time it takes
to transfer the first page of data from the memory to the data register. After R/B#
returns to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into
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the command register. R/B# goes LOW for tDCBSYR1 while data is being transferred
from the data register to the cache register. After the data register contents are
transferred to the cache register, another PAGE READ is automatically started as part of
the 31h command. Data is transferred from the next sequential page of the memory
array to the data register during the same time data is being read serially (pulsing
RE#) from the cache register. If the total time to output data exceeds tR, then the
PAGE READ is hidden.
The second and subsequent pages of data are transferred to the cache register by
issuing additional 31h commands. R/B# will stay LOW up to tDCBSYR2. This time can
vary, depending on whether the previous memory-to-data-register transfer was
completed prior to issuing the next 31h command. See Table 13 on page 22 for timing
parameters. If the data transfer from memory to the data register is not completed
before the 31h command is issued, R/B# stays LOW until the transfer is complete.
It is not necessary to output a whole page of data before issuing another 31h
command. R/B# will stay LOW until the previous PAGE READ is complete and the data
has been transferred to the cache register.
To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh)
command is issued. This command transfers data from the data register to the cache
register without issuing another PAGE READ (see Figure 16 on page 27).
Figure 16.
PAGE READ CACHE MODE
CLE
CE#
WE#
ALE
t
t
t
t
DCBSYR2
R
DCBSYR1
DCBSYR2
R/B#
RE#
I/Ox
00h
Address (5 cycles)
30h
31h
Data output (serial access)
31h
Data output (serial access)
3Fh
Data output (serial access)
Don’t Care
7.2.4
READ ID 90h
The READ ID command is used to read the 5 bytes of identifier code programmed into
the Intel® SD74 NAND Flash Memory devices. The READ ID command reads a 5-byte
table that includes manufacturer ID, device configuration, and part-specific Table 17,
“Device ID and Configuration Codes” on page 29).
Writing 90h to the command register puts the device into the read ID mode. The
command register stays in this mode until another valid command is issued (see
Figure 17).
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Figure 17.
READ ID Operation
CLE
CE#
WE#
t
AR
ALE
RE#
t
t
REA
Byte 0
WHR
I/Ox
90h
00h
Byte 1
Byte 2
Byte 3
Byte 4
Address, 1 cycle
Note: See Table 17 on page 29 for byte definitions.
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Table 17.
Device ID and Configuration Codes
I/O I/O I/O I/O I/O I/O I/O I/O
Options
Value1 Notes
7
6
5
4
3
2
1
0
Byte 0
Manufacturer ID
Intel
0
0
1
0
1
1
0
0
2Ch
DCh
Byte 1
Device ID
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
Byte 2
4Gb, x8, 3V
8Gb, x8, 3V
16Gb, x8, 3V
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
0
1
DCh
D3h
2
1
2
0
0
0
1
00b
01b
00b
Number of die per
CE
Cell type
SLC
0
0
Number of
simultaneously
2
0
1
01b
programmed pages
Interleaved
operationsbetween
multiple die
Not supported
Supported
0
1
0b
1b
Cache
programming
Supported
1
1b
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
90h
90h
Byte value
2
1
1
0
1
0
0
0
1
D1h
Byte 3
Page size
2KB
64B
0
1
01b
1b
Spare area size
(bytes)
1
Block size (w/o
spare)
128KB
0
0
1
1
01b
Organization
Serial access (MIN)
Byte value
x8
25ns
0
0
0b
1xxx0b
95h
1
1
0
0
8-bit bus width
1
0
0
1
0
Byte 4
Reserved
00b
01b
10b
101b
0b
2
4
0
1
1
0
Planes per CE#
Plane size
Reserved
2Gb
1
0
1
0
0
JS29F04G08AANB1
JS29F08G08CANB2
JS29F16G08FANB1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
54h
0
0
54h
58h
2
2
Byte value
1
0
1
1
0
0
0
Notes:
1.
2.
b = binary; h = hex.
The JS29F08G08CANB2 device ID code reflects the configuration of each 4Gb section.
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Intel® SD74 NAND Flash Memory
7.2.5
READ STATUS 70h
These NAND Flash devices have an 8-bit status register that the software can read
during device operation. Table 18 describes the status register.
After a READ STATUS command, all READ cycles will be from the status register until a
new command is issued. Changes in the status register will be seen on I/O[7:0] as
long as CE# and RE# are LOW; it is not necessary to start a new READ STATUS cycle to
see these changes.
In devices that have more than one die sharing a common CE# pin, the READ STATUS
(70h) command reports the status of the die that was last addressed. If interleaved
operations are started on both die, then the TWO-PLANE/MULTIPLE-DIE READ STATUS
(78h) command must be used to select the die that should report status. In this
situation, using the READ STATUS (70h) command will result in bus contention, as both
die will respond until the next operation is issued.
While monitoring the status register to determine when the tR (transfer from NAND
Flash array to data register) is complete, the user must re-issue the READ (00h)
command to make the change from status to read mode. After the READ command has
been re-issued, pulsing the RE# line will result in outputting data, starting from the
initial column address.
Table 18.
Status Register Bit Definition
Program
PageRead
Cache
Mode
SR
Bit
Program
Page
Page
Cache
Mode
Block
Erase
Page Read
Definition
“0” = Successful PROGRAM/
ERASE
“1” = Error in PROGRAM/ERASE
Pass/fail
(N)
01
1
Pass/fail
–
–
–
–
–
Pass/fail
–
“0” = Successful PROGRAM
“1” = Error in PROGRAM
Pass/fail
(N-1)
2
3
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
“0”
“0”
“0”
“0” = Busy
“1” = Ready
Ready/
busy2
Ready/
busy2
5
6
7
Ready/busy
Ready/busy
Ready/busy
Ready/busy
Ready/busy
Ready/busy
“0” = Busy
“1” = Ready
Ready/busy
cache3
Ready/busy
cache3
“0” = Protected
“1” = Not protected
Write
protect
Write
protect
Write
protect
Write
protect
Write
protect
Notes:
1.
Status register bit 0 reports a “1” if a TWO-PLANE PROGRAM operation fails on one or both planes.
Status register bit 1 reports a “1” if a TWO-PLANE PROGRAM PAGE CACHE MODE operation fails on
one or both planes. Use TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) to determine the plane to
which the operation failed
2.
3.
Status register bit 5 is “0” during the actual programming operation. If cache mode is used, this bit
will be “1” when all internal operations are complete.
Status register bit 6 is “1” when the cache is ready to accept new data. R/B# follows bit 6. See
Figure 21, “PROGRAM PAGE CACHE MODE Example” on page 33 and Figure 74, “PROGRAM PAGE
CACHE MODE Operation Ending on 15h” on page 67.
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Figure 18.
Status Register Operation
CE#
CLE
WE#
RE#
t
CLR
t
REA
70h
Status output
I/Ox
7.3
PROGRAM Operations
PROGRAM PAGE 80h–10h
7.3.1
Intel® NAND Flash devices are inherently page-programmed devices. Pages must be
programmed consecutively within a block, from the least significant page address to
most significant page address (i.e., 0, 1, 2, …, 63). Random page address programming
is prohibited.
Intel® NAND Flash devices also support partial-page programming operations. This
means that any single bit can be programmed only one time before an erase is
required; however, the page can be partitioned such that a maximum of four
programming operations are supported before an erase is required.
7.3.2
SERIAL DATA INPUT 80h
PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command
into the command register, followed by five ADDRESS cycles, then the data. Serial data
is loaded on consecutive WE# cycles starting at the given address. The PROGRAM
(10h) command is written after the data input is complete. The control logic
automatically executes the proper algorithm and controls all the necessary timing to
program and verify the operation. Write verification only detects “1s” that are not
successfully written to “0s.”
R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS
(70h) command and the RESET (FFh) command are the only commands valid during the
programming operation. Bit 6 of the status register will reflect the state of R/B#. When
the device reaches ready, read bit 0 of the status register to determine if the program
operation passed or failed (see Figure 19). The command register stays in read status
register mode until another valid command is written to it.
7.3.3
RANDOM DATA INPUT 85h
After the initial data set is input, additional data can be written to a new column
address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT
command can be used any number of times in the same page prior to issuing the PAGE
WRITE (10h) command. See Figure 20 for the proper command sequence.
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Figure 19.
PROGRAM and READ STATUS Operation
t
PROG
R/B#
80h
Address (5 cycles)
DIN
10h
70h
Status
I/Ox
I/O 0 = 0 PROGRAM successful
I/O 0 = 1 PROGRAM error
Figure 20.
RANDOM DATA INPUT
t
PROG
R/B#
80h Address (5 cycles)
DIN
85h Address (2 cycles)
DIN
10h
70h
Status
I/Ox
7.3.4
PROGRAM PAGE CACHE MODE 80h–15h
Cache programming is actually a buffered programming mode of the standard
PROGRAM PAGE command. Programming is started by loading the SERIAL DATA INPUT
(80h) command to the command register, followed by five cycles of address, and a full
or partial page of data. The data is initially copied into the cache register, and the
CACHE PROGRAM (15h) command is then latched to the command register. Data is
transferred from the cache register to the data register on the rising edge of WE#. R/
B# goes LOW during this transfer time. After the data has been copied into the data
register and R/B# returns to HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing
another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be
controlled by the actual programming time. The first time through equals the time it
takes to transfer the cache register contents to the data register. On the second and
subsequent programming passes, transfer from the cache register to the data register
is held off until current data register content has been programmed into the array.
The PROGRAM PAGE CACHE MODE command can cross block address boundaries; it
must not cross die address boundaries. RANDOM DATA INPUT (85h) commands are
permitted with PROGRAM PAGE CACHE MODE operations.
Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS
(70h) command to determine when the cache register is ready to accept new data. The
R/B# pin always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual
programming of the array is complete for the current programming cycle.
If just the R/B# pin is used to determine programming completion, the last page of the
program sequence must use the PROGRAM PAGE (10h) command instead of the CACHE
PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used every
time, including the last page of the programming sequence, status register bit 5 must
be used to determine when programming is complete (see Figure 21).
Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the
status register is a “1” (ready state). The pass/fail status of the current PROGRAM
operation is returned with bit 0 of the status register when bit 5 of the status register is
a “1” (ready state) (as shown in Figure 21.)
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Figure 21.
PROGRAM PAGE CACHE MODE Example
t
t
t
t
1
LPROG
CBSY
CBSY
CBSY
R/B#
I/Ox
Address &
data input
Address &
data input
Address &
data input
Address &
data input
80h
15h
80h
15h
80h
15h
80h
10h
A: Without status reads
t
t
1
LPROG
CBSY
70h
R/B#
I/Ox
Address &
data input
Status
output2
Address &
data input
Status
output2
80h
15h
80h
10h
70h
B: With status reads
See Note 3, Table 14, “PROGRAM/ERASE Characteristics” on page 23.
Check I/O[6:5] for internal Ready/Busy. Check I/O[1:0] for pass/fail status. RE# can stay LOW or pulse
multiple times after a 70h command.
Notes:
1.
2.
7.4
Internal Data Move
An internal data move requires two command sequences. Issue a READ for INTERNAL
DATA MOVE (00h-35h) command first, then the PROGRAM for INTERNAL DATA MOVE
(85h-10h) command. Data moves are only supported within the plane from which data
is read. Moving data from odd to even blocks, from even to odd blocks, and across die
boundaries is prohibited.
7.4.1
READ FOR INTERNAL DATA MOVE 00h–35h
The READ for INTERNAL DATA MOVE (00h-35h) command is used in conjunction with
the PROGRAM for INTERNAL DATA MOVE (85h-10h) command. First, 00h is written to
the command register, then the internal source address is written (five cycles). After
the address is input, the READ for INTERNAL DATA MOVE (35h) command writes to the
command register. This transfers a page from memory into the cache register.
The written column addresses are ignored even though all five ADDRESS cycles are
required.
The memory device is now ready to accept the PROGRAM for INTERNAL DATA MOVE
command. Please refer to the description of this command in the following section.
7.4.2
PROGRAM for INTERNAL DATA MOVE 85h–10h
After the READ for INTERNAL DATA MOVE (00h-35h) command has been issued and R/
B# goes HIGH, the PROGRAM for INTERNAL DATA MOVE (85h-10h) command can be
written to the command register. This command transfers the data from the cache register
to the data register and programming of the new destination page begins. The
sequence: 85h, destination address (five cycles), then 10h, is written to the device.
After 10h is written, R/B# goes LOW while the control logic automatically programs the
new page. The READ STATUS command can be used instead of the R/B# line to
determine when the write is complete. Status register bit 6 = “1,” bit 0 of the status
register indicates if the operation was successful.
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The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for
INTERNAL DATA MOVE command sequence to modify one or more bytes of the original
data. First, data is copied into the cache register using the 00h-35h command
sequence, then the RANDOM DATA INPUT (85h) command is written along with the
address of the data to be modified next. New data is input on the external data pins.
This copies the new data into the cache register.
When 10h is written to the command register, the original data plus the modified data
are transferred to the data register, and programming of the new page is started. The
RANDOM DATA INPUT command can be issued as many times as necessary before
starting the programming sequence with 10h (see Figure 22 and Figure 23 starting on
page 34).
Because INTERNAL DATA MOVE operations do not use external memory, ECC cannot be
used to check for errors before programming the data to a new page. This can lead to a
data error if the source page contains a bit error due to charge loss or charge gain. In
the case that multiple INTERNAL DATA MOVE operations are performed, these bit errors
may accumulate without correction. For this reason, it is highly recommended that
systems using INTERNAL DATA MOVE operations also use a robust ECC scheme that
can correct two or more bits per sector.
Figure 22.
Figure 23.
INTERNAL DATA MOVE
t
t
PROG
R
R/B#
I/Ox
Address
(5 cycles)
Address
(5 cycles)
00h
35h
85h
10h
70h
Status
INTERNAL DATA MOVE with RANDOM DATA INPUT
t
t
PROG
R
R/B#
Address
(5 cycles)
Address
(5 cycles)
Address
(2 cycles)
Data
I/Ox 00h
35h
85h
Data 85h
10h
70h
Status
Unlimited number
of repetitions
7.5
BLOCK ERASE Operation
7.5.1
BLOCK ERASE 60h–D0h
Erasing occurs at the block level. For example, the JS29F04G08AANB1 device has
4,096 erase blocks, organized into 64 pages per block, 2,112 bytes per page (2,048 +
64 bytes). Each block is 132K bytes (128K + 4K bytes). The BLOCK ERASE command
operates on one block at a time (see Figure 24 on page 35).
Three cycles of addresses BA[18:6] and PA[5:0]are required. Although page addresses
PA[5:0] are loaded, they are a “Don’t Care” and are ignored for BLOCK ERASE
operations. See Figure 2 on page 8 for addressing details.
The actual command sequence is a two-step process. The ERASE SETUP (60h)
command is first written to the command register. Then three cycles of addresses are
written to the device. Next, the ERASE CONFIRM (D0h) command is written to the
command register. At the rising edge of WE#, R/B# goes LOW and the control logic
automatically controls the timing and erase-verify operations. R/B# stays LOW for the
entire tBERS erase time.
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The READ STATUS (70h) command can be used to check the status of the BLOCK
ERASE operation. When bit 6 = “1” the ERASE operation is complete. Bit 0 indicates a
pass/fail condition where “0” = pass (see Figure 24 on page 35, and Table 18 on
page 30).
Figure 24.Block Erase Operation
CLE
CE#
WE#
ALE
t
BERS
R/B#
RE#
I/Ox
60h
D0h
70h
Address Input (3 cycles)
Status
I/O 0 = 0 ERASE successful
I/O 0 = 1 ERASE error
Don’t Care
7.6
One-Time Programmable (OTP) Area
This Intel® NAND Flash device offers a protected, one-time programmable NAND Flash
memory area. Ten full pages (2,112 bytes per page) of OTP data is available on the
device, and the entire range is guaranteed to be good. The OTP area is accessible only
through the OTP commands. Customers can use the OTP area in any way they desire;
typical uses include programming serial numbers or other data for permanent storage.
In Intel® NAND Flash devices, the OTP area leaves the factory in a non-written state
(all bits are “1s”). Programming or partial-page programming enables the user to
program only “0” bits in the OTP area. The OTP area cannot be erased, even if it is not
protected. Protecting the OTP area simply prevents further programming of the OTP
area.
While the OTP area is referred to as “one-time programmable,” Intel provides a unique
way to program and verify data—before permanently protecting it and preventing
future changes.
OTP programming and protection are accomplished in two discrete operations. First,
using the OTP DATA PROGRAM (A0h-10h) command, an OTP page is programmed
entirely in one operation, or in up to four partial-page programming sequences.
Programming can occur on other pages within the OTP area in a similar manner.
Second, the OTP area is permanently protected from further programming using the
OTP DATA PROTECT (A5h-10h) command. The pages within the OTP area can always be
read using the OTP DATA READ (AFh-30h) command, whether or not it is protected.
To determine whether or not the device is busy during an OTP operation, either monitor
R/B# or use the READ STATUS (70h) command. Use of the TWO-PLANE/MULTIPLE-DIE
READ STATUS (78h) command is prohibited during and following OTP operations.
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7.6.1
OTP DATA PROGRAM A0h-10h
The OTP DATA PROGRAM (A0h-10h) command is used to write data to the pages within
the OTP area. An entire page can be programmed at one time, or a page can be
partially programmed up to four times. There is no ERASE operation for the OTP pages.
The OTP DATA PROGRAM enables programming into an offset of an OTP page, using the
two bytes of column address (CA[11:0]). The command is not compatible with the
RANDOM DATA INPUT (85h) command. The OTP DATA PROGRAM command will not
execute if the OTP area has been protected.
To use the OTP DATA PROGRAM command, issue the A0h command. Issue five
ADDRESS cycles: the first two ADDRESS cycles are the column address, and for the
remaining three cycles select a page in the range of 02h-00h-00h through 0Bh-00h-
00h. Next, write from 1 to 2,112 bytes of data. After data input is complete, issue the
10h command. The internal control logic automatically executes the proper
programming algorithm and controls the necessary timing for programming and
verification. Program verification only detects “1s” that are not successfully written to
“0s.”
R/B# goes LOW during the duration of the array programming time (tPROG). The READ
STATUS (70h) command is the only command valid during the OTP DATA PROGRAM
operation. Bit 5 of the status register will reflect the state of R/B#. If bit 7 is “0,” then
the OTP area has been protected; otherwise, it will be a “1.”
When the device is ready, read bit 0 of the status register to determine if the operation
passed or failed (see Table 18 on page 30).
It is possible to program each OTP page a maximum of four times.
Figure 25.
OTP DATA PROGRAM
CLE
CE#
t
WC
WE#
t
t
PROG
WB
ALE
RE#
Col
add 1
Col
add 2
OTP
D
IN
DIN
M
I/Ox
A0h
00h
00h
10h
70h
Status
page1
N
OTP DATA INPUT
command
1 up to m bytes PROGRAM
mand
READ STATUS
command
R/B#
OTP data written
(following "good" status confirmation)
x8 device: m
= 2,112 bytes
Don’t Care
Note: The OTP page must be within the 02h–0Bh range.
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7.6.2
OTP DATA PROTECT A5h-10h
The OTP DATA PROTECT (A5h-10h) command is used to protect all the data in the OTP
area. After the data is protected it cannot be programmed further. When the OTP area
is protected, the pages within the area are no longer programmable and cannot be
unprotected.
To use the OTP DATA PROTECT command, issue the A5h command. Next, issue the
following five ADDRESS cycles: 00h-00h-01h-00h-00h. Finally, issue the 10h
command.
R/B# goes LOW while the OTP area is being protected. The protect command duration
is similar to a normal page programming operation, tPROG. The READ STATUS (70h)
command is the only command valid during the OTP DATA PROTECT operation. Bit 5 of
the status register will reflect the state of R/B#.
When the device is ready, read bit 0 of the status register to determine if the operation
passed or failed (see Table 18, “Status Register Bit Definition” on page 30).
Figure 26.
OTP DATA PROTECT
CLE
CE#
t
WC
WE#
t
t
PROG
WB
ALE
RE#
Col
00h
Col
00h
I/Ox
A5h
01h
00h
00h
10h
70h
Status
OTP DATA PROTECT
Command
PROGRAM
Command
READ STATUS
Command
R/B#
1
OTP Data Protected
Don’t Care
Note: OTP data is protected following “good” status confirmation.
7.6.3
OTP DATA READ AFh-30h
The OTP DATA READ (AFh-30h) command is used to read data from a page within the
OTP area. An OTP page within the OTP area is available for reading data whether or not
the area is protected.
To use the OTP DATA READ command, issue the AFh command. Next, issue five
ADDRESS cycles: the first two ADDRESS cycles are the column address, and for the
remaining three cycles select a page in the range of 02h-00h-00h through 0Bh-00h-
00h. Finally, issue the 30h command.
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R/B# goes LOW (tR) while the data is moved from the OTP page to the data register.
The READ STATUS (70h) command and the RESET (FFh) command are the only
commands valid during the OTP DATA READ operation. Bit 5 of the status register will
reflect the state of R/B#. For details, refer to Table 18 on page 30.
Normal READ operation timings apply to OTP read accesses (see Figure ). Additional
pages within the OTP area can be selected by repeating the OTP DATA READ command.
Figure 27.
OTP DATA READ Operation
CLE
CE#
WE#
ALE
t
R
RE#
Col
Add 1
Col
Add 2
OTP
Page1
DOUT
N
DOUT
N + 1
DOUT
M
I/Ox
R/B#
AFh
00h
00h
30h
Busy
Don’t Care
Note: The OTP page must be within the 02h–0Bh range.
7.7
Two-Plane Operations
This NAND Flash device is divided into two physical planes. Each plane contains a
2,112-byte data register, a 2,112-byte cache register, and a 2,048-block NAND Flash
array. Two-plane commands make better use of the Flash arrays on these physical
planes by performing PROGRAM, READ, or ERASE operations simultaneously,
significantly improving system performance.
7.7.1
TWO-PLANE Addressing
Two-plane commands require two addresses, one address per plane. These two
addresses are subject to the following requirements:
• The least significant block address bit, BA6, must be different for the two
addresses.
• The most significant block address bit, BA18 for 16Gb devices, must be identical for
both addresses.
• The page address bits, PA[5:0], must be identical for both addresses.
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7.7.2
TWO-PLANE PAGE READ 00h-00h-30h
The TWO-PLANE PAGE READ (00h-00h-30h) operation is similar to the PAGE READ
(00h-30h) operation. It transfers two pages of data from the NAND Flash array to the
data registers. Each page must be from a different plane on the same die.
To enter the TWO-PLANE PAGE READ mode, write the 00h command to the command
register, then write five ADDRESS cycles for plane 0 (BA6 = “0”). Next, write the 00h
command to the command register, then write five ADDRESS cycles for plane 1 (BA6 =
“1”). Finally, issue the 30h command. The first-plane and second-plane addresses must
meet the two-plane addressing requirements, and in addition, they must have identical
column addresses.
After the 30h command is written, page data is transferred from both planes to their
respective data registers in tR. During these transfers, R/B# goes LOW. When the
transfers are complete, R/B# goes HIGH. To read out the data from the plane 0 data
register, pulse RE# repeatedly. After the data cycle from the plane 0 address
completes, issue a TWO-PLANE/MULTIPLE-DIE RANDOM DATA READ (06h-E0h)
command to select the plane 1 address, then repeatedly pulse RE# to read out the data
from the plane 1 data register.
Alternately, the READ STATUS (70h) command can monitor the data transfers. When
the transfers are complete, status register bit 6 is set to “1.” To read data from the first
of the two planes, the user must first issue the TWO-PLANE RANDOM DATA READ (06h-
E0h) command and pulse RE# repeatedly. When the data cycle is complete, issue a
TWO-PLANE RANDOM DATA READ (06h-E0h) command to select the other plane. To
output the data beginning at the specified column address, pulse RE# repeatedly.
Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is prohibited
during and following a TWO-PLANE PAGE READ operation.
7.7.3
TWO-PLANE/MULTIPLE-DIE RANDOM DATA READ 06h-E0h
The TWO-PLANE RANDOM DATA READ (06h-E0h) command is similar to the RANDOM
DATA READ (05h-E0h) command, except that it requires five ADDRESS cycles rather
than two. The command selects a die and plane and a column address from which to
read data after a TWO-PLANE PAGE READ (00h-00h-30h) command, and during or
after an interleaved PAGE READ operation (see Section 7.8, “Interleaved Die
Operations” on page 48
To issue a TWO-PLANE RANDOM DATA READ command, issue the 06h command, then
five ADDRESS cycles, and follow with the E0h command. Pulse RE# repeatedly to read
data from the new plane, beginning at the specified column address.
The primary purpose of the TWO-PLANE RANDOM DATA READ command is to select a
new die and plane and a column address within that die and plane. If a new die and
plane do not need to be selected, then it is possible to use the RANDOM DATA READ
(05h-E0h) command instead (see Table 7.2.2, “RANDOM DATA READ 05h–E0h” on
page 26).
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Figure 28.
TWO-PLANE PAGE READ
CLE
WE#
ALE
RE#
Page address M
Page address M
Col
Col
Row
Row
Row
Col
Col
Row
Row
Row
00h
00h
30h
I/Ox
R/B#
add 1
add 2
add 1
add 2
add 3
add 1
add 2
add 1
add 2
add 3
t
Column address J
Plane 0 address
Column address J
Plane 1 address
R
1
CLE
WE#
ALE
RE#
Col
add 1
Col
add 2
Row
add 1
Row
Row
add 3
I/Ox
R/B#
DOUT
0
DOUT
1
DOUT
06h
E0h
DOUT
0
DOUT
1
DOUT
add 2
Plane 0 data
Plane 1 address
Plane 1 data
1
Notes:
1.
2.
Column and page addresses must be the same.
The least significant block address bit, BA6, must not be the same for the first and second plane
addresses.
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Figure 29.
TWO-PLANE PAGE READ with RANDOM DATA READ
t
R
R/B#
RE#
I/Ox
Address
(2 cycles)
00h Address (5 cycles) 00h Address (5 cycles) 30h
Data Output
Plane 0 Data
05h
E0h
Data Output
Plane 0 Data
Plane 0 Address
Plane 1 Address
1
R/B#
RE#
I/Ox
Address
(2 cycles)
06h Address (5 cycles) E0h
Plane 1 Address
Data Output
Plane 1 Data
05h
E0h
Data Output
Plane 1 Data
1
7.7.4
TWO-PLANE PROGRAM PAGE 80h-11h-80h-10h or 80h-11h-
81h-10h
The TWO-PLANE PROGRAM PAGE (80h-11h-80h-10h or 80h-11h-81h-10h) operation is
similar to the PROGRAM PAGE (80h-10h) operation. It programs two pages of data
from the data registers to the Flash arrays. The pages must be programmed to
different planes on the same die. Within a block, the pages must be programmed
consecutively from the least significant to most significant page address. Random page
programming within a block is prohibited. The first plane address and the second plane
address must meet the two-plane addressing requirements (see “TWO-PLANE
Addressing” on page 38).
To begin the TWO-PLANE PROGRAM PAGE operation, write the 80h command to the
command register; write five ADDRESS cycles for the first plane; then write the data.
Serial data is loaded on consecutive WE# cycles starting at the given address. Next,
write the 11h command. The 11h command is a “dummy” command that informs the
control logic that the first set of data for the first plane is complete. No programming of
the NAND Flash array occurs. R/B# goes LOW for tDBSY, then returns HIGH. The READ
STATUS (70h) command also indicates that the device is ready when status register bit
6 is set to “1.” The only valid commands during tDBSY are READ STATUS (70h) and
RESET (FFh).
After tDBSY, write the 80h (or 81h) command to the command register; write five
ADDRESS cycles for the second plane; then write the data. The PROGRAM (10h)
command is written after the second-plane data input is complete.
After the 10h command is written, the control logic automatically executes the proper
algorithm and controls all the necessary timing to program and verify the operations to
both planes. WRITE verification only detects “1s” that are not successfully written to
“0s.”
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R/B# goes LOW for the duration of the array programming time (tPROG). When
programming and verification are complete, R/B# returns HIGH. The READ STATUS
(70h) command also indicates that the device is ready when status register bit 6 is set
to “1.” The only valid commands during tPROG are READ STATUS (70h), TWO-PLANE/
MULTIPLE-DIE READ STATUS (78h), and RESET (FFh).
When the device is ready, if the READ STATUS (70h) command indicates an error in the
operation (status register bit 0 = “1”), use the TWO-PLANE/MULTIPLE-DIE READ
STATUS (78h) command twice—once for each plane—to determine which plane
operation failed.
During serial data input for either plane, the RANDOM DATA INPUT (85h) command can
be used any number of times to change the column address within that plane. For
details on this command, see Section 7.3.3, “RANDOM DATA INPUT 85h” on page 31.
Figure 30 shows TWO-PLANE PROGRAM PAGE operation.
Figure 30.
TWO-PLANE PROGRAM PAGE
t
t
PROG
DBSY
R/B#
I/Ox
80h
Address (5 cycles) Data input
1st plane address
11h
80h
Address (5 cycles)
2nd plane address
Data input
10h
70h
Status
(or 81h)
Figure 31.
TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT
t
DBSY
R/B#
80h Address (5 cycles)
1st Plane Address
Data Input
85h Address (2 cycles)
Data Input
11h
81h Address (5 cycles)
2nd Plane Address
Data Input
I/Ox
Different column
address than previous
5 address cycles, for
1st plane only.
1
Repeat as many times as necessary
t
PROG
R/B#
I/Ox
85h Address (2 cycles)
Data Input
10h
Different column
address than previous
5 address cycles, for
2nd plane only.
1
Repeat as many times as necessary
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7.7.5
TWO-PLANE PROGRAM PAGE CACHE MODE 80h-11h-80h-15h or
80h-11h-81h-15h
The TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h or 80h-11h-81h-
15h) operation is similar to the PROGRAM PAGE CACHE MODE (80h-15h) operation. It
programs two pages of data from the data registers to the NAND Flash arrays. The
pages must be programmed to different planes on the same die. Within a block, the
pages must be programmed consecutively from the least significant to the most
significant page address. Random page programming within a block is prohibited. The
first plane and second plane addresses must meet the two-plane addressing
requirements (see “Two-Plane Addressing” on page 38).
To enter the two-plane program page cache mode, write the 80h command to the
command register, write five ADDRESS cycles for the first plane, then write the data.
Serial data is loaded on consecutive WE# cycles starting at the given address. Next,
write the 11h command. The 11h command is a “dummy” command that informs the
control logic that the first set of data for the first plane is complete. No programming of
the NAND Flash array occurs. R/B# goes LOW for tDBSY, then returns HIGH. The READ
STATUS (70h) command also indicates that the device is ready when status register bit
6 is set to “1.” The only valid commands during tDBSY are READ STATUS (70h) and
RESET (FFh).
After tDBSY, write the 80h (or 81h) command to the command register, write five
ADDRESS cycles for the second plane, then write the data. The CACHE WRITE (15h)
command is written after the second-plane data input is complete. Data is transferred
from the cache registers to the data registers on the rising edge of WE#. R/B# goes
LOW during this transfer time. After the data has been copied into the data registers
and R/B# returns HIGH, memory array programming to both planes begins.
When R/B# returns HIGH, new data can be written to the cache registers by issuing
another TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h or 80h-11h-
81h-15h) sequence. The time that R/B# stays LOW (tCBSY) is determined by the
actual programming time of the previous operation. For the first cache operation, the
duration of tCBSY is the time it takes for the data to be copied from the cache registers
to the data registers. On the second and subsequent TWO-PLANE PROGRAM PAGE
CACHE MODE operations, transfer from the cache registers to the data registers is
delayed until the current data register contents have been programmed into the arrays.
If the R/B# pin is used to determine programming completion, the last operation of the
program sequence must use the TWO-PLANE PROGRAM PAGE (80h-11h-80h-10h or
80h-11h-81h-10h) command instead of the TWO-PLANE PROGRAM PAGE CACHE MODE
(80h-11h-80h-15h or 80h-11h-81h-15h) command. If the TWO-PLANE PROGRAM
PAGE CACHE MODE (80h-11h-80h-15h or 80h-11h-81h-15h) command is used for the
last operation, then use READ STATUS (70h) to monitor the operation progress; status
register bit 5 indicates when programming is complete. See Table 13 on page 36 for
details of the status register.
To determine when the current TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-
80h-10h or 80h-11h-81h-10h) operation has completed, issue the READ STATUS (70h)
command and check status register bits 5 and 6. When the device is ready, use status
register bit 0 to determine if the current operation passed and status register bit 1 to
determine if the previous operation passed. If either bit 0 or bit 1 = “1,” indicating a
failed operation, then use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command twice—once for each plane—to determine which current or previous plane
operation failed. For more information on status register bit definitions, see Table 18 on
page 30.
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During the serial data input for either plane, the RANDOM DATA INPUT (85h) command
can be used any number of times to change the column address within that plane. For
details on this command, see Section 7.3.3, “RANDOM DATA INPUT 85h” on page 31.
See Figure 32 on page 44 for an example.
Figure 32.
TWO-PLANE PROGRAM PAGE CACHE MODE
t
t
CBSY
DBSY
R/B#
I/Ox
80h
Address/data input
11h
80h
Address/data input
15h
1st plane
(or 81h)
2nd plane
1
t
t
CBSY
DBSY
R/B#
I/Ox
80h
Address/data input
11h
Address/data input
15h
80h
1st plane
2nd plane
(or 81h)
1
2
t
t
LPROG
DBSY
R/B#
I/Ox
80h
Address/data input
11h
Address/data input
10h
80h
1st plane
(or 81h)
2nd plane
2
7.7.6
TWO-PLANE INTERNAL DATA MOVE 00h-00h-35h/85h-11h-
80h-10h
A TWO-PLANE INTERNAL DATA MOVE operation is similar to an INTERNAL DATA MOVE
operation, and requires two sequences. Issue a TWO-PLANE READ for INTERNAL DATA
MOVE (00h-00h-35h) command first, then the TWO-PLANE PROGRAM for INTERNAL
DATA MOVE (85h-11h-80h-10h) command. Data moves are only supported within the
planes from which data is read. The first plane and second plane addresses must meet
the two-plane addressing requirements for both the TWO-PLANE READ for INTERNAL
DATA MOVE (00h-00h-35h) and TWO-PLANE PROGRAM for INTERNAL DATA MOVE
(85h-11h-80h-10h) commands (see “Two-Plane Addressing” on page 38).
7.7.7
TWO-PLANE READ for INTERNAL DATA MOVE 00h-00h-35h
The TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command is used in
conjunction with the TWO-PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-80h-
10h) command. First, write 00h to the command register, then write the first plane
internal source address (five cycles). Again, write 00h to the command register,
followed by the second-plane internal source address (five cycles). Finally, write 35h to
the command register. After the 35h command, R/B# goes LOW for tR while two pages
are read into their respective cache registers.
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The memory device is now ready to accept the TWO-PLANE PROGRAM for INTERNAL
DATA MOVE (85h-11h-80h-10h) command.
7.7.8
TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-80h-
10h or 85h-11h-81h-10h
After the TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command has
been issued and R/B# goes HIGH (or the status register bit 6 is “1”), the TWO-PLANE
PROGRAM for INTERNAL DATA MOVE (85h-11h-80h-10h or 85h-11h-81h-10h)
command is used. Pages must be read from and programmed to the same plane.
First, write 85h to the command register, then write the first plane destination address
(five cycles), then write 11h to the command register. The 11h command is a “dummy”
command that informs the control logic that the first set of data for the first plane is
complete. No programming of the NAND Flash array occurs. R/B# goes LOW for tDBSY,
then returns HIGH. The READ STATUS (70h) command also indicates that the device is
ready when status register bit 6 is set to “1.” The only valid commands during tDBSY
are READ STATUS (70h) and RESET (FFh).
After tDBSY, write the 80h (or 81h) command to the command register, then write the
second plane destination address (five cycles), then write 10h to the command register.
Data is transferred from the cache registers to the data registers on the rising edge of
WE#, and programming begins on both planes.
R/B# goes LOW for the duration of array programming time, tPROG. When
programming and verification are complete, R/B# returns HIGH. The READ STATUS
(70h) command also indicates that the device is ready when status register bit 6 is set
to “1.” The only valid commands during tPROG are READ STATUS (70h), TWO-PLANE/
MULTIPLE-DIE READ STATUS (78h), and RESET (FFh).
If the READ STATUS (70h) command indicates an error in the operation (status register
bit 0 = “1”), use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command twice—
once for each plane—to determine which plane operation failed.
During the serial data input for either plane, the RANDOM DATA INPUT (85h) command
can be used any number of times to change the column address within that plane. For
details on this command, see Section 7.3.3, “RANDOM DATA INPUT 85h” on page 31.
See Figure 33 on page 45 for an example.
Figure 33.
TWO-PLANE INTERNAL DATA MOVE
t
t
DBSY
R
R/B#
I/Ox
00h Address (5 cycles) 00h Address (5 cycles) 35h
85h Address (5 cycles) 11h
1st plane destination
1st plane source
2nd plane source
1
t
PROG
R/B#
I/Ox
Address (5 cycles) 10h
2nd plane destination
70h
Status
80h
(or 81h)
1
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Figure 34.
TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT
t
R
R/B#
I/Ox
00h Address (5 cycles) 00h Address (5 cycles) 35h
1st plane source 2nd plane source
85h Address (5 cycles)
Data
85h Address (2 cycles) Data 11h
1st plane destination Optional
Unlimited number
of repetitions
1
t
t
PROG
DBSY
R/B#
I/Ox
80h
Address (5 cycles)
Data
85h Address (2 cycles)
Data
10h
70h
Status
Optional
Unlimited number
of repetitions
(or 81h) 2nd plane destination
1
7.7.9
TWO-PLANE BLOCK ERASE 60h-60h-D0h
The TWO-PLANE BLOCK ERASE (60h-60h-D0h) operation is similar to the BLOCK
ERASE (60h-D0h) operation. It erases two blocks instead of one. The blocks to be
erased must be on different planes on the same die. The first plane and second plane
addresses must meet the two-plane addressing requirements (see “TWO-PLANE
Addressing” on page 38). Additionally, the page addresses, PA[5:0], for both planes
must be LOW.
Begin a TWO-PLANE BLOCK ERASE operation by writing 60h to the command register,
followed by three ADDRESS cycles of the first plane block address. Then write 60h
again to the command register, followed by three ADDRESS cycles of the second-plane
block address. Finally, issue the D0h command.
R/B# goes LOW for the duration of block erase time, tBERS. When block erase is
complete, R/B# returns HIGH. The READ STATUS (70h) command also indicates that
the device is ready when status register bit 6 is set to “1.” The only valid commands
during tBERS are READ STATUS (70h), TWO-PLANE/MULTIPLE-DIE READ STATUS
(78h), and RESET (FFh).
If the READ STATUS (70h) command indicates an error in the operation (status register
bit 0 = “1”), then use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command
twice—once for each plane—to determine which plane operation failed.
Intel® SD74 NAND Flash Memory
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Intel® SD74 NAND Flash Memory
Figure 35.
TWO-PLANE BLOCK ERASE Operation
CLE
CE#
WE#
ALE
t
BERS
R/B#
RE#
I/Ox
60h
60h
D0h
70h
Address input (3 cycles)
1st plane
Address input (3 cycles)
2nd plane
Status
I/O 0 = 0 ERASE successful
I/O 0 = 1 ERASE error
Don’t Care
7.7.10
TWO-PLANE/MULTIPLE-DIE READ STATUS 78h
In Intel® NAND Flash devices that have two planes, and possibly more than one die in
a package that share the same CE# pin, it is possible to independently poll the status
register of a particular plane and die using the TWO-PLANE/MULTIPLE-DIE READ
STATUS (78h) command. This command can be used to check the status register
during and after two-plane operations (with the exception of TWO-PLANE PAGE READ),
and to check the status of interleaved die operations.
After the 78h command is issued, the device requires three ADDRESS cycles containing
the block and page addresses, BA[18:6] and PA[5:0]. The most significant block
address bit in the third ADDRESS cycle, BA18, selects the proper die, and the least
significant block address bit in the first ADDRESS cycle, BA6, selects the proper plane
within that die.
After the 78h command and the three ADDRESS cycles, the status register is output on
I/O[7:0] when RE# is LOW. Changes in the status register will be seen on I/O[7:0] as
long as CE# and RE# are LOW; it is not necessary to issue a new TWO-PLANE/
MULTIPLE-DIE READ STATUS command to see these changes. The status register bit
definitions are identical to those reported by the READ STATUS (70h) command (see
Table 18, “Status Register Bit Definition” on page 30).
In devices that have more than one die sharing a common CE# pin, when one die is not
busy (status register bit 5 is “1”), it is possible to initiate a new operation to that die
even if the other die is busy (see Section 7.8, “Interleaved Die Operations” on
page 48).
If both die are busy during or following an interleaved die operation, the READ STATUS
(70h) command must not be used to check status, as both die will respond, causing
bus contention on I/O[7:0]. The TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command is required to check status during and after interleaved die operations.
Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is prohibited
during and following power-on RESET and OTP commands.
Intel® SD74 NAND Flash Memory
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47
Intel® SD74 NAND Flash Memory
Figure 36.
TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle
t
AR
t
t
WHR
REA
7.8
Interleaved Die Operations
In devices that have more than one die sharing a common CE# pin, it is possible to
significantly improve performance by interleaving operations between the die. When
both die are idle (R/B# is HIGH or status register bit 5 is “1”), issue a command to the
first die (BA18 = “0”). Then, while the first die is busy (R/B# is LOW), issue a command
to the other die (BA18 = “1”).
There are two ways to verify operation completion in each die: using the R/B# signal,
or monitoring the status register. R/B# remains LOW while either die is busy. When R/
B# goes HIGH, then both die are idle and the operations are complete. Alternatively,
the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command can report the status of
each die individually. If a die is performing a cache operation, like PROGRAM PAGE
CACHE MODE (80h-15h) or TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-
15h), then the die is able to accept the data for another cache operation when status
register bit 6 is “1.” All operations, including cache operations, are complete on a die
when status register bit 5 is “1.”
During and following interleaved die operations, the READ STATUS (70h) command is
prohibited. Instead, use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command. This command selects which die will report status. Interleaved two-plane
commands must also meet the requirements in “TWO-PLANE Addressing” on page 38.
PROGRAM PAGE, PROGRAM PAGE CACHE MODE, TWO-PLANE PROGRAM PAGE, TWO-
PLANE PROGRAM PAGE CACHE MODE, BLOCK ERASE, and TWO-PLANE BLOCK ERASE
can be used as interleaved operations on separate die that share a common CE#.
7.8.1
Interleaved PROGRAM PAGE Operations
Figure 37 on page 49 and Figure 38 on page 49 show how to perform two types of
interleaved PROGRAM PAGE operations. In Figure 37, the R/B# signal is monitored for
operation completion. In Figure 38, the status register is monitored for operation
completion with the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command.
RANDOM DATA INPUT (85h) is permitted during interleaved PROGRAM PAGE
operations.
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Figure 37.
Interleaved PROGRAM PAGE with R/B# Monitoring
I/Ox
80h Address Data 10h
Die 1
80h Address Data 10h
Die 2
80h Address Data 10h
Die 1
80h Address Data 10h
Die 2
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
Figure 38.
Interleaved PROGRAM PAGE with Status Register Monitoring
I/Ox
78h
80h Address Data 10h
Die 1
80h Address Data 10h
Die 2
Address Status
Die 1
80h Address Data 10h
Die 1
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
7.8.2
Interleaved PROGRAM PAGE CACHE MODE Operations
Figure 37 and Figure 38 show how to perform two types of interleaved PROGRAM PAGE
CACHE MODE operations. In Figure 37, the R/B# signal is monitored. In Figure 38, the
status register is monitored with the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command.
RANDOM DATA INPUT (85h) is permitted during interleaved PROGRAM PAGE CACHE
MODE operations.
Figure 39.
Interleaved PROGRAM PAGE CACHE MODE with R/B# Monitoring
I/Ox
80h Address Data 15h
Die 1
80h Address Data 15h
Die 2
80h Address Data 15h
Die 1
80h Address Data 15h
Die 2
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
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Intel® SD74 NAND Flash Memory
Figure 40.
Interleaved PROGRAM PAGE CACHE MODE with Status Register Monitoring
I/Ox
78h
80h Address Data 15h
Die 1
80h Address Data 15h
Die 2
Address Status
Die 1
80h Address Data 15h
Die 1
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
7.8.3
Interleaved TWO-PLANE PROGRAM PAGE Operations
Figure 41 and Figure 42 show how to perform two types of interleaved TWO-PLANE
PROGRAM PAGE operations. In Figure 41, the R/B# signal is monitored for operation
completion. In Figure 42, the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command is used to monitor the status register for operation completion.
The interleaved TWO-PLANE PROGRAM PAGE operation must meet two-plane
addressing requirements. See Section 7.7.1, “TWO-PLANE Addressing” on page 38 for
details.
RANDOM DATA INPUT (85h) is permitted during interleaved TWO-PLANE PROGRAM
PAGE operations.
Figure 41.
Interleaved TWO-PLANE PROGRAM PAGE with R/B# Monitoring
I/Ox
80h Address Data 11h
Die 1
80h Address Data 10h
Die 1
80h Address Data 11h
Die 2
80h Address Data 10h
Die 2
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
1
I/Ox
80h Address Data 11h
Die 1
80h Address Data
Die 1
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
1
Note: Two-plane addressing requirements apply.
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Figure 42.
Interleaved TWO-PLANE PROGRAM PAGE with Status Register Monitoring
I/Ox
80h Address Data 11h
Die 1
80h Address Data 10h
Die 1
80h Address Data 11h
Die 2
80h Address Data 10h
Die 2
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
1
80h Address Data 11h
Die 1
I/Ox
R/B#
78h Address Status
Die 1
80h Address Data 10h
Die 1
78h Address Status
Die 2
80h Address Data 11h
Die 2
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
1
Note: Two-plane addressing requirements apply.
7.8.4
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE
Operations
Figure 43 and Figure 44 show how to perform two types of interleaved TWO-PLANE
PROGRAM PAGE CACHE MODE operations. In Figure 43, the R/B# signal is monitored.
In Figure 44, the status register is monitored with the TWO-PLANE/MULTIPLE-DIE
READ STATUS (78h) command.
The interleaved TWO-PLANE PROGRAM PAGE CACHE MODE operation must meet two-
plane addressing requirements. See Section 7.7.1, “TWO-PLANE Addressing” on
page 38 for details.
RANDOM DATA INPUT (85h) is permitted during interleaved TWO-PLANE PROGRAM
PAGE CACHE MODE operations.
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Figure 43.
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE with R/B# Monitoring
I/Ox
80h Address Data 11h
Die 1
80h Address Data 15h
(or 81h)
80h Address Data 11h
Die 2
80h Address Data 15h
(or 81h)
Die 1
Die 2
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
1
I/Ox
15h
80h Address Data 11h
Die 1
80h Address Data
(or 81h)
Die 1
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
1
Figure 44.
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE with Status Register
Monitoring
80h Address Data 11h
Die 1
80h Address Data 15h
(or 81h) Die 1
80h Address Data 11h
Die 2
80h Address Data 15h
(or 81h) Die 2
I/Ox
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
1
I/Ox
78h Address Status
Die 1
80h Address Data 11h
80h Address Data 15h
(or 81h)
78h Address Status
Die 2
80h Address Data 11h
Die 2
Die 1
Die 1
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
1
Note: Two-plane addressing requirements apply.
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7.8.5
Interleaved BLOCK ERASE Operations
Figure 45 and Figure 46 show how to perform two types of interleaved BLOCK ERASE
operations. In Figure 45, the R/B# signal is monitored for operation completion. In
Figure 46, the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is used to
monitor the status register for operation completion.
Figure 45.
Interleaved BLOCK ERASE with R/B# Monitoring
I/Ox
60h Address D0h
Die 1
60h Address D0h
Die 2
60h Address D0h
Die 1
60h Address D0h
Die 2
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
Figure 46.
Interleaved BLOCK ERASE with Status Register Monitoring
I/Ox
78h
60h Address D0h
Die 1
60h Address D0h
Die 2
Address Status
Die 1
60h Address D0h
Die 1
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
7.8.6
Interleaved TWO-PLANE BLOCK ERASE Operations
Figure 47 and Figure 48 show how to perform two types of interleaved BLOCK ERASE
operations. In Figure 47, the R/B# signal is monitored for operation completion. In
Figure 48, the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is used to
monitor the status register for operation completion.
The interleaved TWO-PLANE BLOCK ERASE operation must meet two-plane addressing
requirements. See Table 7.7.1, “TWO-PLANE Addressing” on page 38 for details.
Intel® SD74 NAND Flash Memory
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Intel® SD74 NAND Flash Memory
Figure 47.
Interleaved TWO-PLANE BLOCK ERASE with R/B# Monitoring
I/Ox
60h Address 60h Address D0h
Die 1 Die 1
60h Address 60h Address D0h
Die 2 Die 2
60h Address 60h Address D0h
Die 1 Die 1
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
Note: Two-plane addressing requirements apply.
Figure 48.
Interleaved TWO-PLANE BLOCK ERASE with Status Register Monitoring
I/Ox
60h Address 60h Address D0h
Die 1 Die 1
60h Address 60h Address D0h
Die 2 Die 2
78h Address Status
Die 1
60hAddress 60h Address D0h
Die 1 Die 1
R/B#
(die 1 internal)
R/B#
(die 2 internal)
R/B#
(external)
Note: Two-plane addressing requirements apply.
RESET Operation
RESET FFh
7.9
7.9.1
The RESET command is used to put the memory device into a known condition and to
abort a command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy
state. The contents of the memory location being programmed or the block being
erased are no longer valid. The data may be partially erased or programmed, and is
invalid. The command register is cleared and is ready for the next command. The data
register and cache register contents are marked invalid.
The status register contains the value E0h when WP# is HIGH; otherwise it is written
with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the
command register (see Figure 49 and Table 19).
The RESET command must be issued to all CE#s after power-on. The device will be
busy for a maximum of 1ms. Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS
(78h) command is prohibited during and following the initial RESET command and OTP
operations.
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Figure 49.RESET Operation
CLE
CE#
WE#
R/B#
t
WB
t
RST
I/Ox
FFh
RESET
command
Table 19.
Status Register Contents After RESET Operation
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Condition
Status
Hex
WP# HIGH
WP# LOW
Ready
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
E0h
60h
Ready and write protected
7.10
WRITE PROTECT Operation
It is possible to enable and disable PROGRAM and ERASE commands using the WP#
pin. Figure 50 on page 55 through Figure 53 on page 56 illustrate the setup time
(tWW) required from WP# toggling until a PROGRAM or ERASE command is latched into
the command register. After command cycle 1 is latched, the WP# pin must not be
toggled until the command is complete and the device is ready (status register bit 5 is
“1”).
Figure 50.
ERASE Enable
WE#
t
WW
I/Ox
WP#
R/B#
60h
D0h
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Intel® SD74 NAND Flash Memory
Figure 51.
ERASE Disable
WE#
I/Ox
WP#
R/B#
t
WW
60h
80h
80h
D0h
Figure 52.
PROGRAM Enable
WE#
t
WW
I/Ox
WP#
R/B#
10h
Figure 53.
PROGRAM Disable
WE#
I/Ox
WP#
R/B#
t
WW
10h
§ §
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8.0
Error Management
Intel® SD74 NAND Flash Memory devices may have blocks that are invalid when
shipped from the factory. An invalid block is one that contains one or more bad bits.
Additional bad blocks may develop with use. However, the total number of available
blocks will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be used quite
reliably in systems that provide bad-block management and error correction
algorithms. This type of software environment ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
The first block (physical block address 00h) for each CE# is guaranteed to be valid with
ECC (up to 1,000 PROGRAM/ERASE cycles) when shipped from the factory. This
provides a reliable location for storing boot code and critical boot information.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid
blocks before shipping by programming data other than FFh into the first spare location
(column address 2,048) of the first or second page of each bad block.
System software should check the first spare address on the first and second page of
each block prior to performing any program or erase operations on the NAND Flash
device. A bad block table can then be created, allowing system software to map around
these areas. Factory testing is performed under worst-case conditions. Because blocks
marked “bad” may be marginal, it may not be possible to recover this information if the
block is erased.
Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the NAND Flash device, the following
precautions are required:
• Check status after a PROGRAM, ERASE, or INTERNAL DATA MOVE operation.
• Under typical-use conditions, a minimum of 1-bit ECC per 528 bytes of data is
required.
• Use bad block management and a wear-leveling algorithm.
§ §
Intel® SD74 NAND Flash Memory
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Intel® SD74 NAND Flash Memory
9.0
Timing Diagrams
Figure 54.
COMMAND LATCH Cycle
CLE
t
t
CLH
CLS
t
t
CH
CS
CE#
t
WP
WE#
ALE
t
t
ALH
DH
ALS
t
t
DS
I/Ox
COMMAND
Don’t Care
Figure 55.
ADDRESS LATCH Cycle
CLE
t
CLS
t
CS
CE#
t
WC
t
t
WH
WP
t
WE#
ALS
t
ALH
ALE
I/Ox
t
t
DS
DH
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
Undefined
Don’t Care
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Figure 56.
INPUT DATA LATCH Cycle
CLE
t
CLH
CE#
ALE
t
t
ALS
t
CH
t
WC
t
t
WP
WP
WP
WE#
I/Ox
t
WH
t
t
t
t
t
t
DS DH
DIN 0
DS DH
DS DH
DIN 1
DIN Final1
Don’t Care
1.
DIN Final = 2,111 (x8).
Figure 57.
SERIAL ACCESS Cycle After READ
t
CEA
CE#
t
CHZ
t
t
REA
t
REA
REA
t
t
REH
t
RP
COH
RE#
t
t
RHZ
RHZ
t
RHOH
I/Ox
R/B#
DOUT
DOUT
DOUT
t
t
RR
RC
Don’t Care
Note: Use this timing diagram for tRC ≥ 30ns.
Intel® SD74 NAND Flash Memory
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Intel® SD74 NAND Flash Memory
Figure 58.
SERIAL ACCESS Cycle After READ (EDO Mode)
CE#
t
t
RC
CHZ
t
t
t
RP
REH
COH
RE#
I/Ox
R/B#
t
t
t
REA
RLOH
DOUT
RHZ
REA
t
t
t
RHOH
CEA
DOUT
DOUT
t
RR
Don’t Care
Note: Use this timing diagram for tRC < 30ns.
Figure 59.
READ STATUS Operation
t
CLR
CLE
t
t
CLH
CLS
t
CS
CE#
t
t
CH
WP
WE#
t
t
CEA
t
CHZ
t
t
COH
WHR
RP
RE#
t
RHZ
t
RHOH
t
t
t
IR
t
DS DH
REA
Status
output
70h
I/Ox
Don’t Care
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Figure 60.
TWO-PLANE/MULTIPLE-DIE READ STATUS Operation
t
CS
CE#
CLE
WE#
ALE
RE#
t
t
CLH
CLS
t
t
WC
t
t
t
CH
WP
WP WH
t
t
CHZ
CEA
t
t
t
t
AR
ALH
ALS
ALH
t
COH
t
RHZ
t
t
REA
t
t
t
DH
WHR
RHOH
Status output
DS
I/Ox
78h
Row add 1 Row add 2 Row add 3
Don’t Care
Figure 61.
PAGE READ Operation
CLE
t
CLR
CE#
t
WC
WE#
t
WB
t
AR
ALE
RE#
t
t
t
R
RHZ
RC
t
t
RP
RR
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
DOUT
N
DOUT
N + 1
DOUT
M
I/Ox
R/B#
30h
00h
Busy
Don’t Care
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Intel® SD74 NAND Flash Memory
Figure 62.
READ Operation with CE# “Don’t Care”
CLE
CE#
RE#
ALE
t
R
R/B#
WE#
I/Ox
00h
Address (5 cycles)
30h
Data output
t
CEA
t
CE#
t
t
REA
CHZ
COH
RE#
Don’t Care
Out
I/Ox
Figure 63.
RANDOM DATA READ Operation
CLE
t
CLR
CE#
WE#
ALE
t
t
WB
RHW
t
t
WHR
AR
t
t
t
REA
R
RC
RE#
t
RR
DOUT
DOUT
DOUT
DOUT
Col
Col
Row
Row
Row
Col
Col
I/Ox
00h
30h
05h
E0h
N
N + 1
M
M + 1
add 1 add 2 add 1 add 2 add 3
add 1 add 2
Column address N
Column address M
Busy
R/B#
Don’t Care
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Figure 64.
PAGE READ CACHE MODE Operation, Part 1 of 2
CLE
t
t
t
CLS CLH
t
CH
CS
CE#
t
WC
WE#
ALE
t
t
RHW
CEA
t
RC
RE#
t
t
R
WB
t
REA
t
t
DS DH
t
RR
Col
add
Col
add
Row
add
Row
add
Row
add 3
DOUT DOUT
DOUT
0
00h
30h
31h
31h
I/Ox
1
2
1
2
0
1
Column address
00h
Page address
Page address
Page address
M + 1
t
t
DCBSYR2
DCBSYR1
M
M
R/B#
Column address 0
Column address 0
1
Continued to
of next page
1
Don’t Care
Figure 65.
PAGE READ CACHE MODE Operation, Part 2 of 2
CLE
t
t
t
t
CLS
CS
CLH
CH
CE#
WE#
ALE
t
t
t
RHW
CEA
RHW
t
RC
RE#
t
WB
t
RR
t
t
t
DS DH
31h
REA
DOUT
0
DOUT
1
DOUT
0
DOUT
1
DOUT
0
DOUT
1
I/Ox
R/B#
DOUT
DOUT
31h
DOUT
3Fh
DOUT
t
t
t
DCBSYR2
Page address
Page address
Page address
DCBSYR2
DCBSYR2
M + 1
M + 2
M + x
Column address 0
Column address 0
Column address 0
1
Don’t Care
Continued from
of previous page
1
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
63
Intel® SD74 NAND Flash Memory
Figure 66.
Figure 67.
Figure 68.
PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2
CLE
tCLS tCLH
t
t
CH
CS
CE#
t
WC
WE#
ALE
t
t
RHW
CEA
t
RC
RE#
t
REA
t
t
DS DH
Col
add
Col
add
Row
add
Row
add
Row
add 3
DOUT DOUT
DOUT
0
00h
30h
70h
Status
31h
70h
Status
00h
DOUT
31h
70h
Status
00h
I/Ox
1
2
1
2
0
1
Column address
00h
Page address
M
Page address
M
Page address
M + 1
I/O 5 = 0, Busy
1, Ready
I/O 6 = 0, Cache busy
1, Cache ready
I/O 6 = 0, Cache busy
=
=
=
1, Cache ready
Column address 0
Column address 0
1
Don’t Care
Continued to
of next page
1
PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2
CLE
t
t
t
t
CLS
CS
CLH
CH
CE#
WE#
ALE
t
t
RHW
CEA
t
RC
RE#
t
t
t
DS DH
REA
DOUT
0
DOUT
1
DOUT
0
DOUT
1
DOUT
0
DOUT
1
I/Ox
DOUT
31h
Status
00h
DOUT
31h
70h
Status
00h
DOUT
3Fh
70h
Status
00h
DOUT
70h
Page address
Page address
Page address
M + x
I/O 6 = 0, Cache busy
1, Cache ready
M + 1
I/O 6 = 0, Cache busy
1, Cache ready
M + 2
I/O 6 = 0, Cache busy
1, Cache ready
=
=
=
Column address 0
Column address 0
Column address 0
1
Don’t Care
Continued from
of previous page
1
READ ID Operation
CLE
CE#
WE#
t
AR
ALE
RE#
t
t
REA
WHR
I/Ox
90h
00h
Address, 1 cycle
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Intel® SD74 NAND Flash Memory
Datasheet
64
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Note: See Table 17, “Device ID and Configuration Codes” on page 29 for actual values.
Figure 69.
PROGRAM PAGE Operation
CLE
CE#
t
t
ADL
WC
WE#
t
t
t
WHR
WB
PROG
ALE
RE#
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
DIN
DIN
I/Ox
R/B#
80h
10h
70h
Status
N
M
SERIAL DATA
INPUT command
1 up to m Byte
serial input
PROGRAM
command
READ STATUS
command
x8 device: m = 2,112 bytes
Don’t Care
Figure 70.
Program Operation with CE# “Don’t Care”
CLE
CE#
WE#
ALE
I/Ox
80h
Address (5 cycles)
Data
t
input
Data
input
10h
t
CS
t
CH
CE#
WP
WE#
Don’t Care
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
65
Intel® SD74 NAND Flash Memory
Figure 71.
PROGRAM PAGE Operation with RANDOM DATA INPUT
CLE
CE#
t
t
t
ADL
WC
ADL
WE#
ALE
t
t
t
WB
PROG
WHR
RE#
Col
Col
Row
Row
Row
DIN
N
DIN
N+1
Col
Col
DIN
N
DIN
N+1
80h
85h
Status
I/Ox
10h
70h
add 1 add 2 add 1 add 2 add 3
add 1 add 2
SERIAL DATA
INPUT command
RANDOM DATA Column address
INPUT command
PROGRAM
command
READ STATUS
command
Serial input
Serial input
R/B#
Don’t Care
Figure 72.
INTERNAL DATA MOVE Operation
CLE
CE#
t
t
ADL
WC
WE#
ALE
t
t
t
t
WHR
WB
WB PROG
RE#
t
R
Col
Col
Row
Row
Row
Col
Col
Row Row Row
Data
1
Data
N
I/Ox
Status
00h
35h
85h
10h
70h
READ
STATUS
add 1 add 2 add 1 add 2 add 3
add 1 add 2 add 1 add 2 add 3
Busy
Busy
R/B#
INTERNAL
DATA MOVE
Don’t Care
Note: INTERNAL DATA MOVE operations are only supported within the plane from which data is read.
Figure 73.
PROGRAM PAGE CACHE MODE Operation
CLE
CE#
t
t
ADL
WC
WE#
ALE
t
t
t
t
t
WHR
WB CBSY
WB LPROG
RE#
Col
Col
Col
Row Row Row
add 1 add 2 add 3
DIN
DIN
Col
Row Row Row
DIN
DIN
I/Ox
80h
10h
70h
80h
15h
Status
add 1 add 2
add 1 add 2 add 1 add 2 add 3
N
M
N
M
SERIAL DATA
INPUT
Serial input PROGRAM
PROGRAM
R/B#
Last page - 1
Last page
Don’t Care
Intel® SD74 NAND Flash Memory
Datasheet
66
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
Figure 74.
PROGRAM PAGE CACHE MODE Operation Ending on 15h
CLE
CE#
t
t
t
ADL
WC
ADL
WE#
ALE
t
t
WHR
WHR
RE#
Col
add
Col
add
Row
add
Row
add
Row
add
Col
add
Col
add
Row Row
add add
Row
add 3
DIN
N
DIN
M
DIN
N
DIN
M
I/Ox
80h
15h 70h Status
80h
15h
70h
Status
70h
Status
1
2
1
2
3
1
2
1
2
SERIAL DATA
INPUT
Serial input PROGRAM
PROGRAM
Last page – 1
Last page
Poll status until:
I/O6 1, Ready
To verify successful completion of the last 2 pages:
=
I/O5
I/O0
I/O1
=
=
=
1, Ready
0, Last page PROGRAM successful
0, Last page – 1 PROGRAM successful
Don’t Care
Figure 75.
BLOCK ERASE Operation
CLE
CE#
t
WC
WE#
t
t
WHR
WB
ALE
RE#
t
BERS
Row
Row
Row
add 3
Status
I/Ox
R/B#
60h
D0h
70h
add 1
add 2
Row address
ERASE
command
READ STATUS
command
Busy
AUTO BLOCK
ERASE SETUP
command
I/O0
I/O0
=
=
0, Pass
1, Fail
Don’t Care
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
67
Intel® SD74 NAND Flash Memory
Figure 76.
RESET Operation
CLE
CE#
WE#
R/B#
t
WB
t
RST
I/Ox
FFh
RESET
command
§ §
Intel® SD74 NAND Flash Memory
Datasheet
68
March 2007
Order Number: 312774-012US
Intel® SD74 NAND Flash Memory
10.0
Ordering Information
Figure 77, “Decoder” on page 69 provides the device part number decoder and
Table 20, “Intel® NAND Flash Memory Ordering Information” on page 69 provides the
available combinations. For combinations not listed, please contact your local Intel
sales office.
Figure 77.
Decoder
J
S
2
9
F
0
4
G
0
8
A
A
N
B
1
Product Generation / Revisions
1-9 Generations
Package Designator
JS = 48-Pin Pb-Free TSOP
Process Identifier
A = 90nm, B = 72 nm, C = 50 nm
Group Designator
29F = Intel® Flash Memory
Product Technology Type
N = NAND Flash Memory
M = MLC NAND Flash Memory
Density
01G = 1Gb
02G = 2Gb
04G = 4Gb
08G = 8Gb
16G = 16Gb
32G = 32Gb
Operating Voltage Range
A = 3.3 V (2.70 – 3.60 V)
B = 1.8 V (1.70 – 1.95 V)
Device Configuration
# of Die
# of CE # of R/B
I/O
A
B
C
F
1
2
2
4
1
1
2
2
1
1
2
2
Common
Common
Common
Common
Device Bus Width
08=8 Bits
16 = 16 Bits
Table 20.
Intel® NAND Flash Memory Ordering Information
Marking Device #
(1st Mark Line)
MM # (2nd
Mark Line)
IM L1 Part Number
Device Nomenclature
4Gb, x8, 1 die, 3 V, NAND, 72 nm, 1st Gen
Intel Si (1000pc T&R), Pb-Free
880199
880200
887759
887753
881167
881166
JS29F04G08AANB1
29F04G08AANB1
29F08G08CANB2
29F16G08FANB1
4Gb, x8, 1 die, 3 V, NAND, 72 nm, 1st Gen
Intel Si (1000pc Tray Pack), Pb-Free
8Gb, x8, 2 die, 3 V, 2 CE, NAND, 72 nm, 1st
Gen Intel Si (1000pc T&R), Pb-Free
JS29F08G08CANB2
JS29F16G08FANB1
8Gb, x8, 2 die, 3 V, 2 CE, NAND, 72 nm, 1st
Gen Intel Si (1000pc Tray Pack), Pb-Free
16Gb, x8, 4 die, 3 V, 2 CE, NAND, 72 nm, 1st
Gen Intel Si (1000pc Tray Pack), Pb-Free
16Gb, x8, 4 die, 3 V, 2 CE, NAND, 72 nm, 1st
Gen Intel Si (1000pc T&R), Pb-Free
§ §
Intel® SD74 NAND Flash Memory
March 2007
Order Number: 312774-012US
Datasheet
69
Intel® SD74 NAND Flash Memory
Intel® SD74 NAND Flash Memory
Datasheet
70
March 2007
Order Number: 312774-012US
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