NTE9672 [NTE]
Integrated Circuit High Threshold Logic (HTL) Quad, 2-Input NAND Gate; 集成电路高阈值逻辑( HTL )四, 2输入与非门型号: | NTE9672 |
厂家: | NTE ELECTRONICS |
描述: | Integrated Circuit High Threshold Logic (HTL) Quad, 2-Input NAND Gate |
文件: | 总2页 (文件大小:24K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NTE9672
Integrated Circuit
High Threshold Logic (HTL)
Quad, 2–Input NAND Gate
Description:
This NTE9672 is a Quad, 2–Input NAND gate with active output pull–up in a 14–Lead DIP style pack-
age. The active output arrangement allows the circuit to handle capacitive loads at a higher speed
than is obtainable with a passive pullup configuration. Additionally, the impedance in the high state
is considerably less, and consequently makes this device more immune to electrical noise. The active
output configuration also allows for a more powerful arrangement to interface with discrete compo-
nents.
Electrical Characteristics: (TA = +25°C unless otherwise specified)
Parameter
Symbol
VOL
Test Conditions
Min Typ Max Unit
Output Voltage
IOL = 12mA, VIH = 8.5V, VCCL = 14V
–
–
–
1.5
–
V
V
VOH
IOH = –0.03mA, VIL = 6.5V, VCC = 15V,
12.5
VCCL = 14V
Short–Circuit Current
Reverse Current
ISC
IR
VCCH = 16V
–6.5
–
–
–
–
–
–
–
–
–
–15 mA
µA
VR = 16V, VCCL = 14V
VCEX = 16V
2
Output Leakage Current ICEX
–
100 µA
Forward Current
IF
VF = 1.5V, VR = 16V, VCCH = 16V
VCCH = 16V
–
–1.2 mA
ICCL
ICCH
t1–3+
t1+3–
–
6
mA
Power Drain Current
Total Device
–
20 mA
200 ns
100 ns
Switching Times
–
IOL =12mA (Pulse In),
IOH = –0.03mA (Pulse Out), VCC = 15V
–
Logic Symbol
Pin Connection Diagram
1
2
3
V
14
Input A1
Input B1
1
2
3
CC
4
5
6
13 Input B4
12 Input A4
Output Y1
9
8
Input A2
Input B2
4
5
11 Output Y4
10
10
Input B3
12
13
11
Output Y2
GND
6
7
9
8
Input A3
Positive Logic: 3 = 1 D 2
Input Loading Factor = 1
Output Loading Factor = 10
Output Y3
Propagation Delay Time = 110ns Typ
Typical Total Power Dissipation
Input High = 176mW
Inputs Low = 52mW
14
8
7
1
.785 (19.95) Max
.300 (7.62)
.200
(5.08)
Max
.100 (2.45)
.099 (2.5) Min
.600 (15.24)
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