TP3054WM-X [NSC]
Extended Temperature Serial Interface CODEC/Filter COMBO Family; 扩展温度串行接口编解码器/滤波器COMBO系列
| 型号： | TP3054WM-X |
| 厂家： | 
National Semiconductor |
| 描述： | Extended Temperature Serial Interface CODEC/Filter COMBO Family |
| 文件： | 总16页 (文件大小：668K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2005
TP3054-X, TP3057-X
Extended Temperature Serial Interface CODEC/Filter
COMBO® Family
General Description
Features
n −40˚C to +85˚C operation
The TP3054, TP3057 family consists of µ-law and A-law
monolithic PCM CODEC/filters utilizing the A/D and D/A
conversion architecture shown in Figure 1, and a serial PCM
interface. The devices are fabricated using National’s ad-
vanced double-poly CMOS process (microCMOS).
n Complete CODEC and filtering system (COMBO)
including:
— Transmit high-pass and low-pass filtering
— Receive low-pass filter with sin x/x correction
— Active RC noise filters
The encode portion of each device consists of an input gain
adjust amplifier, an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz. Also included are auto-zero circuitry and a com-
panding coder which samples the filtered signal and en-
codes it in the companded µ-law or A-law PCM format. The
decode portion of each device consists of an expanding
decoder, which reconstructs the analog signal from the com-
panded µ-law or A-law code, a low-pass filter which corrects
for the sin x/x response of the decoder output and rejects
signals above 3400 Hz followed by a single-ended power
amplifier capable of driving low impedance loads. The de-
vices require two 1.536 MHz, 1.544 MHz or 2.048 MHz
transmit and receive master clocks, which may be asynchro-
nous; transmit and receive bit clocks, which may vary from
64 kHz to 2.048 MHz; and transmit and receive frame sync
pulses. The timing of the frame sync pulses and PCM data is
compatible with both industry standard formats.
— µ-law or A-law compatible COder and DECoder
— Internal precision voltage reference
— Serial I/O interface
— Internal auto-zero circuitry
n µ-law, 16-pin—TP3054
n A-law, 16-pin—TP3057
n Designed for D3/D4 and CCITT applications
n
5V operation
n Low operating power—typically 50 mW
n Power-down standby mode—typically 3 mW
n Automatic power-down
n TTL or CMOS compatible digital interfaces
n Maximizes line interface card circuit density
n Dual-In-Line or PCC surface mount packages
n See also AN-370, “Techniques for Designing with
CODEC/Filter COMBO Circuits”
Connection Diagrams
Dual-In-Line Package
Plastic Chip Carriers
00867401
Top View
Order Number TP3054N-X
NS Package Number N16E
Order Number TP3054WM-X
NS Package Number M16B
00867408
Top View
Order Number TP3057V-X
NS Package Number V20A
COMBO® and TRI-STATE® are registered trademarks of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation
DS008674
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Block Diagram
00867402
FIGURE 1.
Pin Descriptions
Symbol
Function
BCLKR/CLKSEL The bit clock which shifts data into DR
after the FSR leading edge. May vary
from 64 kHz to 2.048 MHz.
Symbol
Function
VBB
Negative power supply pin.
VBB = −5V 5%.
Alternatively, may be a logic input
which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in
synchronous mode and BCLKX is used
for both transmit and receive directions
(see Table 1).
GNDA
VFRO
VCC
Analog ground. All signals are
referenced to this pin.
Analog output of the receive power
amplifier.
Positive power supply pin.
VCC = +5V 5%.
MCLKR/PDN
Receive master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLKX, but should
be synchronous with MCLKX for best
performance. When MCLKR is
FSR
Receive frame sync pulse which
enables BCLKR to shift PCM data into
DR. FSR is an 8 kHz pulse train. See
Figure 2 and Figure 3 for timing details.
Receive data input. PCM data is shifted
into DR following the FSR leading edge.
connected continuously low, MCLKX is
selected for all internal timing. When
MCLKR is connected continuously high,
the device is powered down.
DR
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2
With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLKR/
CLKSEL. In this synchronous mode, the bit clock, BCLKX,
may be from 64 kHz to 2.048 MHz, but must be synchronous
with MCLKX.
Pin Descriptions (Continued)
Symbol
MCLKX
Function
Transmit master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLKR. Best
performance is realized from
synchronous operation.
Each FSX pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled DX output on the positive edge of BCLKX. After 8 bit
clock periods, the TRI-STATE DX output is returned to a high
impedance state. With an FSR pulse, PCM data is latched
via the DR input on the negative edge of BCLKX (or BCLKR
if running). FSX and FSR must be synchronous with
FSX
Transmit frame sync pulse input which
enables BCLKX to shift out the PCM
data on DX. FSX is an 8 kHz pulse
train, see Figure 2 and Figure 3 for
timing details.
MCLKX/R
.
BCLKX
The bit clock which shifts out the PCM
data on DX. May vary from 64 kHz to
2.048 MHz, but must be synchronous
with MCLKX.
TABLE 1. Selection of Master Clock Frequencies
Master Clock
BCLKR/CLKSEL
Frequency Selected
DX
The TRI-STATE® PCM data output
which is enabled by FSX.
TP3057
TP3054
1.536 MHz or
1.544 MHz
2.048 MHz
Clocked
2.048 MHz
TSX
Open drain output which pulses low
during the encoder time slot.
Analog output of the transmit input
amplifier. Used to externally set gain.
Inverting input of the transmit input
amplifier.
0
1
1.536 MHz or
1.544 MHz
2.048 MHz
GSX
VFXI−
VFXI+
1.536 MHz or
1.544 MHz
Non-inverting input of the transmit input
amplifier.
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLKX and MCLKR must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLKR should be synchronous
with MCLKX, which is easily achieved by applying only static
logic levels to the MCLKR/PDN pin. This will automatically
connect MCLKX to all internal MCLKR functions (see Pin
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FSX starts each encoding cycle and must be synchronous
with MCLKX and BCLKX. FSR starts each decoding cycle
and must be synchronous with BCLKR. BCLKR must be a
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLKX and BCLKR may operate from
64 kHz to 2.048 MHz.
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initial-
izes the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the DX and VFRO
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLKR/PDN pin and FSX and/or FSR pulses must be
present. Thus, 2 power-down control modes are available.
The first is to pull the MCLKR/PDN pin high; the alternative is
to hold both FSX and FSR inputs continuously low—the
device will power-down approximately 1 ms after the last
FSX or FSR pulse. Power-up will occur on the first FSX or
FSR pulse. The TRI-STATE PCM data output, DX, will remain
in the high impedance state until the second FSX pulse.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FSX and FSR, must be one bit clock period long, with
timing relationships specified in Figure 2. With FSX high
during a falling edge of BCLKX, the next rising edge of
BCLKX enables the DX TRI-STATE output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge
disables the DX output. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling
edge of BCLKR latches in the sign bit. The following seven
falling edges latch in the seven remaining bits. All four de-
vices may utilize the short frame sync pulse in synchronous
or asynchronous operating mode.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLKX
and the MCLKR/PDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up the device
and a high level powers down the device. In either case,
MCLKX will be selected as the master clock for both the
transmit and receive circuits. A bit clock must also be applied
to BCLKX and the BCLKR/CLKSEL can be used to select the
proper internal divider for a master clock of 1.536 MHz,
1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the
device automatically compensates for the 193rd clock pulse
each frame.
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pre-filter, followed by an eighth order switched-capacitor
bandpass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. The A/D
is of companding type according to µ-law (TP3054) or A-law
(TP3057) coding conventions. A precision voltage reference
is trimmed in manufacturing to provide an input overload
(tMAX) of nominally 2.5V peak (see table of Transmission
Characteristics). The FSX frame sync pulse controls the
sampling of the filter output, and then the successive-
approximation encoding cycle begins. The 8-bit code is then
loaded into a buffer and shifted out through DX at the next
FSX pulse. The total encoding delay will be approximately
165 µs (due to the transmit filter) plus 125 µs (due to encod-
ing delay), which totals 290 µs. Any offset voltage due to the
filters or comparator is cancelled by sign bit integration.
Functional Description (Continued)
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses,
FSX and FSR, must be three or more bit clock periods long,
with timing relationships specified in Figure 3. Based on the
transmit frame sync, FSX, the COMBO will sense whether
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The DX TRI-STATE output buffer is
enabled with the rising edge of FSX or the rising edge of
BCLKX, whichever comes later, and the first bit clocked out
is the sign bit. The following seven BCLKX rising edges clock
out the remaining seven bits. The DX output is disabled by
the falling BCLKX edge following the eighth rising edge, or by
FSX going low, whichever comes later. A rising edge on the
receive frame sync pulse, FSR, will cause the PCM data at
DR to be latched in on the next eight falling edges of BCLKR
(BCLKX in synchronous mode). All four devices may utilize
the long frame sync pulse in synchronous or asynchronous
mode.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter clocked
at 256 kHz. The decoder is A-law (TP3057) or µ-law
(TP3054) and the 5th order low pass filter corrects for the sin
x/x attenuation due to the 8 kHz sample/hold. The filter is
then followed by a 2nd order RC active post-filter/power
amplifier capable of driving a 600Ω load to a level of 7.2
dBm. The receive section is unity-gain. Upon the occurrence
of FSR, the data at the DR input is clocked in on the falling
edge of the next eight BCLKR (BCLKX) periods. At the end of
the decoder time slot, the decoding cycle begins, and 10 µs
later the decoder DAC output is updated. The total decoder
delay is ∼10 µs (decoder update) plus 110 µs (filter delay)
In applications where the LSB bit is used for signalling, with
FSR two bit clock periods long, the decoder will interpret the
lost LSB as “1⁄
” to minimize noise and distortion.
2
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be realized.
The op amp drives a unity-gain filter consisting of RC active
plus 62.5 µs (1⁄
frame), which gives approximately 180 µs.
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4
Absolute Maximum Ratings (Note 1)
Voltage at any Digital Input or
Output
V
CC+0.3V to GNDA−0.3V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature Range
Storage Temperature Range
Lead Temperature
−55˚C to + 125˚C
−65˚C to +150˚C
VCC to GNDA
7V
VBB to GNDA
−7V
(Soldering, 10 sec.)
300˚C
Voltage at any Analog Input
or Output
VCC+0.3V to VBB−0.3V
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V 5%, VBB = −5.0V 5%; TA
=
−40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC
+5.0V, VBB = −5.0V, TA = 25˚C.
=
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACE
VIL
Input Low Voltage
Input High Voltage
0.6
V
V
VIH
VOL
2.2
Output Low Voltage
Output High Voltage
DX, IL=3.2 mA
0.4
0.4
0.4
V
SIGR, IL=1.0 mA
V
TSX, IL=3.2 mA, Open Drain
DX, IH=−3.2 mA
V
VOH
2.4
2.4
V
SIGR, IH=−1.0 mA
V
IIL
Input Low Current
GNDA≤VIN≤VIL, All Digital Inputs
VIH≤VIN≤VCC
−10
−10
−10
10
10
10
µA
µA
µA
IIH
IOZ
Input High Current
Output Current in High Impedance
State (TRI-STATE)
DX, GNDA≤VO≤VCC
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
IIXA
Input Leakage Current
Input Resistance
−2.5V≤V≤+2.5V, VFXI+ or VFXI−
−2.5V≤V≤+2.5V, VFXI+ or VFXI−
Closed Loop, Unity Gain
GSX
−200
200
nA
MΩ
Ω
RIXA
ROXA
RLXA
CLXA
VOXA
AVXA
FUXA
10
Output Resistance
Load Resistance
1
2
3
10
kΩ
pF
V
Load Capacitance
Output Dynamic Range
Voltage Gain
GSX
50
GSX, RL ≥ 10 kΩ
VFXI+ to GSX
−2.8
5000
1
2.8
V/V
MHz
mV
V
Unity Gain Bandwidth
Offset Voltage
V
V
OSXA
CMXA
−20
−2.5
60
20
>
Common-Mode Voltage
CMRRXA 60 dB
2.5
CMRRXA Common-Mode Rejection Ratio
PSRRXA Power Supply Rejection Ratio
DC Test
DC Test
dB
dB
60
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
RORF
RLRF
Output Resistance
Load Resistance
Pin VFRO
1
3
Ω
Ω
VFRO= 2.5V
600
CLRF
Load Capacitance
Output DC Offset Voltage
500
pF
mV
VOSRO
−200
200
POWER DISSIPATION (ALL DEVICES)
ICC0
IBB0
ICC1
IBB1
Power-Down Current
No Load (Note 2)
0.65
0.01
5.0
2.0
mA
mA
mA
mA
Power-Down Current
No Load (Note 2)
0.33
11.0
11.0
Power-Up (Active) Current
Power-Up (Active) Current
No Load( –40˚C to 85˚C)
No Load ( –40˚C to 85˚C)
5.0
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2: I
and I
are measured after first achieving a power-up state.
BB0
CC0
5
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Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V 5%, VBB = −5.0V 5%; TA
=
−40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC
=
+5.0V, VBB = –5.0V, TA = 25˚C. All timing parameters are assured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing
Conventions section for test methods information.
Symbol
1/tPM
Parameter
Conditions
Depends on the Device Used and the
BCLKR/CLKSEL Pin.
Min
Typ
Max
Units
MHz
MHz
MHz
ns
Frequency of Master Clocks
1.536
1.544
2.048
MCLKX and MCLKR
tRM
Rise Time of Master Clock
Fall Time of Master Clock
Period of Bit Clock
MCLKX and MCLKR
50
50
tFM
MCLKX and MCLKR
ns
tPB
485
488
15725
50
ns
tRB
Rise Time of Bit Clock
BCLKX and BCLKR
BCLKX and BCLKR
MCLKX and MCLKR
MCLKX and MCLKR
ns
tFB
Fall Time of Bit Clock
50
ns
tWMH
tWML
tSBFM
Width of Master Clock High
Width of Master Clock Low
Set-Up Time from BCLKX High
to MCLKX Falling Edge
160
160
100
ns
ns
First Bit Clock after
the Leading Edge
of FSX
Short Frame
Long Frame
ns
125
100
tSFFM
Setup Time from FSX High to
MCLKX Falling Edge
Long Frame Only
ns
tWBH
tWBL
tHBFL
Width of Bit Clock High
Width of Bit Clock Low
Holding Time from Bit Clock
Low to Frame Sync
VIH=2.2V
160
160
0
ns
ns
ns
VIL=0.6V
Long Frame Only
tHBFS
tSFB
Holding Time from Bit Clock
High to Frame Sync
Short Frame Only
Long Frame Only
0
115
0
ns
ns
ns
Set-Up Time from Frame Sync
to Bit Clock Low
tDBD
Delay Time from BCLKX High
to Data Valid
Load=150 pF plus 2 LSTTL Loads
140
tDBTS
tDZC
Delay Time to TSX Low
Delay Time from BCLKX Low to
Data Output Disabled
Delay Time to Valid Data from
FSX or BCLKX, Whichever
Comes Later
Load=150 pF plus 2 LSTTL Loads
CL=0 pF to 150 pF
140
165
ns
ns
50
20
tDZF
CL=0 pF to 150 pF
165
ns
tSDB
tHBD
tSF
Set-Up Time from DR Valid to
BCLKR/X Low
50
50
ns
ns
ns
ns
ns
Hold Time from BCLKR/X Low to
DR Invalid
Set-Up Time from FSX/R to
BCLKX/R Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
50
tHF
Hold Time from BCLKX/R Low
to FSX/R Low
Short Frame Sync Pulse (1 Bit Clock
Period Long)
100
100
tHBFl
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FSX or FSR)
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
tWFL
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
160
ns
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7
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8
Transmission Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V 5%, VBB = −5.0V 5%; TA
=
−40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
Absolute Levels
Nominal 0 dBm0 Level is 4 dBm
(600Ω)
(Definition of nominal gain)
0 dBm0
1.2276
Vrms
tMAX
Max Overload Level
TP3054 (3.17 dBm0)
TP3057 (3.14 dBm0)
TA=25˚C, VCC=5V, VBB=−5V
Input at GSx=0 dBm0 at 1020 Hz
f=16 Hz
2.501
2.492
VPK
VPK
GXA
GXR
Transmit Gain, Absolute
−0.15
0.15
−40
−30
−26
−0.1
0.15
0.20
0.1
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Transmit Gain, Relative to GXA
f=50 Hz
f=60 Hz
f=200 Hz
−1.8
−0.15
−0.15
−0.35
−0.7
f=300 Hz–3000 Hz
f=3152 Hz
f=3300 Hz
f=3400 Hz
0
f=4000 Hz
−14
−32
f=4600 Hz and Up, Measure
Response from 0 Hz to 4000 Hz
Relative to GXA
GXAT
GXAV
GXRL
Absolute Transmit Gain Variation
with Temperature
−0.15
0.15
dB
dB
Absolute Transmit Gain Variation
with Supply Voltage
Relative to GXA
−0.05
0.05
Transmit Gain Variations with
Level
Sinusoidal Test Method
Reference Level=−10 dBm0
VFXI+=−40 dBm0 to +3 dBm0
VFXI+=−50 dBm0 to −40 dBm0
VFXI+=−55 dBm0 to −50 dBm0
TA=25˚C, VCC=5V, VBB=−5V
Input=Digital Code Sequence
for 0 dBm0 Signal at 1020 Hz
f=0 Hz to 3000 Hz
−0.2
−0.4
−1.2
0.2
0.4
1.2
dB
dB
dB
GRA
Receive Gain, Absolute
−0.20
−0.15
−0.35
−0.7
0.20
0.15
0.1
dB
dB
dB
dB
dB
dB
GRR
Receive Gain, Relative to GRA
f=3300 Hz
f=3400 Hz
0
f=4000 Hz
−14
0.15
GRAT
GRAV
GRRL
Absolute Receive Gain Variation
with Temperature
Relative to GRA
−0.15
Absolute Receive Gain Variation
with Supply Voltage
Relative to GRA
−0.05
0.05
dB
Receive Gain Variations with
Level
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
Ideally Encoded
PCM Level =−40 dBm0 to +3 dBm0
PCM Level =−50 dBm0 to −40 dBm0
PCM Level =−55 dBm0 to −50 dBm0
−0.2
−0.4
−1.2
0.2
0.4
1.2
dB
dB
dB
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Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V 5%, VBB = −5.0V 5%; TA
=
−40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25˚C.
Symbol
AMPLITUDE RESPONSE
VRO Receive Output Drive Level
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Parameter
Conditions
Min
Typ
Max
Units
RL=600Ω
−2.5
2.5
V
DXA
DXR
Transmit Delay, Absolute
f=1600 Hz
290
195
120
50
315
220
145
75
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Transmit Delay, Relative to DXA
f=500 Hz−600 Hz
f=600 Hz−800 Hz
f=800 Hz−1000 Hz
f=1000 Hz−1600 Hz
f=1600 Hz−2600 Hz
f=2600 Hz−2800 Hz
f=2800 Hz−3000 Hz
f=1600 Hz
20
40
55
75
80
105
155
200
130
180
−25
−20
70
DRA
DRR
Receive Delay, Absolute
Receive Delay, Relative to DRA
f=500 Hz−1000 Hz
f=1000 Hz−1600 Hz
f=1600 Hz−2600 Hz
f=2600 Hz−2800 Hz
f=2800 Hz−3000 Hz
−40
−30
90
100
145
125
175
NOISE
NXC
Transmit Noise, C Message
Weighted
TP3054
12
16
dBrnC0
dBm0p
(Note 3)
NXP
Transmit Noise, P Message
Weighted
TP3057
−74
−67
(Note 3)
NRC
Receive Noise, C Message
Weighted
PCM Code is Alternating
Positive and Negative Zero — TP3054
TP3057 PCM Code Equals Positive
Zero —
8
11
dBrnC0
NRP
Receive Noise, P Message
Weighted
−82
−79
dBm0p
dBm0
NRS
Noise, Single Frequency
f=0 kHz to 100 kHz, Loop Around
Measurement, VFXI+=0 Vrms
VCC=5.0 VDC+100 mVrms
f=0 kHz−50 kHz (Note 4)
VBB=−5.0 VDC+ 100 mVrms
f=0 kHz−50 kHz (Note 4)
PCM Code Equals Positive Zero
−53
PPSRX
NPSRX
PPSRR
Positive Power Supply Rejection,
Transmit
40
40
dBC
dBC
Negative Power Supply Rejection,
Transmit
Positive Power Supply Rejection,
Receive
V
CC=5.0 VDC+100 mVrms
Measure VFR0
f=0 Hz−4000 Hz
38
38
35
dBC
dB
f=4 kHz−25 kHz
f=25 kHz−50 kHz
dB
NPSRR
Negative Power Supply Rejection,
Receive
PCM Code Equals Positive Zero
V
BB=−5.0 VDC+100 mVrms
Measure VFR0
f=0 Hz−4000 Hz
f=4 kHz−25 kHz
f=25 kHz−50 kHz
38
38
35
dBC
dB
dB
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10
Transmission Characteristics (Continued)
Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V 5%, VBB = −5.0V 5%; TA
=
−40˚C to +85˚C by correlation with 100% electrical testing at TA = 25˚C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25˚C.
Symbol
NOISE
SOS
Parameter
Conditions
Min
Typ
Max
Units
Spurious Out-of-Band Signals
at the Channel Output
Loop Around Measurement, 0 dBm0,
300 Hz to 3400 Hz Input PCM Code
Applied at DR.
−30
dB
4600 Hz–7600 Hz
−30
−40
−30
dB
dB
dB
7600 Hz–8400 Hz
8400 Hz–100,000 Hz
DISTORTION
STDX,
STDR
Signal to Total Distortion
Sinusoidal Test Method (Note 6)
Level=3.0 dBm0
Transmit or Receive
Half-Channel
33
36
28
29
13
14
dBC
dBC
dBC
dBC
dBC
dBC
dB
=0 dBm0 to −30 dBm0
=−40 dBm0
XMT
RCV
XMT
RCV
=−55 dBm0
SFDX
SFDR
IMD
Single Frequency Distortion,
Transmit
−43
−43
−41
Single Frequency Distortion,
Receive
dB
dB
Intermodulation Distortion
Loop Around Measurement,
VFXI+=−4 dBm0 to −21 dBm0, Two
Frequencies in the Range
300 Hz−3400 Hz
CROSSTALK
CTX-R
Transmit to Receive Crosstalk,
f=300 Hz−3400 Hz
−90
−90
−70
−70
dB
dB
0 dBm0 Transmit Level
Receive to Transmit Crosstalk,
0 dBm0 Receive Level
DR=Quiet PCM Code (Note 6)
f=300 Hz−3400 Hz, VFXI=Multitone
(Note 4)
CTR-X
ENCODING FORMAT AT DX OUTPUT
TP3054
TP3057
A-Law
µ-Law
(Includes Even Bit Inversion)
VIN (at GSX)=+Full-Scale
VIN (at GSX)=0V
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
VIN (at GSX)=−Full-Scale
Note 3: Measured by extrapolation from the distortion test result at −50 dBm0.
Note 4: PPSR , NPSR , and CT are measured with a −50 dBm0 activation signal applied to VF I .
+
X
X
R–X
X
Note 5: TP3054/57 are measured using C message weighted filter for µ-law and psophometric weighted filter for A-law.
@
Note 6: CT
1.544 MHz MCLK freq. is −70 dB max. 50% 5% BCLK duty cycle.
X X
X–R
11
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This common ground point should be decoupled to VCC and
VBB with 10 µF capacitors.
Applications Information
POWER SUPPLIES
RECEIVE GAIN ADJUSTMENT
While the pins of the TP3050 family are well protected
against electrical misuse, it is recommended that the stan-
dard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may be
plugged into a “hot” socket with power and clocks already
present, an extra long ground pin in the connector should be
used.
For applications where a TP3050 family CODEC/filter re-
ceive output must drive a 600Ω load, but a peak swing lower
than 2.5V is required, the receive gain can be easily ad-
justed by inserting a matched T-pad or π-pad at the output.
Table 2 lists the required resistor values for 600Ω termina-
tions. As these are generally non-standard values, the equa-
tions can be used to compute the attenuation of the closest
practical set of resistors. It may be necessary to use unequal
values for the R1 or R4 arms of the attenuators to achieve a
precise attenuation. Generally it is tolerable to allow a small
deviation of the input impedance from nominal while still
maintaining a good return loss. For example a 30 dB return
loss against 600Ω is obtained if the output impedance of the
attenuator is in the range 282Ω to 319Ω (assuming a perfect
transformer).
All ground connections to each device should meet at a
common point as close as possible to the GNDA pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 µF supply decou-
pling capacitors should be connected from this common
ground point to VCC and VBB, as close to device pins as
possible.
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common card
ground in star formation, rather than via a ground bus.
T-Pad Attenuator
00867411
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12
Applications Information (Continued)
π-Pad Attenuator
00867412
Note: See Application Note 370 for further details.
TABLE 2. Attentuator Tables for Z1=Z2=300Ω
(All Values in Ω)
dB
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
R1
1.7
R2
26k
13k
R3
3.5
6.9
R4
52k
26k
3.5
5.2
8.7k
6.5k
5.2k
4.4k
3.7k
3.3k
2.9k
2.6l
1.3k
850
650
494
402
380
284
244
211
184
161
142
125
110
98
10.4
13.8
17.3
21.3
24.2
27.7
31.1
34.6
70
17.4k
13k
6.9
8.5
10.5k
8.7k
7.5k
6.5k
5.8k
5.2k
2.6k
1.8k
1.3k
1.1k
900
785
698
630
527
535
500
473
450
430
413
386
366
10.4
12.1
13.8
15.5
17.3
34.4
51.3
68
3
107
144
183
224
269
317
370
427
490
550
635
720
816
924
1.17k
1.5k
4
5
84
6
100
115
379
143
156
168
180
190
200
210
218
233
246
7
8
9
10
11
12
13
14
15
16
18
20
77
61
13
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Typical Synchronous Application
00867406
FIGURE 4.
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14
Physical Dimensions inches (millimeters)
unless otherwise noted
Dual-In-Line Package (M)
Order Number TP3054WM-X
NS Package Number M16B
Molded Dual-In-Line Package (N)
Order Number TP3054N-X
NS Package Number N16E
15
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Cavity Dual-In-Line Package (V)
Order Number TP3057V-X
NS Package Number V20A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
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which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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