MM74HCA244N [NSC]
IC HC/UH SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDIP20, DIP-20, Bus Driver/Transceiver;
| 型号： | MM74HCA244N |
| 厂家： | 
National Semiconductor |
| 描述： | IC HC/UH SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDIP20, DIP-20, Bus Driver/Transceiver 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1990
MM74HCA244
Octal TRI-STATE Buffer
É
General Description
Features
Y
Typical propagation delay: 14 ns
These TRI-STATE buffers utilize advanced silicon-gate
CMOS technology and are general purpose high speed non-
inverting buffers. They possess high drive current outputs
which enable high speed operation even when driving large
bus capacitances. These circuits achieve speeds compara-
ble to low power Schottky devices, while retaining the ad-
vantage of CMOS circuitry, i.e., high noise immunity, and
low power consumption. All three devices have a fanout of
15 LS-TTL equivalent inputs.
Y
TRI-STATE outputs for connection to system buses
Wide power supply range: 2–6V
Low quiescent supply current: 40 mA
Output current: 6 mA
Y
Y
Y
Y
Y
Y
Y
Low output noise generation
QOS specification V
, V
OLV OLP
Identical pinout to HC
Speed upgrade to HC
The MM74HCA244 is a non-inverting buffer and has two
active low enables (1G and 2G). Each enable independently
controls 4 buffers. This device does not have Schmitt trigger
inputs.
All inputs are protected from damage due to static dis-
and ground.
charge by diodes to V
CC
Connection Diagram
Dual-In-Line Package
TL/F/10883–1
Top View
Order Number MM74HCA244
Truth Table
’HCA244
1G 1A 1Y 2G 2A 2Y
L
L
L
H
L
L
H
Z
Z
L
L
L
H
L
L
H
Z
Z
H
H
H
H
H
H
e
e
e
H
high level, L
low level, Z
high impedance
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/10883
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
6
Units
V
Supply Voltage (V
)
CC
2
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HCA
IN
CC
CC
b
a
85
40
C
§
DC Output Voltage (V
)
0.5 to V
OUT
Input Rise or Fall Times
g
g
g
Clamp Diode Current (I , I
)
20 mA
35 mA
70 mA
IK OK
e
e
e
(t , t )
r f
V
CC
V
CC
V
CC
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
DC Output Current, per pin (I
)
OUT
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering 10 seconds)
260 C
§
DC Electrical Characteristics (Note 4)
74HCA
e
T
25 C
§
A
eb
T
40 to 85 C
§
Symbol
Parameter
Conditions
V
Units
A
CC
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
3.0V
4.5V
6.0V
1.5
1.5
2.1
V
V
V
V
IH
2.1
3.15
4.2
3.15
4.2
Maximum Low Level
Input Voltage
2.0V
3.0V
4.5V
6.0V
0.5
0.9
0.5
0.9
V
V
V
V
IL
1.35
1.8
1.35
1.8
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
2.0V
3.0V
4.5V
6.0V
2.0
3.0
4.5
6.0
1.9
2.9
4.4
5.9
1.9
2.9
4.4
5.9
V
V
V
V
OH
IN
s
20 mA
l
OUT
l
e
V
I
V
or V
IH IL
3.0V
4.5V
6.0V
2.78
4.28
5.78
2.68
4.18
5.68
2.63
4.13
5.63
V
V
V
IN
s
s
6.0 mA
7.8 mA
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
2.0V
3.0V
4.5V
6.0V
0
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
V
IN
s
I
20 mA
l
OUT
l
e
V
I
V
or V
IH IL
3.0V
4.5V
6.0V
0.2
0.2
0.2
0.26
0.26
0.26
0.33
0.33
0.33
V
V
V
IN
s
s
6.0 mA
7.8 mA
l
l
OUT
OUT
l
l
I
e
g
g
1.0
I
I
Maximum Input
Current
V
V
or GND
CC
6.0V
0.1
mA
IN
IN
e
g
g
5
Maximum TRI-STATE
Output Leakage
Current
V
V
G
V , or V
IH IL
6.0V
0.5
mA
OZ
IN
e
V
CC
or GND
OUT
e
V
IH
2
DC Electrical Characteristics (Note 4) (Continued)
74HCA
eb
e
T
25 C
§
A
T
40 to 85 C
§
Symbol
Parameter
Conditions
V
Units
A
CC
Typ
Guaranteed Limits
e
V or GND
CC
I
Maximum Quiescent
Supply Current
V
6.0V
4.0
40
mA
CC
IN
e
I
0 mA
OUT
V
V
Quiet Output Max
Figure 1, 2
(Note 5)
OLP
5.5V
5.5V
0.550
V
V
Dynamic V
OL
Quiet Output Min
Dynamic V
Figure 1, 2
(Note 5)
OLV
b
0.750
OL
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
Note 5: n
e
b
number of device outputs, n 1 outputs switching, each driven 0V to 5.5V, one output at ground.
AC Electrical Characteristics MM74HCA244
e
e
e e
25 C, t t 6 ns
§
r f
V
5V, T
CC
A
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
e
t
t
t
, t
PHL PLH
Maximum Propagation
Delay
C
45 pF
14
17
24
24
ns
L
e
e
, t
PZH PZL
Maximum Enable Delay
to Active Output
R
1 kX
14
14
ns
ns
L
L
C
45 pF
e
e
, t
PHZ PLZ
Maximum Disable Delay
from Active Output
R
1 kX
L
C
L
5 pF
3
e
e
e e
50 pF, t t 6 ns (unless otherwise specified)
r f
AC Electrical Characteristics V
2.0V–6.0V, C
CC
L
74HCA
e
T
A
25 C
§
eb
T
A
40 to 85 C
§
Symbol
Parameter
Conditions
V
Units
CC
Typ
Guaranteed Limits
e
e
t , t
PHL PLH
Maximum Propagation
Delay
C
C
50 pF
2.0V
2.0V
42
51
90
115
165
ns
ns
L
150 pF
130
L
e
e
C
C
50 pF
3.3V
3.3V
21
26
27
39
35
50
ns
ns
L
150 pF
L
e
e
C
C
50 pF
4.5V
4.5V
14
17
18
26
23
33
ns
ns
L
150 pF
L
e
e
C
C
50 pF
6.0V
6.0V
10
14
15
22
20
28
ns
ns
L
150 pF
L
e
t , t
PZH PZL
Maximum Output Enable
Time
R
1 kX
L
e
e
C
C
50 pF
2.0V
2.0V
45
63
125
165
155
205
ns
ns
L
150 pF
L
e
e
C
C
50 pF
3.3V
3.3V
23
32
38
50
47
62
ns
ns
L
150 pF
L
e
e
C
C
50 pF
4.5V
4.5V
15
21
25
33
31
41
ns
ns
L
150 pF
L
e
e
C
C
50 pF
6.0V
6.0V
13
17
21
28
26
35
ns
ns
L
150 pF
L
e
e
t , t
PHZ PLZ
Maximum Output Disable
Time
R
1 kX
2.0V
3.3V
4.5V
6.0V
45
23
15
13
125
38
155
47
ns
ns
ns
ns
L
C
50 pF
L
25
31
21
26
t , t
TLH THL
Maximum Output
Rise and Fall Time
2.0V
3.3V
4.5V
6.0V
60
60
12
10
75
75
15
13
ns
ns
ns
ns
C
PD
Power Dissipation
(per buffer)
e
e
Capacitance (Note 5)
G
G
V
V
12
50
pF
pF
IH
IL
C
C
Maximum Input
Capacitance
5
10
10
pF
IN
Maximum Output
Capacitance
10
pF
OUT
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
4
Logic Diagram
’HCA244
TL/F/10883–2
5
HCA Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the noise
characteristics of HCA.
5. Set the word generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measurement.
6. Set the word generator input levels at 0V LOW and 5.5V
HIGH for HCA devices. Verify levels with a digital volt
meter.
Equipment:
Word Generator
Printed Circuit Board Test Fixture
Dual Trace Oscilloscope
V /V
OLP OLV
and V
/V :
OHP OHV
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50X coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
#
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF, 500X.
2. Deskew the word generator so that no two channels have
greater than 150 ps skew between them. This requires
that the oscilloscope be deskewed first. Swap out the
channels that have more than 150 ps of skew until all
channels being used are within 150 ps. It is important to
deskew the word generator channels before testing. This
will ensure that the outputs switch simultaneously.
Measure V
and V
OLV
on the quiet output during the
and V on the quiet out-
#
#
OLP
HL transition. Measure V
OHP
put during the LH transition.
OHV
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
3. Terminate all inputs and outputs to ensure proper loading
of the outputs and that the input levels are at the correct
voltage.
4. Set V
to 5.0V.
CC
TL/F/10883–3
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note A. V
and V
are measured with respect to ground reference.
OLP
OLV
k
150 ps.
e
e
e
3 ns, t 3 ns, skew
f
Note B. Input pulses have the following characteristics: f
1 MHz, t
r
TL/F/10883–4
FIGURE 2. Simultaneous Switching Test Circuit
6
7
Physical Dimensions inches (millimeters)
Dual-In-Line Package
Order Number MM74HCA244N
NS Package N20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
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Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
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