MM74HCA393J [NSC]
IC HCA SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP14, DIP-14, Counter;
| 型号： | MM74HCA393J |
| 厂家： | 
National Semiconductor |
| 描述： | IC HCA SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP14, DIP-14, Counter CD 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1990
MM74HCA390 Dual 4-Bit Decade Counter/
MM74HCA393 Dual 4-Bit Binary Counter
General Description
These counter circuits contain independent ripple carry
counters and utilize advanced silicon-gate CMOS technolo-
gy. The MM74HCA390 incorporates dual decade counters,
tionally as well as pin equivalent to the 74LS390/74LS393.
All inputs are protected from damage due to static dis-
charge by diodes to V
and ground.
CC
each composed of
a divide-by-two and a divide-by-five
counter. The divide-by-two and divide-by-five counters can
be cascaded to form dual decade, dual bi-quinary, or vari-
ous combinations up to a single divide-by-100 counter. The
MM74HCA393 contains two 4-bit ripple carry binary coun-
ters, which can be cascaded to create a single divide-by-
256 counter.
Features
Y
Typical operating frequency: 50 MHz
Y
Y
Y
Y
Typical propagation delay: 15 ns (Ck to Q )
A
Wide operating supply voltage range: 2–6V
k
Low input current: 1 mA
Low quiescent supply current: 40 mA maximum
(74HC Series)
Each of the two 4-bit counters is incremented on the high to
low transition (negative edge) of the clock input, and each
has an independent clear input. When clear is set high all
four bits of each counter are set to a low level. This enables
count truncation and allows the implementation of divide-by-
N counter configurations.
Y
Y
Y
Y
Y
Fanout of 10 LS-TTL loads
Low output noise generation
QOS specifications V
, V
OLV OLP
Identical pinout to HC
Speed upgrade of HC
Each of the counters outputs can drive 10 low power
Schottky TTL equivalent loads. These counters are func-
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/10886–3
Top View
TL/F/10886–1
Order Number MM74HCA390
Top View
Order Number MM74HCA393
C
1995 National Semiconductor Corporation
TL/F/10886
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
6
Units
V
Supply Voltage (V
)
CC
2
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
0.5 to V
1.5V
0.5V
IN
CC
CC
Operating Temp. Range (T )
A
MM74HCA
DC Output Voltage (V
)
b
a
85
40
C
OUT
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
Input Rise or Fall Times
DC Output Current, per pin (I
)
e
e
e
(t , t )
r f
V
V
V
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
OUT
CC
CC
CC
DC V or GND Current, per pin (I
CC
)
CC
)
b
a
65 C to 150 C
Storage Temperature Range (T
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temp. (T ) (Soldering 10 seconds)
L
260 C
§
DC Electrical Characteristics (Note 4)
74HCA
e
T
A
25 C
§
eb
T
40 to 85 C
§
Symbol
Parameter
Conditions
V
CC
Units
A
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
3.0V
4.5V
6.0V
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
V
V
IH
Maximum Low Level
Input Voltage
2.0V
3.0V
4.5V
6.0V
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
V
V
IL
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
3.0V
4.5V
6.0V
2.0
3.0
4.5
6.0
1.9
2.9
4.4
5.9
1.9
2.9
4.4
5.9
V
V
V
V
l
OUT
l
e
V
I
I
V
s
s
or V
4.0 mA
5.2 mA
3.0V
4.5V
6.0V
2.78
4.28
5.78
2.68
4.18
5.68
2.63
4.13
5.63
V
V
V
IN
IH IL
l
l
OUT
OUT
l
l
e
V
OL
Maximum Low Level
Output Voltage
V
I
V
s
or V
IL
20 mA
IN
IH
2.0V
3.0V
4.5V
6.0V
0
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
V
l
OUT
l
e
V
I
I
V
s
s
or V
4.0 mA
5.2 mA
3.0V
4.5V
6.0V
0.2
0.2
0.2
0.26
0.26
0.26
0.33
0.33
0.33
V
V
V
IN
IH IL
l
l
OUT
OUT
l
l
e
g
g
I
I
Maximum Input
Current
V
IN
V
CC
or GND
6.0V
6.0V
5.5V
5.5V
0.1
1.0
mA
mA
V
IN
e
Maximum Quiescent
Supply Current
V
IN
V
CC
or GND
4.0
40
CC
e
I
0 mA
OUT
V
Quiet Output
Maximum Dynamic V
Figures 1, 2
(Note 5)
0.550
OLP
OLV
OL
b
V
Quiet Output
Maximum Dynamic V
Figures 1, 2
(Note 5)
0.750
V
OL
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
Note 5:
@
1 outputs switching, each driven 0V to 5.5V, one output ground.
e
b
n
number of device outputs, n
2
AC Electrical Characteristics MM74HCA390/MM74HCA393
e
e
e
e e
15 pF, t t
r f
V
5V, T
25 C, C
§
6 ns
CC
A
L
Symbol
Parameter
Conditions
Typ
50
13
19
23
27
15
Guaranteed Limit
Units
MHz
ns
f
t
t
t
t
t
t
t
Maximum Operating Frequency
35
20
35
42
50
28
5
MAX
, t
PHL PLH
Maximum Propagation Delay, Clock A to Q
Maximum Propagation Delay, Clock A to Q
Maximum Propagation Delay, Clock A to Q
Maximum Propagation Delay, Clock A to Q
A
B
C
D
, t
PHL PLH
ns
, t
PHL PLH
ns
, t
PHL PLH
ns
Maximum Propagation Delay, Clear to any Q
Minimum Removal Time
ns
PHL
REM
W
b
2
ns
Minimum Pulse Width Clear or Clock
10
15
ns
e
e
e
6 ns (unless otherwise specified)
AC Electrical Characteristics C 50 pF, t
t
f
L
r
74HCA
eb
e
T
A
25 C
§
T
A
40 to 85 C
§
Symbol
Parameter
Conditions
V
Units
CC
Typ
Guaranteed Limits
f
t
t
t
t
t
t
t
t
Maximum Operating
Frequency
2.0V
3.3V
4.5V
6.0V
6
5
MAX
22
32
38
18
27
32
MHz
MHz
MHz
, t
PHL PLH
Maximum Propagation
Delay Clock A to Q
2.0V
3.3V
4.5V
6.0V
45
23
15
13
120
36
24
20
150
45
30
26
ns
ns
ns
ns
A
, t
PHL PLH
Maximum Propagation
Delay Clock A to Q
2.0V
3.3V
4.5V
6.0V
68
35
23
20
180
54
36
31
225
68
45
38
ns
ns
ns
ns
B
, t
PHL PLH
Maximum Propagation
Delay Clock A to Q
2.0V
3.3V
4.5V
6.0V
90
45
30
26
220
66
44
37
275
83
55
47
ns
ns
ns
ns
C
, t
PHL PLH
Maximum Propagation Delay
Clock to Q
2.0V
3.3V
4.5V
6.0V
100
53
35
30
260
78
52
44
325
98
65
55
ns
ns
ns
ns
D
Maximum Propagation
Delay Clear to any Q
2.0V
3.3V
4.5V
6.0V
54
27
18
15
150
45
30
26
190
57
38
33
ns
ns
ns
ns
PHL
REM
W
Minimum Clear Removal
Time
2.0V
3.3V
4.5V
6.0V
25
8
5
30
9
6
ns
ns
ns
ns
5
5
Minimum Pulse Width
Clear or Clock
2.0V
3.3V
4.5V
6.0V
30
15
10
9
75
75
15
13
95
95
19
16
ns
ns
ns
ns
, t
THL TLH
Maximum Output Rise
and Fall Time
2.0V
3.3V
4.5V
6.0V
30
12
8
75
75
15
13
95
95
19
16
ns
ns
ns
ns
7
C
C
Power Dissipation
Capacitance (Note 5)
(per counter)
42
pF
PD
Maximum Input Capacitance
5
pF
IN
2
e
a
e
a
V f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I V
CC CC
, and the no load dynamic current consumption, I
C
.
D
S
3
HCA Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the noise
characteristics of HCA.
4. Set V
to 5.0V.
CC
5. Set the word generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measurement.
Equipment:
6. Set the word generator input levels at 0V LOW and 5.5V
HIGH for HCA devices. Verify levels with a digital volt
meter.
Word Generator
Printed Circuit Board Test Fixture
Dual Trace Oscilloscope
V /V
OLP OLV
and V
/V :
OHP OHV
Procedure:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50X coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
#
1. Verify Test Fixture Loading: Standard Load 50 pF, 500X.
2. Deskew the word generator so that no two channels have
greater than 150 ps skew between them. This requires
that the oscilloscope be deskewed first. Swap out the
channels that have more than 150 ps of skew until all
channels being used are within 150 ps. It is important to
deskew the word generator channels before testing. This
will ensure that the outputs switch simultaneously.
Measure V
and V
OLV
on the quiet output during the
and V on the quiet out-
#
#
OLP
HL transition. Measure V
OHP
put during the LH transition.
OHV
3. Terminate all inputs and outputs to ensure proper loading
of the outputs and that the input levels are at the correct
voltage.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
TL/F/10885–4
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note A. V
and V
are measured with respect to ground reference.
OLP
OLV
k
150 ps.
e
e
e
3 ns, t 3 ns, skew
f
Note B. Input pulses have the following characteristics: f
1 MHz, t
r
TL/F/10885–5
FIGURE 2. Simultaneous Switching Test Circuit
4
Logic Timing Waveforms
TL/F/10886–2
5
6
Physical Dimensions inches (millimeters)
Order Number MM74HCA393J
NS Package Number J14A
Order Number MM74HCA390J
NS Package Number J16A
7
Physical Dimensions inches (millimeters) (Continued)
Order Number MM74HCA393N
NS Package Number N14A
Order Number MM74HCA390N
NS Package Number N16A
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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相关型号：
MM74HCA393N
IC HCA SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP14, DIP-14, Counter
TI
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