MM74C89N [NSC]
64-Bit TRI-STATE Random Access Read/Write Memory; 64位三态随机存取存储器读/写
| 型号： | MM74C89N |
| 厂家： | 
National Semiconductor |
| 描述： | 64-Bit TRI-STATE Random Access Read/Write Memory |
| 文件： | 总6页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1988
MM54C89/MM74C89 64-Bit TRI-STATE
Random Access Read/Write Memory
É
General Description
The MM54C89/MM74C89 is a 16-word by 4-bit random ac-
cess read/write memory. Inputs to the memory consist of
four address lines, four data input lines, a write enable line
and a memory enable line. The four binary address inputs
are decoded internally to select each of the 16 possible
word locations. An internal address register latches the ad-
dress information on the positive to negative transition of
the memory enable input. The four TRI-STATE data output
lines working in conjunction with the memory enable input
provide for easy memory expansion.
Read Operation: The complement of the information which
was written into the memory is non-destructively read out at
the four outputs. This is accomplished by selecting the de-
sired address and bringing memory enable low and write
enable high.
When the device is writing or disabled the output assumes a
TRI-STATE (Hi-z) condition.
Features
Y
Wide supply voltage range
Guaranteed noise margin
High noise immunity
Low power
3.0V to 15V
1.0V
Address Operation: Address inputs must be stable t pri-
SA
or to the positive to negative transition of memory enable. It
is thus not necessary to hold address information stable for
Y
Y
Y
0.45 V
CC
(typ.)
fan out of 2
driving 74L
more than t after the memory is enabled (positive to neg-
HA
ative transition of memory enable).
TTL compatibility
Y
Y
Y
Low power consumption
Fast access time
100 nW/package (typ.)
e
Note: The timing is different than the DM7489 in that a positive to negative
transition of the memory enable must occur for the memory to be
selected.
130 ns (typ.) at V
10V
CC
TRI-STATE output
Write Operation: Information present at the data inputs is
written into the memory at the selected address by bringing
write enable and memory enable low.
Logic and Connection Diagrams
Dual-In-Line Package
TL/F/5888–2
Top View
Order Number MM54C89
or MM74C89
TL/F/5888–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/5888
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation (P )
D
Dual-In-Line
Small Outline
700 mW
500 mW
b
a
0.3V
Voltage at any Pin
0.3V to V
CC
Operating V Range
CC
3.0V to 15V
18V
Operating Temperature Range
MM54C89
MM74C89
Absolute Maximum V
CC
b
a
55 C to 125 C
§
§
40 C to 85 C
Lead Temperature (T )
L
(Soldering, 10 seconds)
b
a
§
§
260 C
§
b
a
65 C to 150 C
Storage Temperature Range (T )
S
§
§
DC Electrical Characteristics Min/Max limits apply across temperature range, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
e
e
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
V
V
5.0V
10V
3.5
8.0
V
V
IN(1)
CC
CC
e
e
V
CC
V
CC
5.0V
10V
1.5
2.0
V
V
IN(0)
e
e
e b
V
CC
V
CC
5.0V, I
10V, I
10 mA
10 mA
4.5
9.0
V
V
OUT(1)
OUT(0)
O
e b
O
e
e
e a
V
CC
V
CC
5.0V, I
10V, I
10 mA
10 mA
0.5
1.0
V
V
O
e a
O
e
e
e
e
b
I
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
V
15V, V
15V
0V
0.005
b
0.005
1.0
mA
mA
IN(1)
IN(0)
OZ
CC
CC
IN
IN
b
V
15V, V
1.0
1.0
e
e
e
15V
e
Output Current in High
Impedance State
V
CC
V
CC
15V, V
15V, V
0.005
0.005
1.0
mA
mA
b
b
0V
O
e
I
Supply Current
V
CC
15V
0.05
300
mA
CC
CMOS/LPTTL INTERFACE
e
e
b
b
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
54C, V
74C, V
4.5V
4.75V
V
V
1.5
1.5
V
V
IN(1)
CC
CC
CC
CC
e
e
54C, V
74C, V
4.5V
4.75V
0.8
0.8
V
V
IN(0)
CC
CC
e
e
e b
360 mA
54C, V
74C, V
4.5V, I
O
4.75V, I
2.4
2.4
V
V
OUT(1)
OUT(0)
CC
CC
e b
360 mA
e a
360 mA
O
e
e
54C, V
74C, V
4.5V, I
O
4.75V, I
0.4
0.4
V
V
CC
CC
e a
360 mA
O
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
e
e
e
e
e
I
I
I
I
Output Source Current
(P-Channel)
V
T
5.0V, V
0V
SOURCE
SOURCE
SINK
CC
OUT
b
b
3.3
1.75
mA
mA
mA
mA
e
25 C
§
10V, V
A
e
Output Source Current
(P-Channel)
V
CC
0V
OUT
b
b
8.0
15
3.6
16
e
T
25 C
§
A
e
V
CC
Output Sink Current
(N-Channel)
V
T
5.0V, V
CC
OUT
OUT
1.75
8.0
e
25 C
§
10V, V
A
e
V
CC
Output Sink Current
(N-Channel)
V
CC
SINK
e
T
A
25 C
§
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Range’’ they are not
meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
e
e
50 pF, unless otherwise noted
AC Electrical Characteristics* T
25 C, C
§
Conditions
A
L
Symbol
Parameter
Min
Typ
Max
Units
e
e
t
t
t
t
t
Propagation Delay from
Memory Enable
V
V
5V
10V
270
100
500
220
ns
ns
pd
CC
CC
e
e
Access Time from
Address Input
V
CC
V
CC
5V
10V
350
130
650
280
ns
ns
ACC
SA
e
e
Address Setup Time
V
CC
V
CC
5V
10V
150
60
ns
ns
e
e
Address Hold Time
V
CC
V
CC
5V
10V
60
40
ns
ns
HA
ME
e
e
Memory Enable Pulse Width
V
CC
V
CC
5V
10V
400
150
250
90
ns
ns
2
e
e
50 pF, unless otherwise noted (Continued)
AC Electrical Characteristics* T
25 C, C
§
A
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
t
t
t
t
t
t
Write Enable Setup
Time for a Read
V
5V
10V
0
0
ns
ns
SR
WS
WE
HD
SD
CC
V
CC
e
e
Write Enable Setup
Time for a Write
V
CC
V
CC
5V
10V
t
t
ns
ns
ME
ME
e
e
e
0
Write Enable Pulse Width
Data Input Hold Time
Data Input Setup
V
CC
V
CC
5V, t
WS
10V, t
300
100
160
60
ns
ns
e
0
WS
e
e
V
CC
V
CC
5V
10V
50
25
ns
ns
e
e
V
CC
V
CC
5V
10V
50
25
ns
ns
e
e
e
e
e
5 pF, R 10k
L
5 pF, R
, t
1H 0H
Propagation Delay from a Logical
‘‘1’’ or Logical ‘‘0’’ to the High
Impedance State from
V
CC
V
CC
5V, C
L
10V, C
180
b
300
120
ns
ns
e
10k
85
L
L
Memory Enable
e
e
e
e
e
e
t , t
1H 0H
Propagation Delay from a Logical
‘‘1’’ or Logical ‘‘0’’ to the High
Impedance State from
Write Enable
V
CC
V
CC
50V, C
10V, C
5 pF, R
5 pF, R
10k
10k
180
85
300
120
ns
ns
L
L
L
L
C
C
C
Input Capacity
Any Input (Note 2)
5
pF
pF
pF
IN
Output Capacity
Any Output (Note 2)
(Note 3)
6.5
230
OUT
PD
Power Dissipation Capacity
*AC Parameters are guaranteed by DC correlated testing.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note,
PD
AN-90.
e
AC Electrical Characteristics* Guaranteed across the specified temperature range, C
50 pF
L
MM54C89
e b
MM74C89
e b
A
a
55 C to 125 C
a
Parameter
Conditions
T
T
40 C to 85 C
Units
§
§
Max
§
§
Max
A
Min
Min
e
e
e
t
t
t
t
t
t
t
V
V
V
5V
10V
15V
700
310
250
600
265
210
ns
ns
ns
PD
CC
CC
CC
e
e
e
V
CC
V
CC
V
CC
5V
10V
15V
910
400
320
780
345
270
ns
ns
ns
ACC
SA
e
e
e
V
CC
V
CC
V
CC
5V
10V
15V
210
90
70
180
80
60
ns
ns
ns
e
e
e
V
CC
V
CC
V
CC
5V
10V
15V
80
55
45
70
50
40
ns
ns
ns
HA
ME
WE
HD
e
e
e
V
CC
V
CC
V
CC
5V
10V
15V
560
210
170
480
180
150
ns
ns
ns
e
e
e
V
CC
V
CC
V
CC
5V
10V
15V
420
140
110
360
120
100
ns
ns
ns
e
e
e
V
CC
V
CC
V
CC
5V
10V
15V
70
35
30
60
30
25
ns
ns
ns
*AC Parameters are guaranteed by DC correlated testing.
3
AC Electrical Characteristics*
e
Guaranteed across the specified temperature range, C
50 pF (Continued)
L
MM54C89
a
55 C to 125 C
MM74C89
e b a
e b
Parameter
Conditions
T
A
T
A
40 C to 85 C
§
Units
§
§
§
Max
Min
Max
Min
e
e
e
t
t
V
V
V
5V
10V
15V
70
35
30
60
30
25
ns
ns
ns
SD
CC
CC
CC
e
e
e
, t
1H 0H
V
CC
V
CC
V
CC
5V
10V, C
15V, R
420
170
135
360
145
115
ns
ns
ns
e
e
5 pF
10 kX
L
L
*AC Parameters are guaranteed by DC correlated testing.
Truth Table
ME
WE
Operation
Write
Read
Inhibit, Storage
Inhibit, Storage
Condition of Outputs
TRI-STATE
Complement of Selected Word
TRI-STATE
TRI-STATE
L
L
H
H
L
H
L
H
AC Test Circuits
t
t
1H
0H
TL/F/5888–3
TL/F/5888–4
Switching Time Waveforms
t
t
1H
0H
TL/F/5888–6
TL/F/5888–5
Read Cycle
Write Cycle
TL/F/5888–8
TL/F/5888–7
4
Switching Time Waveforms (Continued)
Read Modify Write Cycle
TL/F/5888–9
e
e
Note: t
60 ns
10 ns
r
t
f
5
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C89J or MM74C89J
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number MM54C89N or MM74C89N
NS Package Number N16E
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