MM74C901N [FAIRCHILD]
Hex Inverting TTL Buffer . Hex Non-Inverting TTL Buffer; 六角反相TTL缓冲器。六角非反相缓冲器TTL
| 型号： | MM74C901N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Hex Inverting TTL Buffer . Hex Non-Inverting TTL Buffer |
| 文件： | 总6页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
MM74C901 • MM74C902
Hex Inverting TTL Buffer •
Hex Non-Inverting TTL Buffer
General Description
Features
■ Wide supply voltage range: 3.0V to 15V
The MM74C901 and MM74C902 hex buffers employ com-
plementary MOS to achieve wide supply operating range,
low power consumption, and high noise immunity. These
buffers provide direct interface from PMOS into CMOS or
TTL and direct interface from CMOS to TTL or CMOS
operating at a reduced VCC supply.
■ Guaranteed noise margin: 1.0V
■ High noise immunity: 0.45 VCC (typ.)
■ TTL compatibility: Fan out of 2 driving standard TTL
Ordering Code:
Order Number Package Number
Package Description
MM74C901M
MM74C901N
MM74C902M
MM74C902N
M14A
N14A
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
MM74C901
MM74C902
Top View
Top View
Logic Diagrams
MM74C901
MM74C902
CMOS to TTL Inverting Buffer
CMOS to TTL Buffer
© 1999 Fairchild Semiconductor Corporation
DS005909.prf
www.fairchildsemi.com
Operating VCC Range
Absolute Maximum VCC
Lead Temperature (TL)
(Soldering, 10 seconds)
3.0V to 15V
18V
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin
Voltage at Any Input Pin
MM74C901
−0.3V to VCC + 0.3V
260°C
−0.3V to +15V
−0.3V to +15V
MM74C902
Storage Temperature Range (TS)
−65°C to +150°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Power Dissipation (PD)
Dual-In-Line
700 mW
500 mW
Small Outline
Operating Temperature Range (TA)
MM74C901, MM74C902,
−40°C to +85°C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
= 5.0V
= 10V
= 5.0V
= 10V
3.5
8.0
V
V
IN(1)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
1.5
2.0
V
IN(0)
V
= 5.0V, I = −10 µA
4.5
9.0
V
OUT(1)
OUT(0)
O
= 10V, I = −10 µA
V
O
= 5.0V
= 10V
0.5
1.0
1.0
V
V
I
I
I
Logical “1” Input Current
Logical “0” Input Current
Supply Current
= 15V, V = 15V
0.005
−0.005
0.05
µA
µA
µA
IN(1)
IN(0)
CC
IN
= 15V, V = 0V
−1.0
IN
= 15V
15
TTL TO CMOS
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
V
V
= 4.75V
= 4.75V
V
V
− 1.5
CC
V
V
IN(1)
IN(0)
CC
CC
0.8
CMOS TO TTL
V
Logical “1” Input Voltage
MM74C901
IN(1)
V
V
= 4.75V
= 4.75V
4.25
− 1.5
V
V
CC
CC
MM74C902
CC
V
Logical “0” Input Voltage
MM74C901
IN(0)
V
V
V
= 4.75V
= 4.75V
1.0
1.5
V
V
V
CC
CC
CC
MM74C902
V
V
Logical “1” Output Voltage
Logical “0” Output Voltage
MM74C901
= 4.75V, I = −800 µA
2.4
OUT(1)
OUT(0)
O
V
V
= 4.75V, I = 2.6 mA
0.4
0.4
V
V
CC
CC
O
MM74C902
= 4.75V, I = 3.2 mA
O
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
(MM74C901)
I
I
I
I
Output Source Current
(P-Channel)
V
T
V
T
V
T
V
T
= 5.0V, V = 0V
OUT
−5.0
−20
9.0
mA
mA
mA
mA
SOURCE
SOURCE
SINK
CC
= 25°C, V = 0V
A
IN
Output Source Current
(P-Channel)
= 10V, V
= 0V
OUT
CC
= 25°C, V = 0V
A
IN
Output Sink Current
(N-Channel)
= 5.0V, V
= V
OUT CC
CC
= 25°C, V = V
CC
A
IN
Output Sink Current
(N-Channel)
= 5.0V, V = 0.4V
OUT
3.8
SINK
CC
= 25°C, V = V
CC
A
IN
(MM74C902)
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2
DC Electrical Characteristics (Continued)
Symbol
Parameter
Output Source Current
Conditions
= 5.0V, V = 0V
Min
Typ
Max
Units
I
I
I
I
V
T
V
T
V
T
V
T
−5.0
mA
SOURCE
CC
OUT
(P-Channel)
= 25°C, V = V
IN CC
A
Output Source Current
(P-Channel)
= 10V, V = 0V
OUT
−20
9.0
3.8
mA
mA
mA
SOURCE
SINK
CC
= 25°C, V = V
CC
A
IN
Output Sink Current
(N-Channel)
= 5.0V, V
= V
OUT CC
CC
= 25°C, V = 0V
A
IN
Output Sink Current
(N-Channel)
= 5.0V, V
= 0.4V
OUT
SINK
CC
= 25°C, V = 0V
A
IN
AC Electrical Characteristics (Note 2)
T
A = 25°C, CL = 50 pF, unless otherwise noted
Symbol Parameter
MM74C901
Conditions
Min
Typ
Max
Units
t
Propagation Delay Time
to a Logical “1”
V
V
V
V
= 5.0V
= 10V
= 5.0V
= 10V
38
22
21
13
14
30
70
30
35
20
ns
ns
ns
ns
pF
pF
pd1
CC
CC
CC
CC
t
Propagation Delay Time
to a Logical “0”
pd0
C
C
Input Capacitance
Any Input (Note 3)
Per Buffer (Note 4)
IN
Power Dissipation Capacity
PD
MM74C902
t
t
Propagation Delay Time
V
V
V
V
= 5.0V
= 10V
= 5.0V
= 10V
57
27
54
25
5.0
50
90
40
90
40
ns
ns
ns
ns
pF
pF
pd1
pd0
CC
CC
CC
CC
to a Logical “1”
Propagation Delay Time
to a Logical “0”
C
C
Input Capacitance
Power Dissipation Capacity
Any Input (Note 3)
Per Buffer (Note 4)
IN
PD
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note
PD
AN-90.
Typical Application
CMOS to TTL or CMOS at a Lower VCC
Note: V
= V
CC2
CC1
3
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AC Test Circuit and Switching Time Waveforms
CMOS to CMOS
Note: Delays measured with input t , t = 20 ns.
r
f
Typical Performance Characteristics
Typical Propagation Delay to a Logical “0” for the
MM74C901
Typical Propagation Delay to a Logical “1” for the
MM74C901
Typical Propagation Delay to a Logical “0” for the
MM74C902
Typical Propagation Delay to a Logical “1” for the
MM74C902
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-120, 0.150” Narrow
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
MM74C902MX
Buffer, CMOS Series, 6-Func, 1-Input, CMOS, PDSO14, 0.150 INCH, MS-120, SOIC-14
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