LV8571AN [NSC]
IC 2 TIMER(S), REAL TIME CLOCK, PDIP24, 0.300 INCH, PLASTIC, DIP-24, Timer or RTC;型号: | LV8571AN |
厂家: | National Semiconductor |
描述: | IC 2 TIMER(S), REAL TIME CLOCK, PDIP24, 0.300 INCH, PLASTIC, DIP-24, Timer or RTC 时钟 双倍数据速率 光电二极管 外围集成电路 |
文件: | 总24页 (文件大小:350K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
March 1993
LV8571A Low Voltage Timer Clock Peripheral (TCP)
General Description
The LV8571A is intended for use in microprocessor based
systems where information is required for multi-tasking, data
logging or general time of day/date information. This device
is implemented in low voltage silicon gate microCMOS tech-
nology to provide low standby power in battery back-up en-
vironments. The circuit’s architecture is such that it looks
like a contiguous block of memory or I/O ports. The address
space is organized as 2 software selectable pages of 32
bytes. This includes the Control Registers, the Clock Coun-
ters, the Alarm Compare RAM, the Timers and their data
RAM, and the Time Save RAM. Any of the RAM locations
that are not being used for their intended purpose may be
used as general purpose CMOS RAM.
interrupt, and lock out the mp interface. The time power fails
l
Additionally, two supply pins are provided. When
may be logged into RAM automatically when V
BB
V
V
.
CC
BB
, internal circuitry will automatically switch from the
l
V
CC
main supply to the battery supply. Status bits are provided
to indicate initial application of battery power, system power,
and low battery detect.
(Continued)
Features
Y
g
3.3V 10% supply
Y
Full function real time clock/calendar
Ð 12/24 hour mode timekeeping
Ð Day of week and day of years counters
Ð Four selectable oscillator frequencies
Ð Parallel resonant oscillator
Two 16-bit timers
Ð 10 MHz external clock frequency
Ð Programmable multi-function output
Ð Flexible re-trigger facilities
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week, day of month and day of year counters are
provided. Time is controlled by an on-chip crystal oscillator
requiring only the addition of the crystal and two capacitors.
The choice of crystal frequency is program selectable.
Y
Y
Y
Two independent multifunction 10 MHz 16-bit timers are
provided. These timers operate in four modes. Each has its
own prescaler and can select any of 7 possible clock inputs.
Thus, by programming the input clocks and the timer coun-
ter values a very wide range of timing durations can be
achieved. The range is from about 400 ns (4.915 MHz oscil-
lator) to 65,535 seconds (18 hrs., 12 min.).
Power fail features
Ð Internal power supply switch to external battery
Ð Power Supply Bus glitch protection
Ð Automatic log of time into RAM at power failure
On-chip interrupt structure
Ð Periodic, alarm, timer and power fail interrupts
Up to 44 bytes of CMOS RAM
Y
Y
Power failure logic and control functions have been integrat-
ed on chip. This logic is used by the TCP to issue a power fail
INTR/MFO pins programmable High/Low and push-pull
or open drain
Block Diagram
TL/F/11416–1
FIGURE 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/11416
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
Operation Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Min
3.0
Max
3.6
Unit
V
Supply Voltage (V ) (Note 3)
CC
b
Supply Voltage (V ) (Note 3)
BB
2.2
0.0
V
0.4
V
CC
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
DC Input or Output Voltage
(V , V )
IN OUT
V
V
CC
b
a
DC Input Voltage (V
)
0.5V to V
0.5V
0.5V
IN
CC
CC
b
a
85
Operation Temperature (T )
A
40
C
§
kV
b
0.5V to V
a
DC Output Voltage (V
)
OUT
Electr-Static Discharge Rating
Typical Values
1
b
a
65 C to 150 C
Storage Temperature Range
Power Dissipation (PD)
§
§
500 mW
i
DIP
Board
Socket
59 C/W
§
JA
Lead Temperature (Soldering, 10 sec.)
260 C
§
65 C/W
§
i
PLCC
Board
Socket
77 C/W
§
JA
85 C/W
§
DC Electrical Characteristics
l
e
e
e
g
3.3V 10%, V
V
CC
2.5V, V
V , C
IH L
100 pF (unless otherwise specified)
Conditions Min
BB
PFAIL
Symbol
Parameter
Max
Units
a
V
V
V
V
High Level Input Voltage
(Note 4)
Any Inputs Except OSC IN,
OSC IN with External Clock
2.0
b
V
CC
0.3
V
V
IH
V
0.2
BB
b
b
Low Level Input Voltage
All Inputs Except OSC IN
OSC IN with External Clock
0.3
0.3
0.8
0.2
V
V
IL
e b
e b
b
0.2
High Level Output Voltage
(Excluding OSC OUT)
I
I
20 mA
2.0 mA
V
V
V
OH
OL
OUT
OUT
CC
2.4
e
e
Low Level Output Voltage
(Excluding OSC OUT)
I
I
20 mA
2.0 mA
0.2
0.3
V
V
OUT
OUT
e
g
I
I
I
Input Current (Except OSC IN)
V
V
V
V
or GND
0.7
mA
mA
IN
IN
CC
e
e
g
Output TRI-STATE Current
É
Output High Leakage Current
MFO, INTR Pins
V
or GND
1
1
OZ
OUT
CC
V
CC
or GND
LKG
OUT
g
mA
Outputs Open Drain
e
V
V
I
Quiescent Supply Current
(Note 7)
F
32.768 kHz
CC
OSC
e
e
e
V
V
V
or GND (Note 5)
or GND (Note 6)
220
700
8
mA
mA
mA
IN
IN
IN
CC
CC
V
IH
or V (Note 6)
IL
e
F
4.194304 MHz or
4.9152 MHz
or GND (Note 6)
OSC
e
e
V
V
V
V
6
8
mA
mA
IN
IN
CC
or V (Note 6)
IH
IL
e
GND
I
I
Quiescent Supply Current
(Single Supply Mode)
(Note 7)
V
V
F
F
CC
BB
BB
IN
e
V
or GND
32.768 kHz
4.9152 MHz or
4.194304 MHz
CC
e
e
60
6
mA
mA
OSC
OSC
e
GND
Standby Mode Battery
Supply Current
(Note 8)
V
CC
e
e
OSC OUT
other pins
open circuit,
GND
e
e
F
OSC
F
OSC
32.768 kHz
4.9152 MHz or
4.194304 MHz
8
400
mA
mA
s
s
2.6V
I
Battery, Supply Leakage
2.2V
other pins at GND
V
BLK
BB
e
e
e
e
V
CC
V
CC
GND, V
3.6V, V
2.6V
2.2V
0.8
mA
mA
BB
BB
b
0.8
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
s
e
e
pin) 3.0V
b
V 0.4V. Single Supply Mode: Data retention voltage is
CC
Note 3: For F
4.194304 or 4.9152 MHz, V minimum
BB
2.8V. In battery backed mode, V
BB
OSC
s
s
2.2V min. In single Supply Mode (Power connected to V
CC
V
CC
3.6V.
Note 4: This parameter (V ) is not tested on all pins at the same time.
IH
Note 5: This specification tests I
with all power fail circuitry disabled, by setting D7 of Interrupt Control Register 1 to 0.
CC
Note 6: This specification tests I
with all power fail circuitry enabled, by setting D7 of Interrupt Control Register 1 to 1.
CC
Note 7: This specification is tested with both the timers and OSC IN driven by a signal generator. Contents of the Test Register
e
00(H), the MFO pin is not
configured as buffered oscillator out and MFO, INTR, are configured as open drain.
e
Note 8: This specification is tested with both the timers off, and only OSC IN is driven by a signal generator. Contents of the Test Register
00(H) and the MFO
pin is not configured as buffered oscillator out.
2
AC Electrical Characteristics
l
e
e
e
V , C 100 pF (unless otherwise specified)
IH L
g
3.3V 10%, V
V
CC
2.5V, V
BB
PFAIL
Symbol
READ TIMING
Parameter
Min
Max
Units
t
t
t
t
t
t
t
t
Address Valid Prior to Read Strobe
Read Strobe Width (Note 9)
10
ns
ns
ns
ns
ns
ns
ns
ns
AR
100
RW
CD
Chip Select to Data Valid Time
Address Hold after Read (Note 10)
Read Strobe to Valid Data
100
2
RAH
RD
90
80
Read or Chip Select to TRI-STATE
DZ
Chip Select Hold after Read Strobe (Note 10)
0
RCH
DS
Minimum Inactive Time between Read or Write Accesses
70
WRITE TIMING
t
t
t
t
t
t
t
Address Valid before Write Strobe
Address Hold after Write Strobe (Note 10)
Chip Select to End of Write Strobe
Write Strobe Width (Note 11)
10
2
ns
ns
ns
ns
ns
ns
ns
AW
WAH
CW
110
100
70
2
WW
DW
Data Valid to End of Write Strobe
Data Hold after Write Strobe (Note 10)
Chip Select Hold after Write Strobe (Note 10)
WDH
WCH
0
INTERRUPT TIMING
t
Clock rollover to INTR out is typically 20 ms
ROLL
Note 9: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 10: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 11: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
GND to 3.0V
6 ns (10%–90%)
1.3V
Reference Levels
a
Active High 0.5V
b
Active Low 0.5V
TRI-STATE Reference
Levels (Note 13)
e
Note 12: C
100 pF, includes jig and scope capacitance.
L
e
e
e
Note 13: S1
V
for active low to high impedance measurements.
CC
S1
S1
GND for active high to high impedance measurements.
open for all other timing measurements.
e
e
1 MHz)
Capacitance (T
25 C, f
§
A
TL/F/11416–2
Parameter
(Note 14)
Symbol
Typ
Units
C
C
Input Capacitance
5
7
pF
pF
IN
Output Capacitance
OUT
Note 14: This parameter is not 100% tested.
Note 15: Output rise and fall times 25 ns max (10%–90%) with 100 pF load.
3
Timing Waveforms
Read Timing Diagram
TL/F/11416–3
Write Timing Diagram
TL/F/11416–4
4
PFAIL (Input): In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
General Description (Continued)
The LV8571A’s interrupt structure provides four basic types
of interrupts: Periodic, Alarm/Compare, Timer, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
e
logic. When PFAIL
logic 0 the TCP goes into a lockout
mode, in a minimum of 30 ms or a maximum of 63 ms unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
One dedicated general purpose interrupt output is provided.
A second interrupt output is available on the Multiple Func-
tion Output (MFO) pin. Each of these may be selected to
generate an interrupt from any source. Additionally, the
MFO pin may be programmed to be either as oscillator out-
put or Timer 0’s output.
to V . Refer to section on Power Fail Functional Descrip-
CC
tion.
V
(Battery Power Pin): This pin is connected to a back-
BB
up power supply. This power supply is switched to the inter-
nal circuitry when the V becomes lower than V . Utiliz-
CC BB
ing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the TCP pro-
grammed for single power supply only, and power applied to
Pin Description
CS, RD, WR (Inputs): These pins interface to mP control
lines. The CS pin is an active low enable for the read and
write operations. Read and Write pins are also active low
and enable reading or writing to the TCP. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to com-
plete its cycle.
the V
pin.
CC
V
: This is the main system power pin.
CC
GND: This is the common ground power pin for both V
.
BB
and V
CC
Connection Diagram
A0–A4 (Inputs): These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
Dual-In-Line
OSC IN (Input): OSC OUT (Output): These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to V and V , and the correct crystal select bits in
BB CC
the Real Time Mode Register have been set.
MFO (Output): The multi-function output can be used as a
second interrupt output for interrupting the mP. This pin can
also provide an output for the oscillator or the internal Timer
0. The MFO output can be programmed active high or low,
open drain or push-pull. If in battery backed mode and a
pull-up resistor is attached, it should be connected to a volt-
age no greater than V . This pin is configured open drain
BB
l
during battery operation (V
V ).
CC
BB
INTR (Output): The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
output can be programmed active high or low, push-pull or
open drain. If in battery backed mode and a pull-up resistor
is attached, it should be connected to a voltage no greater
TL/F/11416–5
Top View
Order Number LV8571AN
See NS Package Number N24C
than V . This pin is configured open drain during battery
BB
l
operation (V
BB
V ).
CC
D0–D7 (Input/Output): These 8 bidirectional pins connect
to the host mP’s data bus and are used to read from and
write to the TCP. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
5
Functional Description
The LV8571A contains a fast access real time clock, two 10
MHz 16-bit timers, interrupt control logic, power fail detect
logic, and CMOS RAM. All functions of the TCP are con-
trolled by a set of nine registers. A simplified block diagram
that shows the major functional blocks is given in Figure 1.
The memory map of the TCP is shown in the memory ad-
dressing table. The memory map consists of two 31 byte
pages with a main status register that is common to both
pages. A control bit in the Main Status Register is used to
select either page. Figure
2 shows the basic concept.
Page 0 contains all the clock timer functions, while page 1
has scratch pad RAM. The control registers are split into
two separate blocks to allow page 1 to be used entirely as
scratch pad RAM. Again a control bit in the Main Status
Register is used to select either control register block.
The blocks are described in the following sections:
1. Real Time Clock
2. Oscillator Prescaler
3. Interrupt Logic
4. Power Failure Logic
5. Additional Supply Management
6. Timers
TL/F/11416–6
FIGURE 2. LV8571A Internal Memory Map
6
Functional Description (Continued)
INITIAL POWER-ON of BOTH V and V
BB CC
Save Enable bit (D7) of the Interrupt Routing Register, and
then to write a zero. Writing a one into this bit will enable the
clock contents to be duplicated in the Time Save RAM.
Changing the bit from a one to a zero will freeze and store
the contents of the clock in Time Save RAM. The time then
can be read without concern for clock rollover, since inter-
nal logic takes care of synchronization of the clock. Be-
cause only the bits used by the clock counters will be
latched, the Time Save RAM should be cleared prior to use
to ensure that random data stored in the unused bits do not
confuse the host microprocessor. This bit can also provide
time save at power failure, see the Additional Supply Man-
agement Functions section. With the Time Save Enable bit
at a logical 0, the Time Save RAM may be used as RAM if
the latched read function is not necessary.
V
and V
may be applied in any sequence. In order for
CC
BB
the power fail circuitry to function correctly, whenever power
is off, the V pin must see a path to ground through a
CC
maximum of 1 MX. The user should be aware that the con-
trol registers will contain random data. The first task to be
carried out in an initialization routine is to start the oscillator
by writing to the crystal select bits in the Real Time Mode
Register. If the LV8571A is configured for single supply
mode, an extra 50 mA may be consumed until the crystal
select bits are programmed. The user should also ensure
that the TCP is not in test mode (see register descriptions).
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
As shown in Figure 2, the clock has 10 bytes of counters,
which count from 1/100 of a second to years. Each counter
counts in BCD and is synchronously clocked. The count se-
quence of the individual byte counters within the clock is
shown later in Table VII. Note that the day of week, day of
month, day of year, and month counters all roll over to 1.
The hours counter in 12 hour mode rolls over to 1 and the
AM/PM bit toggles when the hours rolls over to 12
INITIALIZING AND WRITING TO THE
CALENDAR-CLOCK
Upon initial application of power to the TCP or when making
time corrections, the time must be written into the clock. To
correctly write the time to the counters, the clock would
normally be stopped by writing the Start/Stop bit in the Real
Time Mode Register to a zero. This stops the clock from
counting and disables the carry circuitry. When initializing
the clock’s Real Time Mode Register, it is recommended
that first the various mode bits be written while maintaining
the Start/Stop bit reset, and then writing to the register a
second time with the Start/Stop bit set.
e
counter.
e
1). The AM/PM bit is bit D7 in the hours
(AM
0, PM
All other counters roll over to 0. Also note that the day of
year counter is 12 bits long and occupies two addresses.
Upon initial application of power the counters will contain
random information.
The above method is useful when the entire clock is being
corrected. If one location is being updated the clock need
not be stopped since this will reset the prescaler, and time
will be lost. An ideal example of this is correcting the hours
for daylight savings time. To write to the clock ‘‘on the fly’’
the best method is to wait for the 1/100 of a second period-
ic interrupt. Then wait an additional 16 ms, and then write
the data to the clock.
READING THE CLOCK: VALIDATED READ
Since clocking of the counter occurs asynchronously to
reading of the counter, it is possible to read the counter
while it is being incremented (rollover). This may result in an
incorrect time reading. Thus to ensure a correct reading of
the entire contents of the clock (or that part of interest), it
must be read without a clock rollover occurring. In general
this can be done by checking a rollover bit. On this chip the
periodic interrupt status bits can serve this function. The
following program steps can be used to accomplish this.
PRESCALER/OSCILLATOR FUNCTIONAL
DESCRIPTION
Feeding the counter chain is a programmable prescaler
which divides the crystal oscillator frequency to 32 kHz and
further to 100 Hz for the counter chain (see Figure 3 ). The
crystal frequency that can be selected are: 32 kHz, 32.768
kHz, 4.9152 MHz, and 4.194304 MHz.
1. Initialize program for reading clock.
2. Dummy read of periodic status bit to clear it.
3. Read counter bytes and store.
4. Read rollover bit, and test it.
5. If rollover occured go to 3.
Once 32 kHz is generated it feeds both timers and the
clock. The clock and timer prescalers can be independently
enabled by controlling the timer or clock Start/Stop bits.
6. If no rollover, done.
To detect the rollover, individual periodic status bits can be
polled. The periodic bit chosen should be equal to the high-
est frequency counter register to be read. That is if only
SECONDS through HOURS counters are read, then the
SECONDS periodic bit should be used.
READING THE CLOCK: INTERRUPT DRIVEN
Enabling the periodic interrupt mask bits cause interrupts
just as the clock rolls over. Enabling the desired update rate
and providing an interrupt service routine that executes in
less than 10 ms enables clock reading without checking for
a rollover.
READING THE CLOCK: LATCHED READ
TL/F/11416–7
Another method to read the clock that does not require
checking the rollover bit is to write a one into the Time
FIGURE 3. Programmable Clock Prescaler Block
7
Functional Description (Continued)
The oscillator is programmed via the Real Time Mode Reg-
ister to operate at various frequencies. The crystal oscillator
is designed to offer optimum performance at each frequen-
cy. Thus, at 32.768 kHz the oscillator is configured as a low
frequency and low power oscillator. At the higher frequen-
cies the oscillator inverter is reconfigured. In addition to the
inverter, the oscillator feedback bias resistor is included on
chip, as shown in Figure 4. The oscillator input may be driv-
en from an external source if desired. Refer to test mode
application note for details. The oscillator stability is en-
hanced through the use of an on chip regulated power sup-
ply.
The interrupts are enabled by writing a one to the appropri-
ate bits in Interrupt Control Register 0 and/or 1. Any of the
interrupts can be routed to either the INTR pin or the MFO
pin, depending on how the Interrupt Routing register is pro-
grammed. This, for example, enables the user to dedicate
the MFO as a non-maskable interrupt pin to the CPU for
power failure detection and enable all other interrupts to
appear on the INTR pin. The polarity for the active interrupt
can be programmed in the Output Mode Register for either
active high or low, and open drain or push pull outputs.
TABLE I. Registers that are Applicable
to Interrupt Control
The typical range of trimmer capacitor (as shown in Oscilla-
tor Circuit DiagramFigure 4, and in the typical application) at
the oscillator input pin is suggested only to allow accurate
tuning of the oscillator. This range is based on a typical
printed circuit board layout and may have to be changed
depending on the parasitic capacitance of the printed circuit
board or fixture being used. In all cases, the load capaci-
tance specified by the crystal manufacturer (nominal value
11 pF for the 32.768 crystal) is what determines proper os-
cillation. This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground).
Register
Select
Page
Register Name
Address
Select
Main Status Register
Periodic Flag Register
Interrupt Routing
Register
X
0
X
0
00H
03H
0
1
1
1
0
0
0
0
04H
03H
04H
02H
Interrupt Control
Register 0
Interrupt Control
Register 1
Output Mode
Register
The Interrupt Status Flag D0, in the Main Status Register,
indicates the state of INTR and MFO outputs. It is set when
either output becomes active and is cleared when all TCP
interrupts have been cleared and no further interrupts are
pending (i.e., both INTR and MFO are returned to their inac-
tive state). This flag enables the TCP to be rapidly polled by
the mP to determine the source of an interrupt in a wiredÐ
OR interrupt system.
Note that the Interrupt Status Flag will only monitor the state
of the MFO output if it has been configured as an interrupt
output (see Output Mode Register description). This is true,
regardless of the state of the Interrupt Routing Register.
Thus the Interrupt Status Flag provides a true reflection of
all conditions routed to the external pins.
Status for the interrupts are provided by the Main Status
Register and the Periodic Flag Register. Bits D1–D5 of the
Main Status Register are the main interrupt bits.
TL/F/11416–8
These register bits will be set when their associated timing
events occur. Enabled Alarm or Timer interrupts that occur
will set its Main Status Register bit to a one. However, an
external interrupt will only be generated if the appropriate
Alarm or Timer interrupt enable bits are set (see Figure 5 ).
FIGURE 4. Oscillator Circuit Diagram
R
OUT
XTAL
C
o
C
t
(Switched
Internally)
Disabling the periodic bits will mask the Main Status Regis-
ter periodic bit, but not the Periodic Flag Register bits. The
Power Fail Interrupt bit is set when the interrupt is enabled
and a power fail event has occurred, and is not reset until
the power is restored. If all interrupt enable bits are 0 no
interrupt will be asserted. However, status still can be read
from the Main Status Register in a polled fashion (see Fig-
ure 5 ).
32/32.768 kHz 47 pF 2 pF–22 pF 150 kX to 350 kX
4.194304 MHz 68 pF 0 pF–80 pF 500X to 900X
4.9152 MHz
68 pF 29 pF–49 pF 500X to 900X
INTERRUPT LOGIC FUNCTIONAL DESCRIPTION
The TCP has the ability to coordinate processor timing ac-
tivities. To enhance this, an interrupt structure has been im-
plemented which enables several types of events to cause
interrupts. Interrupts are controlled via two Control Regis-
ters in block 1 and two Status Registers in block 0. (See
Register Description for notes on paging and also Figure 5
and Table I.)
To clear a flag in bits D2–D5 of the Main Status Register a 1
must be written back into the bit location that is to be
cleared. For the Periodic Flag Register reading the status
will reset all the periodic flags.
8
Functional Description (Continued)
Interrupts Fall Into Four Categories:
To generate periodic interrupts at the desired rate, the asso-
ciated Periodic Interrupt Enable bit in Interrupt Control Reg-
ister 0 must be set. Any combination of periodic interrupts
may be enabled to operate simultaneously. Enabled period-
ic interrupts will now affect the Periodic Interrupt Flag in the
Main Status Register. The Periodic Route bit in the Interrupt
Routing Register is used to route the periodic interrupt
events to either the INTR output or the MFO output.
1. The Timer Interrupts: For description see Timer Section.
2. The Alarm Compare Interrupt: Issued when the value in
the time compared RAM equals the counter.
3. The Periodic Interrupts: These are issued at every incre-
ment of the specific clock counter signal. Thus, an inter-
rupt is issued every minute, second, etc. Each of these
interrupts occurs at the roll-over of the specific counter.
When a periodic event occurs, the Periodic Interrupt Flag in
the Main Status Register is set, causing an interrupt to be
generated. The mP clears both flag and interrupt by writing a
‘‘1’’ to the Periodic Interrupt Flag. The individual flags in the
periodic Interrupt Flag Register do not require clearing to
cancel the interrupt.
4. The Power Fail Interrupt: Issued upon recognition of a
power fail condition by the internal sensing logic. The
power failed condition is determined by the signal on the
PFAIL pin. The internal power fail signal is gated with the
chip select signal to ensure that the power fail interrupt
does not lock the chip out during a read or write.
If all periodic interrupts are disabled and a periodic interrupt
is left pending (i.e., the Periodic Interrupt Flag is still set), the
Periodic Interrupt Flag will still be required to be cleared to
cancel the pending interrupt.
ALARM COMPARE INTERRUPT DESCRIPTON
The alarm/time comparison interrupt is a special interrupt
similar to an alarm clock wake up buzzer. This interrupt is
generated when the clock time is equal to a value pro-
grammed into the alarm compare registers. Up to six bytes
can be enabled to perform alarm time comparisons on the
counter chain. These six bytes, or some subset thereof,
would be loaded with the future time at which the interrupt
will occur. Next, the appropriate bits in the Interrupt Control
Register 1 are enabled or disabled (refer to detailed descrip-
tion of Interrupt Control Register 1). The TCP then com-
pares these bytes with the clock time. When all the enabled
compare registers equal the clock time an alarm interrupt is
issued, but only if the alarm compare interrupt is enabled
can the interrupt be generated externally. Each alarm com-
pare bit in the Control Register will enable a specific byte for
comparison to the clock. Disabling a compare byte is the
same as setting its associated counter comparator to an
‘‘always equal’’ state. For example, to generate an interrupt
at 3:15 AM of every day, load the hours compare with 0 3
(BCD), the minutes compare with 1 5 (BCD) and the faster
counters with 0 0 (BCD), and then disable all other compare
registers. So every day when the time rolls over from
3:14:59.99, an interrupt is issued. This bit may be reset by
writing a one to bit D3 in the Main Status Register at any
time after the alarm has been generated.
POWER FAIL INTERRUPTS DESCRIPTION
The Power Fail Status Flag in the Main Status Register
monitors the state of the internal power fail signal. This flag
may be interrogated by the mP, but it cannot be cleared; it is
cleared automatically by the TCP when system power is
restored. To generate an interrupt when the power fails, the
Power Fail Interrupt Enable bit in Interrupt Control Register
1 is set.
The Power Fail Route bit determines which output the inter-
rupt will appear on. Although this interrupt may not be
cleared, it may be masked by clearing the Power Fail Inter-
rupt Enable bit.
POWER FAILURE CIRCUITRY FUNCTIONAL
DESCRIPTION
Since the clock must be operated from a battery when the
main system supply has been turned off, the LV8571A pro-
vides circuitry to simplify design in battery backed systems.
This circuitry switches over to the back up supply, and iso-
lates the LV8571A from the host system. Figure 6 shows a
simplified block diagram of this circuitry, which consists of
three major sections; 1) power loss logic: 2) battery switch
over logic: and 3) isolation logic.
If time comparison for an individual byte counter is disabled,
that corresponding RAM location can then be used as gen-
eral purpose storage.
Detection of power loss occurs when PFAIL is low. De-
bounce logic provides a 30 ms–63 ms debounce time, which
will prevent noise on the PFAIL pin from being interpreted
as a system failure. After 30 ms–63 ms the debounce logic
times out and a signal is generated indicating that system
power is marginal and is failing. The Power Fail Interrupt will
then be generated.
PERIODIC INTERRUPTS DESCRIPTION
The Periodic Flag Register contains six flags which are set
by real-time generated ‘‘ticks’’ at various time intervals, see
Figure 5. These flags constantly sense the periodic signals
and may be used whether or not interrupts are enabled.
These flags are cleared by any read or write operation per-
formed on this register.
9
Functional Description (Continued)
10
Functional Description (Continued)
TL/F/11416–10
FIGURE 6. System-Battery Switchover (Upper Left), Power Fail
and Lock-Out Circuits (Lower Right)
The user may choose to have this power failed signal lock-
out the TCP’s data bus within 30 ms min/63 ms max or to
delay the lock-out to enable mP access after power failure is
detected. This delay is enabled by setting the delay enable
bit in the Routing Register. Also, if the lock-out delay was
not enabled the TCP will disconnect itself from the bus with-
After the generation of
a
lock-out signal, and eventual
switch in of the battery supply, the pins of the TCP will be
configured as shown in Table II. Outputs that have a pull-up
resistor should be connected to a voltage no greater than
V
BB
.
TABLE II. Pin Isolation during a Power Failure
in 30 ms min
x
63 ms max. If chip select is low when a
power failure is detected, a safety circuit will ensure that if a
read or write is held active continuously for greater than
30 ms after the power fail signal is asserted, the lock-out will
be forced. If a lock-out delay is enabled, the LV8571A will
remain active for 480 ms after power fail is detected. This
will enable the mP to perform last minute bookkeeping be-
fore total system collapse. When the host CPU is finished
accessing the TCP it may force the bus lock-out before
480 ms has elapsed by resetting the delay enable bit.
e
PFAIL
Standby Mode
Pin
l
V
CC
Logic 0
V
BB
CS, RD, WR
A0–A4
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Open Drain
D0–D7
Oscillator
PFAIL
INTR, MFO
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares V to the
voltage. As the main supply fails, the TCP will continue
The Timer and Interrupt Power Fail Operation bits in the
Real-Time Mode Register determine whether or not the tim-
ers and interrupts will continue to function after a power fail
event.
CC
V
BB
to operate from the V
pin until V
falls below the V
BB
CC
CC
voltage. At this time, the battery supply is switched in, V is
CC
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
As power returns to the system, the battery switch over cir-
power as soon as it becomes
cuit will switch back to V
CC
greater than the battery voltage. The chip will remain in the
to be avoided, then the voltage at the V pin must not be
CC
allowed to equal the voltage at the V pin.
BB
e
e
1
locked out state as long as PFAIL
0. When PFAIL
11
Functional Description (Continued)
the chip is unlocked, but only after another 30 ms min
63 ms max debounce time. The system designer must en-
sure that his system is stable when power has returned.
x
binary down counter and associated control. The operation
is similar to existing mP peripheral timers except that several
features have been enhanced. The timers can operate in
four modes, and in addition, the input clock frequency can
be selected from a prescaler over a wide range of frequen-
cies. Furthermore, these timers are capable of generating
interrupts and the Timer 0 output signal is available as a
hardware output via the MFO pin. Timer 1 output, however,
is not available as a hardware output signal. Both the inter-
rupt and MFO outputs are fully programmable active high, or
low, open drain, or push-pull.
The power fail circuitry contains active linear circuitry that
draws supply current from V . In some cases this may be
CC
undesirable, so this circuit can be disabled by masking the
power fail interrupt. The power fail input can perform all
lock-out functions previously mentioned, except that no ex-
ternal interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using V
standby mode.
in
BB
Figure 7 shows the functional block diagram of one of the
timers. The timer consists of a 16-bit counter, two 8-bit input
registers, two 8-bit output registers, clock prescaler, mode
control logic, and output control logic. The timer and the
data registers are organized as two bytes for each timer.
Under normal operations a read/write to the timer locations
will read or write to the data input register. The timer con-
tents can be read by setting the counter Read bit (RD) in the
timer control register.
LOW BATTERY, INITIAL POWER ON DETECT, AND
POWER FAIL TIME SAVE
There are three other functions provided on the LV8571A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time keeping
failure detect, a low battery detect circuit, and a time save
on power failure.
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
TIMER INITIALIZATION
The timer’s operation is controlled by a set of registers, as
listed in Table III. These consist of 2 data input registers and
one control register per timer. The data input registers con-
tain the timers count down value. The Timer Control Regis-
ter is used to set up the mode of operation and the input
clock rate. The timer related interrupts can be controlled by
programming the Interrupt Routing Register and Interrupt
Control Register 0. The timer outputs are configured by the
Output Mode Register.
The Oscillator Fail flag will not be reset until the real-time
clock is started. This allows the system to discriminate be-
tween an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit D6 of the
Periodic Flag Register must be written low. This will not af-
fect the contents of the Oscillator Fail Flag.
Another status bit is the low battery detect. This bit is set
only when the clock is operating under the V
pin, and
CC
when the battery voltage is determined to be less than 2.1V
(typical). When the power fail interrupt enable bit is low, it
disables the power fail circuit and will also shut off the low
battery voltage detection circuit as well.
TABLE III. Timer Associated Registers
Register Page
Register Name
Address
Select
Select
Timer 0 Data MSB
X
X
0
X
X
0
0
1
1
0
0
0
0
0
0
0
0
0
10H
0FH
01H
12H
11H
02H
04H
03H
02H
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatical-
ly. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it will auto-
matically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a
software write or power fail write.
Timer 0 Data LSB
Timer 0 Control Register
Timer 1 Data MSB
Timer 1 Data LSB
Timer 1 Control Register
Interrupt Routing Register
Interrupt Control Reg. 0
Output Mode Register
All these registers must be initialized prior to starting the
timer(s). The Timer Control Register should first be set to
select the timer mode with the timer start/stop bit reset.
Then when the timer is to be started the control register
should be rewritten identically but with the start/stop bit set.
SINGLE POWER SUPPLY APPLICATIONS
The LV8571A can be used in a single power supply applica-
pin must be connected to
tion. To achieve this, the V
BB
ground, and the power connected to V
and PFAIL pins.
CC
The Oscillator Failed/Single Supply bit in the Periodic Flag
Register should be set to a logic 1, which will disable the
oscillator battery reference circuit. The power fail interrupt
should also be disabled. This will turn off the linear power
fail detection circuits, and will eliminate any quiescent power
drawn through these circuits. Until the crystal select bits are
initialized, the LV8571A may consume about 50 mA due to
arbitrary oscillator selection at power on.
TIMER OPERATION
Each timer is capable of operation in one of four modes. As
mentioned, these modes are programmed in each timer’s
Control Register which is described later. All four modes
operate in a similar manner. They operate on the two 8-bit
data words stored into the Data Input Register. At the begin-
ning of a counting cycle the 2 bytes are loaded into the timer
and the timer commences counting down towards zero. The
exact action taken when zero is reached depends on the
mode selected, but in general, the timer output will change
state, and an interrupt will be generated if the timer inter-
rupts are unmasked.
(This extra 50 mA is not consumed if the battery backed
mode is selected).
TIMER FUNCTIONAL DESCRIPTION
The LV8571A contains 2 independent multi-mode timers.
Each timer is composed of a 16-bit negative edge triggered
12
Functional Description (Continued)
INPUT CLOCK SELECTION
er causes the same synchronization error that starting the
timer does. The range of errors is specified in Table V.
The input frequency to the timers may be selected. Each
timer has a prescaler that gives a wide selection of clocking
rates. Table IV shows the range of programmable clocks
available and the corresponding setting in the Timer Control
Register. Note that the output of Timer 1 may be used as
the input to Timer 0. This is a cascade option for the timers
and allows them to be clocked as a 32-bit down counter.
TABLE V. Maximum Synchronization Errors
Clock Selected
Error
a
a
a
a
a
a
a
a
External
Crystal
Crystal/4
10.7 kHz
1 kHz
Ext. Clock Period
1 Crystal Clock Period
1 Crystal Clock Period
32 ms
TABLE IV. Programmable Timer Input Clocks
32 ms
C2
C1
C0
Selected Clock
100 Hz
10 Hz
32 ms
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Timer 1 Output
32 ms
Crystal Oscillator
(Crystal Oscillator)/4
93.5 ms (10.7 kHz)
1 ms (1 kHz)
1 Hz
32 ms
MODES OF OPERATION
Bits M0 and M1 in the Timer Control Registers are used to
specify the modes of operation. The mode selection is de-
scribed in Table VI.
10 ms (100 Hz)
1/10 Second (10 Hz)
1 Second (1 Hz)
TABLE VI. Programmable Timer Modes of Operation
Note that the second and third selections are not fixed fre-
quencies, but depend on the crystal oscillator frequency
chosen.
M1
M0
Function
Modes
0
0
1
1
0
1
0
1
Single Pulse Generator
Rate Generator, Pulse Output
Square Wave Output
Mode 0
Mode 1
Mode 2
Mode 3
Since the input clock frequencies are usually running asyn-
chronously to the timer Start/Stop control bit, a 1 clock cy-
cle error may result. This error results when the Start/Stop
occurs just after the clock edge (max error). To minimize
this error on all clocks an independent prescaler is used for
each timer and is designed so that its Start/Stop error is
less than 1 clock cycle.
Retriggerable One Shot
MODE 0: SINGLE PULSE GENERATOR
When the timer is in this mode the output will be initially low
if the Timer Start/Stop bit is low (stopped). When this mode
is initiated the timer output will go high on the next falling
edge of the prescaler’s input clock, the contents of the
The count hold/gate bit in the Timer Control Register can
be used to suspend the timer operation in modes 0, 1, and 2
(in mode 3 it is the trigger input). Suspending the tim-
TL/F/11416–11
FIGURE 7. LV8571A Timer Block Diagram
13
Functional Description (Continued)
input data registers are loaded into the timer. The output will
stay high until the counter reaches zero. At zero the output
is reset. The result is an output pulse whose duration is
equal to the input clock period times the count value (N)
loaded into the input data register. This is shown inFigure 8.
for one clock period of the timer clock. Then on the next
clock the counter is reloaded automatically and the count-
down repeats itself. The output, shown in Figure 9, is a
waveform whose pulse width and period is determined by N,
the input register value, and the input clock period:
e
c
e
a
(N 1) (Clock Period)
Pulse Width
Clock Period
N
Period
e
An interrupt is generated when the zero count is reached.
This can be used for one-time interrupts that are set to oc-
cur a certain amount of time in the future. In this mode the
Timer Start/Stop bit (TSS) is automatically reset upon zero
detection. This removes the need to reset TSS before start-
ing another operation.
Pulse Width
Clock Period
Again, the output polarity is controllable as in mode 0. If
enabled, an interrupt is generated whenever the zero count
is reached. This can be used to generate a periodic inter-
rupt.
MODE 2: SQUARE WAVE GENERATOR
The count down operation may be temporarily suspended
either under software control by setting the Count Hold/
Gate bit in the timer register high, or in hardware by setting
the G0 or G1 pin high.
This mode is also cyclic but in this case a square wave
rather than a pulse is generated. The output square wave
period is determined by the value loaded into the timer input
register. This period and the duty cycle are:
The above discussion assumes that the MFO output is pro-
grammed to be non-inverting outputs (active high). If the
polarity of the output waveform is wrong for the application
the polarity can be reversed by configuring the Output Mode
Register. The drive configuration can also be programmed
to be push pull or open drain.
e
a
e
Duty Cycle 0.5
Period
2(N
1) (Clock Period)
When the timer is stopped the output will be low, and when
the Start/Stop bit is set high the timer’s counter will be load-
ed on the next clock falling transition and the output will be
set high.
The output will be toggled after the zero count is detected
and the counter will then be reloaded, and the cycle will
MODE 1: RATE GENERATOR
When operating in this mode the timer will operate continu-
ously. Before the timer is started its output is low. When the
timer is started the input data register contents are loaded
into the counter on the negative clock edge and the output
is set high (again assuming the Output Mode Register is
programmed active high). The timer will then count down to
zero. Once the zero count is reached the output goes low
a
continue. Thus, every N
1 counts the output gets toggled,
as shown in Figure 10. Like the other modes the timer oper-
ation can be suspended by setting the count hold/gate bit
(CHG) in the Timer Control Register. An interrupt will be
generated every falling edge of the timer output, if enabled.
TL/F/11416–12
FIGURE 8. Typical Waveforms for Timer Mode 0
(MFO Output Programmed Active High)
TL/F/11416–13
FIGURE 9. Timing Waveforms for Timer Mode 1
(MFO Output Programmed Active High)
14
Functional Description (Continued)
Those users who find the error rate unacceptable may re-
duce the problem effectively to zero by employing a hard-
ware work-around that synchronizes the writing of the read
bit to the timer control register with respect to the decre-
menting clock. Refer to Figure 1 in Appendix A, for a sug-
gested hardware work-around.
A software work-around can reduce the errors but not as
substantial as a hardware work-around. Software work-
arounds are based on observations that the read following a
bad read appeared to be valid.
TL/F/11416–14
This problem concerns statistical probability and is similar to
metastability issues. For more information on metastability,
refer to 1991 IEEE transactions on Custom Integrated Cir-
cuits Conference, paper by T.J. Gabara of AT&T Bell Labo-
ratories, page 29.4.1.
FIGURE 10. Timing Waveforms for Timer Mode 2
(MFO Output Programmed Active High)
MODE 3: RETRIGGERABLE ONE SHOT
Once the timer Start/Stop bit is set the output stays inac-
tive, and nothing happens until the Count Hold/Gate (CHG)
bit is set in the timer control register. When a transition
ocurs the one shot output is set active immediately; the
counter is loaded with the value in the input register on the
next transition of the input clock and the countdown begins.
If a retrigger occurs, regardless of the current counter value,
the counters will be reloaded with the value in the input
register and the counter will be restarted without changing
the output state. See Figure 11. A trigger count can occur at
any time during the count cycle. In this mode the timer will
output a single pulse whose width is determined by the val-
ue in the input data register (N) and the input clock period.
Normally reading the timer data register addresses, 0FH
and 10H for Timer 0 and 11H and 12H for Timer 1 will result
in reading the input data register which contains the preset
value for the timers.
To read the contents of a timer, the mP first sets the timer
read bit in the appropriate Timer Control Register high. This
will cause the counter’s contents to be latched to 2–8 bit
output registers, and will enable these registers to be read if
the mP reads the timer’s input data register addresses. On
reading the LSB byte the timer read bit is internally reset
and subsequent reads of the timer locations will return the
input register values.
e
c
N
Pulse Width
Clock Period
DETAILED REGISTER DESCRIPTION
The timer will generate an interrupt only when it reaches a
count of zero. This timer mode is useful for continuous
‘‘watch dog’’ timing, line frequency power failure detection,
etc.
There are 5 external address bits: Thus, the host microproc-
essor has access to 32 locations at one time. An internal
switching scheme provides a total of 67 locations.
This complete address space is organized into two pages.
Page 0 contains two blocks of control registers, timers, real
time clock counters, and special purpose RAM, while page
1 contains general purpose RAM. Using two blocks enables
the 9 control registers to be mapped into 5 locations. The
only register that does not get switched is the Main Status
Register. It contains the page select bit and the register
select bit as well as status information.
READING THE TIMERS
National has discovered that some users may encounter
unacceptable error rates for their applications when reading
the timers on the fly asynchronously. When doing asynchro-
nous reads of the timers, an error may occur. The error is
that a successive read may be larger than the previous
read. Experimental results indicate that the typical error rate
is approximately one per 29000 under the following condi-
tions:
A memory map is shown in Figure 2 and register addressing
in Table VII. They show the name, address and page loca-
tions for the LV8571A.
Timer clock frequency of 5 MHz.
Computer: 386/33 MHz PC/AT
Program: Microsoft ‘C’ 6.0, reading and saving timer con-
tents in a continuous loop.
TL/F/11416–15
FIGURE 11. Timing Waveforms for Timer Mode 3, MFO Output Programmed Active High
15
Functional Description (Continued)
TABLE VII. Register/Counter/RAM
Addressing for LV8571A
MAIN STATUS REGISTER
PS
RS
A0-4
Description
(Note 1) (Note 2)
CONTROL REGISTERS
00
01
02
03
04
01
02
03
04
X
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
Main Status Register
Timer 0 Control Register
Timer 1 Control Register
Periodic Flag Register
Interrupt Routing Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
TL/F/11416–16
COUNTERS (CLOCK CALENDAR)
The Main Status Register is always located at address 0
regardless of the register block or the page selected.
05
06
07
08
09
0
0
0
0
0
X
X
X
X
X
1/100, 1/10 Seconds (0–99)
Seconds
Minutes
Hours
(0–59)
(0–59)
(1–12, 0–23)
D0: This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins. The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt). This is unlike D3–D5
which can be set by an internal event but may not cause an
interrupt. This bit is reset when the interrupt status bits in the
Main Status Register are cleared.
Days of
Month
(1–28/29/30/31)
(1–12)
(0–99)
0A
0B
0C
0D
0E
0
0
0
0
0
X
X
X
X
X
Months
Years
Julian Date (LSB)
Julian Date
Day of Week
(1–99)
(0–3)
(1–7)
D1–D5: These five bits of the Main Status Register are the
main interrupt status bits. Any bit may be a one when any of
the interrupts are pending. Once an interrupt is asserted the
mP will read this register to determine the cause. These
interrupt status bits are not reset when read. Except for D1,
to reset an interrupt a one is written back to the correspond-
ing bit that is being tested. D1 is reset whenever the PFAIL
TIMER DATA REGISTERS
0F
10
11
12
0
0
0
0
X
X
X
X
Timer 0 LSB
Timer 0 MSB
Timer 1 LSB
Timer 1 MSB
TIME COMPARE RAM
e
pin
logic 1. This prevents loss of interrupt status when
13
14
15
0
0
0
X
X
X
Sec Compare RAM (0–59)
Min Compare RAM (0–59)
Hours Compare
reading the register in a polled mode. D1, D3–D5 are set
regardless of whether these interrupts are masked or not by
bits D6 and D7 of Interrupt Control Registers 0 and 1.
RAM
DOM Compare
RAM
(1–12, 0–23)
(1–28/29/30/31)
(1–12)
16
17
18
0
0
0
X
X
X
D6 and D7: These bits are Read/Write bits that control
which register block or RAM page is to be selected. Bit D6
controls the register block to be accessed (see memory
map). The memory map of the clock is further divided into
two memory pages. One page is the registers, clock and
timers, and the second page contains 31 bytes of general
purpose RAM. The page selection is determined by bit D7.
Months Compare
RAM
DOW Compare RAM (1–7)
TIME SAVE RAM
19
1A
1B
1C
1D
0
0
0
0
0
X
X
X
X
X
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
1E
1F
0
0
1
RAM
RAM/Test Mode Register
X
01–1F
1
X
2nd Page General Purpose RAM
1 PSÐPage Select (Bit D7 of Main Status Register)
2 RSÐRegister Select (Bit D6 of Main Status Register)
16
Functional Description (Continued)
TIMER 0 AND 1 CONTROL REGISTER
D0–D5: These bits are set by the real time rollover events:
e
read and can be used as selective data change flags.
(Time Change
1). The bits are reset when the register is
D6: This bit performs a dual function. When this bit is read, a
one indicates that an oscillator failure has occurred and the
time information may have been lost. Some of the ways an
oscillator failure might be caused are: failure of the crystal,
shorting OSC IN or OSC OUT to GND or V , removal of
CC
crystal, removal of battery when in the battery backed mode
(when a ‘‘0’’ is written to D6), lowering the voltage at the
V
pin to a value less than 2.2V when in the battery
BB
backed mode. Bit D6 is automatically set to 1 on initial pow-
er-up or an oscillator fail event. The oscillator fail flag is
reset by writing a one to the clock start/stop bit in the Real
Time Mode Register, with the crystal oscillating.
TL/F/11416–17
These registers control the operation of the timers. Each
timer has its own register.
When D6 is written to, it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application. When set to a one this bit configures the TCP
for single power supply applications. This bit is automatically
set on initial power-up or an oscillator fail event. When set,
D6 disables the oscillator reference circuit. The result is that
D0: This bit will Start (1) or Stop (0) the timer. When the
timer is stopped the timer’s prescaler and counter are reset,
and the timer will restart from the beginning when started
again. In mode 0 on time out the TSS bit is internally reset.
the oscillator is referenced to V . When a zero is written to
CC
D6 the oscillator reference is enabled, thus the oscillator is
D1 and D2: These control the count mode of the timers.
See Table VI.
referenced to V . This allows operation in standard battery
BB
standby applications.
D3–D5: These bits control which clock signal is applied to
the timer’s counter input. Refer to Table IV for details.
At initial power on, if the LV8571A is going to be pro-
pin should be
D6: This is the read bit. If a one is written into this location it
will cause the contents of the timer to be latched into a
holding register, which can be read by the mP at any time.
Reading the least significant byte of the timer will reset the
RD bit. The timer read cycle can be aborted by writing RD to
zero.
grammed for battery backed mode, the V
BB
connected to a potential in the range of 2.2V to V -0.4V.
CC
pin should be
For single supply mode operation, the V
BB
connected to GND and the PFAIL pin connected to V
.
CC
D7: Writing a one to this bit enables the test mode register
at location 1F (see Table VII). This bit should be forced to
zero during initialization for normal operation. If the test
mode has been entered, clear the test mode register before
leaving test mode. (See separate test mode application
note for further details.)
D7: The CHG bit has two mode dependent functions. In
modes 0 through 2 writing a one to this bit will suspend the
timer operation (without resetting the timer prescaler). How-
ever, in mode 3 this bit is used to trigger or re-trigger the
count sequence as with the gate pins. If retriggering is de-
sired using the CHG bit, it is not necessary to write a zero to
this location prior to the re-trigger. The action of further writ-
ing a one to this bit will re-trigger the count.
INTERRUPT ROUTING REGISTER
PERIODIC FLAG REGISTER
TL/F/11416–19
TL/F/11416–18
D0–D4: The lower 5 bits of this register are associated with
the main interrupt sources created by this chip. The purpose
of this register is to route the interrupts to either the MFO
(multi-function pin), or to the main interrupt pin. When any
bit is set the associated interrupt signal will be sent to the
MFO pin, and when zero it will be sent to the INTR pin.
The Periodic Flag Register has the same bit for bit corre-
spondence as Interrupt Control Register 0 except for D6
and D7. For normal operation (i.e., not a single supply appli-
cation) this register must be written to on initial power up or
after an oscillator fail event. D0–D5 are read only bits, D6
and D7 are read/write.
17
Functional Description (Continued)
D5: The Delay Enable bit is used when a power fail occurs.
D2: The count mode for the hours counter can be set to
either 24 hour mode or 12 hour mode with AM/PM indicator.
A one will place the clock in 12 hour mode.
If this bit is set, a 480 ms delay is generated internally before
the mP interface is locked out. This will enable the mP to
access the registers for up to 480 ms after it receives a
power fail interrupt. After a power failure is detected but
prior to the 480 ms delay timing out, the host mP may force
immediate lock out by resetting the Delay Enable bit. Note if
this bit is a 0 when power fails then after a delay of 30 ms
min/63 ms max the mP cannot read the chip.
D3: This bit is the master Start/Stop bit for the clock. When
a one is written to this bit the real time counter’s prescaler
and counter chain are enabled. When this bit is reset to zero
the contents of the real time counter is stopped and the
prescaler is cleared. When the TCP is initially powered up
this bit will be held at a logic 0 until the oscillator starts
functioning correctly after which this bit may be modified. If
an oscillator fail event occurs, this bit will be reset to logic 0.
D6: This read only bit is set and reset by the voltage at the
pin. It can be used by the mP to determine whether the
V
BB
battery voltage at the V pin is getting too low. A compara-
BB
D4: This bit controls the operation of the interrupt output in
standby mode. If set to a one it allows Alarm, Periodic, and
Power Fail interrupts to be functional in standby mode. Tim-
er interrupts will also be functional provided that bit D5 is
also set. Note that the MFO and INTR pins are configured
as open drain in standby mode.
tor monitors the battery and when the voltage is lower than
2.1V (typical) this bit is set. The power fail interrupt must be
enabled to check for a low battery voltage.
D7: Time Save Enable bit controls the loading of real-time-
clock data into the Time Save RAM. When a one is written
to this bit the Time Save RAM will follow the corresponding
clock registers, and when a zero is written to this bit the time
in the Time Save RAM is frozen. This eliminates any syn-
chronization problems when reading the clock, thus negat-
ing the need to check for a counter rollover during a read
cycle.
If bit D4 is set to a zero then interrupt control register 0 and
bits D6 and D7 of interrupt control register 1 will be reset
l
when the TCP enters the standby mode (V
BB
V ). They
CC
will have to be re-configured when system (V ) power is
CC
restored.
D5: This bit controls the operation of the timers in standby
mode. If set to a one the timers will continue to function
when the TCP is in standby mode. The input pins TCK, G0,
G1 are locked out in standby mode, and cannot be used.
This bit must be set to a one prior to power failing to enable
the Time Save feature. When the power fails this bit is auto-
matically reset and the time is saved in the Time Save RAM.
Therefore external control of the timers is not possible in
standby mode. Note also that MFO and T1 pins are auto-
matically reconfigured open drain during standby.
REAL TIME MODE REGISTER
D6 and D7: These two bits select the crystal clock frequen-
cy as per the following table:
Crystal
XT1
XT0
Frequency
0
0
1
1
0
1
0
1
32.768 kHz
4.194304 MHz
4.9152 MHz
32.000 kHz
All bits are Read/Write, and any mode written into this regis-
ter can be determined by reading the register. On initial
power up these bits are random.
TL/F/11416–20
D0–D1: These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
OUTPUT MODE REGISTER
Leap Year
LY1
LY0
Counter
0
0
1
1
0
1
0
1
Leap Year Current Year
Leap Year Last Year
Leap Year 2 Years Ago
Leap Year 3 Years Ago
TL/F/11416–21
18
Functional Description (Continued)
D0 and D1: These bits are available as general purpose
RAM.
switching is required. When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin.
D2: This bit, when set to a one makes the INTR output pin
active high, and when set to a zero, it makes this pin active
low.
D6 and D7: These are individual timer enable bits. A one
written to these bits enable the timers to generate interrupts
to the mP.
D3: This bit controls whether the INTR pin is an open drain
or push-pull output. A one indicates push-pull.
INTERRUPT CONTROL REGISTER 1
D4: This bit, when set to a one makes the MFO output pin
active high, and when set to a zero, it makes this pin active
low.
D5: This bit controls whether the MFO pin is an open drain
or push-pull output. A one indicates push-pull.
D6 and D7: These bits are used to program the signal ap-
pearing at the MFO output, as follows:
D7 D6
MFO Output Signal
0
0
1
0
1
X
2nd Interrupt
Timer 0 Waveform
Buffered Crystal Oscillator
TL/F/11416–23
D0–D5: Each of these bits are enable bits which will enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the ‘‘always equal’’ state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit D3 of the Main Status Regis-
ter, all bits must be written to a logic zero.
INTERRUPT CONTROL REGISTER 0
D6: In order to generate an external alarm compare inter-
rupt to the mP from bit D3 of the Main Status Register, this
bit must be written to a logic 1. If battery backed mode is
selected then this bit is controlled by D4 of the Real Time
Mode Register.
D7: The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
TL/F/11416–22
e
be generated to the mP when PFAIL
0. If battery backed
D0–D5: These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subse-
quent interrupts will be spaced correctly. These interrupts
are useful when minute, second, real time reading, or task
mode is selected then this bit is controlled by D4 of the Real
Time Mode Register.
This bit also enables the low battery detection analog cir-
cuitry.
If the user wishes to mask the power fail interrupt, but utilize
the analog circuitry, this bit should be enabled, and the
Routing Register can be used to route the interrupt to the
MFO pin. The MFO pin can then be left open or configured
as the Timer 0 or buffered oscillator output.
19
Control and Status Register Address Bit Map
D7
D6
D5
D4
D3
D2
D1
D0
e
e
e
00H
1. Reset by
writing
1 to bit.
Main Status Register PS
0
RS
0
ADDRESS
1
1
1
1
2
3
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Page
Register
Select
Timer 1
Timer 0
Alarm
Interrupt
Periodic
Interrupt
Power Fail
Interrupt
Interrupt
Status
2. Set/reset by
voltage at
PFAIL pin.
Select
Interrupt
Interrupt
3. Reset when
all pending
interrupts
are removed.
e
e
e
Address 01H
Timer 0 Control Register PS
0
RS
0
Count Hold
Gate
Timer
Read
Input Clock Input Clock Input Clock
Select C2 Select C1 Select C0
Mode
Mode
Timer
All Bits R/W
All Bits R/W
Select M1
Select M0
Start/Stop
e
e
e
02H
Timer 1 Control Register PS
0
RS
Input Clock Input Clock Input Clock
Select C2 Select C1 Select C0
0
Address
Count Hold
Gate
Timer
Read
Mode
Mode
Timer
Select M1
Select M0
Start/Stop
e
e
e
Address 03H
Periodic Flag Register PS
0
RS
0
4. Read Osc fail
Write 0 Batt-
Backed Mode
Write 1 Single
Supply Mode
4
5
5
5
5
5
5
R/W
R/W
R
R
R
R
R
R
Test
Osc. Fail/
1 ms
Flag
10 ms
Flag
100 ms
Flag
Seconds
Flag
10 Second
Flag
Minute
Flag
Mode
Single Supply
5. Reset by
positive edge
of read.
e
e
e
04H
Interrupt Routing Register PS
0
RS
0
Address
R/W
Timer 0
6
R/W
R
R/W
R/W
R/W
R/W
R/W
Power Fail
Delay
Timer 1
Alarm
Periodic
Int. Route
MFO/INT
Power Fail 6. Set and reset
Time Save Low Battery
Enable Flag
by V
BB
voltage.
Int. Route
MFO/INT
Int. Route
MFO/INT
Int. Route
MFO/INT
Int. Route
MFO/INT
Enable
e
e
e
01H
Real Time Mode Register PS
0
RS
1
Address
Clock
on Back-Up on Back-Up Start/Stop
Crystal
Crystal
Timers EN Interrupt EN
12/24 Hr.
Mode
Leap Year
MSB
Leap Year
LSB
All Bits R/W
Freq. XT1
Freq. XT0
e
e
e
02H
Output Mode Register PS
0
RS
MFO
PP/OD
1
Address
MFO
Active HI/LO
MFO as
Crystal
MFO as
Timer 0
INTR
INTR
RAM
RAM
All Bits R/W
All Bits R/W
PP/OD
Active HI/LO
e
e
e
Address 03H
Interrupt Control Register 0 PS
0
RS
1
Timer 1
Interrupt
Enable
Timer 0
Interrupt
Enable
1 ms
10 ms
100 ms
Interrupt
Enable
Seconds
Interrupt
Enable
10 Second
Interrupt
Enable
Minute
Interrupt
Enable
Interrupt
Enable
Interrupt
Enable
e
e
e
Address 04H
Interrupt Control Register 1 PS
0
RS
1
Power Fail
Interrupt
Enable
Alarm
Interrupt
Enable
DOW
Interrupt
Enable
Month
DOM
Interrupt
Enable
Hours
Interrupt
Enable
Minute
Interrupt
Enable
Second
Interrupt
Enable
Interrupt
Enable
All Bits R/W
20
Application Hints
Suggested initialization procedure for LV8571A in battery
backed applications that use the V pin.
BB
ration, interrupt control and timer functions may be ini-
tialized.
6. Test bit D6 in the Periodic Flag Register:
1. Enter the test mode by writing a 1 to bit D7 in the Period-
ic Flag Register.
IF a 1, go to 5.1 If this bit remains a 1 after 3 seconds,
then abort and check hardware. The crystal may be de-
fective or not installed. There may be a short at OSC IN
2. Write zero to the RAM/TEST mode Register located in
page 0, address HEX 1F.
or OSC OUT to V or GND, or to some impedance that
CC
3. Leave the test mode by writing a 0 to bit D7 in the Peri-
odic Flag Register. Steps 1, 2, 3 guarantee that if the
test mode had been entered during power on (due to
random pulses from the system), all test mode condi-
tions are cleared. Most important is that the OSC Fail
Disable bit is cleared. Refer to AN-589 for more informa-
tion on test mode operation.
is less than 10 MX.
IF a 0, then the oscillator is running, go to step 7.
7. Write a 0 to bit D6 in the Periodic Flag Register. This
action puts the clock chip in the battery backed mode.
This mode can be entered only if the OSC fail flag (bit
D6 of the Periodic Flag Register) is a 0. Reminder, bit D6
is a dual function bit. When read, D6 returns oscillator
status. When written, D6 causes either the Battery
Backed Mode, or the Single Supply Mode of operation.
4. After power on (V
and V powered), select the cor-
BB
CC
rect crystal frequency bits (D7, D6 in the Real Time
Mode Register) as shown in Table 1.
The only method to ensure the chip is in the battery
backed mode is to measure the waveform at the OSC
OUT pin. If the battery backed mode was selected suc-
cessfully, then the peak to peak waveform at OSC OUT
is referenced to the battery voltage. If not in battery
Table 1
Frequency
32.768 KHz
4.194304 MHz
4.9152 MHz
32.0 KHz
D7
0
D6
0
0
1
backed mode, the waveform is referenced to V . The
CC
measurement should be made with a high impedance
low capacitance probe (10 MX, 10 pF oscilloscope
probe or better). Typical peak to peak swings are within
1
0
1
1
0.6V of V
and ground respectively.
CC
5. Enter a software loop that does the following:
8. Write a 1 to bit D7 of Interrupt Control Register 1. This
action enables the PFAIL pin and associated circuitry.
Set a 3 second(approx) software counter. The crystal
oscillator may take 1 second to start.
9. Write a 1 to bit D4 of the Real Time Mode Register. This
action ensures that bit D7 of Interrupt Control Register 1
5.1 Write a 1 to bit D3 in the Real Time Mode Register (try
to start the clock). Make sure the crystal select bits re-
main the same as in step 1. Under normal operation, this
bit can be set only if the oscillator is running. During the
software loop, RAM, real time counters, output configu-
l
remains a 1 when V
V
CC
(standby mode).
BB
10. Initialize the rest of the chip as needed.
Typical Application
TL/F/11416–24
*These components may be necessary to meet UL requirements for lithium batteries. Consult battery manufacturer.
21
Appendix A
TL/F/11416–29
FIGURE A1. Typical Interface Where the ‘‘Write Strobe’’ is Synchronized to the Decrementing Clock of the Timer
22
Typical Performance Characteristics
Operating Current vs
Supply Voltage
(Battery Backed Mode
Operating Current vs
Supply Voltage
(Single Supply Mode
e
32.768 kHz,
F
OSC
e
e
F
32.768 kHz)
V
BB
2.5V)
OSC
TL/F/11416–25
TL/F/11416–26
Standby Current vs Power
Supply Voltage
Standby Current vs Power
Supply Voltage
e
e
4.194304 MHz)
(F
OSC
32.768 kHz)
(F
OSC
TL/F/11416–27
TL/F/11416–28
23
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number LV8571AN
NS Package Number N24C
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