LP38690SDX-5.0_技术文档

August 19, 2009

LP38690/LP38692

1A Low Dropout CMOS Linear Regulators

Stable with Ceramic Output Capacitors

General Description

Features

The LP38690/2 low dropout CMOS linear regulators provide

tight output tolerance (2.5% typical), extremely low dropout

voltage (450mV @ 1A load current, V_OUT= 5V), and excellent

AC performance utilizing ultra low ESR ceramic output ca-

pacitors.

2.5% output accuracy (25°C)

■

Low dropout voltage: 450mV @ 1A (typ, 5V out)

Wide input voltage range (2.7V to 10V)

Precision (trimmed) bandgap reference

Guaranteed specs for -40°C to +125°C

1µA off-state quiescent current

■

The low thermal resistance of the LLP, SOT-223 and T0-252

packages allow the full operating current to be used even in

high ambient temperature environments.

Thermal overload protection

The use of a PMOS power transistor means that no DC base

drive current is required to bias it allowing ground pin current

to remain below 100 µA regardless of load current, input volt-

age, or operating temperature.

Foldback current limiting

T0-252, SOT-223 and 6-Lead LLP packages

Enable pin (LP38692)

Dropout Voltage: 450 mV (typ) @ 1A (typ. 5V out).

Ground Pin Current: 55 µA (typ) at full load.

Precision Output Voltage: 2.5% (25°C) accuracy.

Applications

Hard Disk Drives

■

Notebook Computers

Battery Powered Devices

Portable Instrumentation

■

Typical Application Circuits

20126601

20126602

Note: * Minimum value required for stability.

**LLP package devices only.

201266

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Connection Diagrams

20126604

SOT-223, Top View

LP38692MP-X.X

20126603

TO-252, Top View

LP38690DT-X.X

20126605

20126606

6-Lead LLP, Bottom View

LP38690SD-X.X

6-Lead LLP, Bottom View

LP38692SD-X.X

Pin Descriptions

Description

V_IN

This is the input supply voltage to the regulator. For LLP devices, both V_INpins must be tied together

for full current operation (500mA maximum per pin).

GND

SNS

Circuit ground for the regulator. This is connected to the die through the lead frame, and also functions

as the heat sink when the large ground pad is soldered down to a copper plane.

Output sense pin allows remote sensing at the load which will eliminate the error in output voltage

due to voltage drops caused by the resistance in the traces between the regulator and the load. This

pin must be tied to V_OUT

.

V_EN

The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.

Regulated output voltage.

V_OUT

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2

Ordering Information

Order Number

LP38690SD-1.8

LP38690SD-2.5

LP38690SD-3.3

LP38690SD-5.0

LP38690DT-1.8

LP38690DT-2.5

LP38690DT-3.3

LP38690DT-5.0

LP38692SD-1.8

LP38692SD-2.5

LP38692SD-3.3

LP38692SD-5.0

LP38692MP-1.8

LP38692MP-2.5

LP38692MP-3.3

LP38692MP-5.0

LP38690SDX-1.8

LP38690SDX-2.5

LP38690SDX-3.3

LP38690SDX-5.0

LP38690DTX-1.8

LP38690DTX-2.5

LP38690DTX-3.3

LP38690DTX-5.0

LP38692SDX-1.8

LP38692SDX-2.5

LP38692SDX-3.3

LP38692SDX-5.0

LP38692MPX-1.8

LP38692MPX-2.5

LP38692MPX-3.3

LP38692MPX-5.0

Package Marking

Package Type

6-Lead LLP

TO-252

Package Drawing

SDE06A

TD03B

Supplied As

L113B

L114B

1000 Units Tape and Reel

75 Units per Rail

L115B

L116B

LP38690DT-1.8

LP38690DT-2.5

LP38690DT-3.3

LP38690DT-5.0

L123B

TO-252

TD03B

75 Units per Rail

TO-252

TD03B

75 Units per Rail

TO-252

TD03B

75 Units per Rail

6-Lead LLP

SOT-223

SDE06A

MP05A

1000 Units Tape and Reel

4500 Units Tape and Reel

2500 Units Tape and Reel

4500 Units Tape and Reel

2000 Units Tape and Reel

L124B

L125B

L126B

LJPB

LJRB

SOT-223

MP05A

LJSB

SOT-223

MP05A

LJTB

SOT-223

MP05A

L113B

6-Lead LLP

TO-252

SDE06A

TD03B

L114B

L115B

L116B

LP38690DT-1.8

LP38690DT-2.5

LP38690DT-3.3

LP38690DT-5.0

L123B

TO-252

TD03B

TO-252

TD03B

TO-252

TD03B

6-Lead LLP

SOT-223

SDE06A

MP05A

L124B

L125B

L126B

LJPB

LJRB

SOT-223

MP05A

LJSB

SOT-223

MP05A

LJTB

SOT-223

MP05A

3

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V(max) All pins (with respect to GND)

I_OUT

-0.3V to 12V

Internally Limited

−40°C to +150°C

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Junction Temperature

Operating Ratings

Storage Temperature Range

Lead Temp. (Soldering, 5 seconds)

ESD Rating (Note 3)

−65°C to +150°C

260°C

2 kV

Internally Limited

V_INSupply Voltage

2.7V to 10V

Operating Junction

Temperature Range

−40°C to +125°C

Power Dissipation (Note 2)

Electrical Characteristics Limits in standard typeface are for T_J= 25°C, and limits in boldface type apply over

the full operating temperature range. Unless otherwise specified: V_IN= V_OUT+ 1V, C_IN= C_OUT= 10 µF, I_LOAD= 10mA. Min/Max

limits are guaranteed through testing, statistical correlation, or design.

Typ

(Note 4)

Symbol

Parameter

Conditions

Min

Max

Units

-2.5

2.5

100 µA < I_L< 1A

V_O

%V_OUT

Output Voltage Tolerance

-5.0

5.0

V_O+ 1V ≤ V_IN≤ 10V

Output Voltage Line Regulation

(Note 6)

ΔV_O/ΔV_IN

ΔV_O/ΔI_L

V_O+ 0.5V ≤ V_IN≤ 10V

0.03

1.8

0.1

5

%/V

%/A

I_L= 25mA

Output Voltage Load Regulation

(Note 7)

1 mA < I_L< 1A

V_IN= V_O+ 1V

(V_O= 1.8V)

I_L= 1A

950

1600

(V_O= 2.5V)

I_L= 0.1A

I_L= 1A

80

800

145

1300

V_IN- V_OUT

Dropout Voltage (Note 8)

mV

(V_O= 3.3V)

I_L= 0.1A

I_L= 1A

65

650

110

1000

(V_O= 5V)

I_L= 0.1A

I_L= 1A

45

450

100

800

I_Q

Quiescent Current

55

100

1

V_IN≤ 10V, I_L=100 µA - 1A

V_EN≤ 0.4V, (LP38692 Only)

0.001

µA

I_L(MIN)

I_FB

Minimum Load Current

Foldback Current Limit

100

V_IN- V_O≤ 4V

V_IN- V_O> 5V

V_IN- V_O< 4V

450

mA

dB

1500

PSRR

Ripple Rejection

V_IN= V_O+ 2V(DC), with 1V(p-p) /

120Hz Ripple

55

160

10

T_SD

Thermal Shutdown Activation

(Junction Temp)

°C

T_SD(HYST)

Thermal Shutdown Hysteresis

(Junction Temp)

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Typ

(Note 4)

Symbol

Parameter

Output Noise

Conditions

Min

Max

Units

e_n

BW = 10Hz to 10kHz

V_O= 3.3V

0.7

0.5

µV/

µA

V_O(LEAK)

V_EN

Output Leakage Current

V_O= V_O(NOM) + 1V @ 10V_IN

Output = OFF

12

Enable Voltage (LP38692 Only)

0.4

Output = ON, V_IN= 4V

Output = ON, V_IN= 6V

Output = ON, V_IN= 10V

V_EN= 0V or 10V, V_IN= 10V

1.8

3.0

4.0

-1

V

I_EN

Enable Pin Leakage

0.001

1

µA

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device

is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not

apply when operating the device outside of its rated operating conditions.

Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used).

The junction-to-ambient thermal resistance ( θ_J-A) for the TO-252 is approximately 90°C/W for a PC board mounting with the device soldered down to minimum

copper area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the TO-252, the θ_J-Adrops to approximately 50°C/W. The

SOT-223 package has a θ_J-Aof approximately 125°C/W when soldered down to a minimum sized pattern (less than 0.1 square inch) and approximately 70°C/W

when soldered to a copper area of one square inch. The θ_J-Avalues for the LLP package are also dependent on trace area, copper thickness, and the number

of thermal vias used (refer to application note AN-1187). If power disspation causes the junction temperature to exceed specified limits, the device will go into

thermal shutdown.

Note 3: ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.

Note 4: Typical numbers represent the most likely parametric norm for 25°C operation.

Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.

Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.

5

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Block Diagrams

20126607

FIGURE 1. LP38690 Functional Diagram (LLP)

20126608

FIGURE 2. LP38690 Functional Diagram (TO-252)

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6

20126609

FIGURE 3. LP38692 Functional Diagram (LLP)

20126610

FIGURE 4. LP38692 Functional Diagram (SOT-223)

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Typical Performance Characteristics Unless otherwise specified: T_J= 25°C, C_IN= C_OUT= 10 µF, Enable

pin is tied to V_IN(LP38692 only), V_OUT= 1.8V, V_IN= V_OUT+1V, I_L= 10mA.

Noise vs Frequency

Ripple Rejection

Noise vs Frequency

Ripple Rejection

20126636

20126635

20126618

20126637

20126620

20126622

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Line Transient Response

Load Transient Response

Line Transient Response

Load Transient Response

20126624

20126626

20126628

20126640

20126641

20126642

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Load Transient Response

20126643

20126644

V_OUTvs Temperature (5.0V)

V_OUTvs Temperature (3.3V)

20126630

20126631

V_OUTvs Temperature (2.5V)

V_OUTvs Temperature (1.8V)

20126632

20126633

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V_OUTvs V_IN(1.8V)

V_OUTvs V_IN(Power-Up)

20126660

20126659

V_OUTvs V_EN, ON (LP38692 Only)

V_OUTvs V_EN, OFF (LP38692 Only)

20126661

20126662

Dropout Voltage vs I_OUT

20126650

20126651

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Enable Voltage vs Temperature

Load Regulation vs Temperature

20126652

20126653

Line Regulation vs Temperature

20126654

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ratings of temperature and voltage. Of course, they are typi-

cally larger and more costly than Z5U/Y5U types for a given

voltage and capacitance.

Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are re-

quired to assure stability. These capacitors must be correctly

selected for proper performance.

TANTALUM

Solid Tantalum capacitors have good temperature stability: a

high quality Tantalum will typically show a capacitance value

that varies less than 10-15% across the full temperature

range of -40°C to +125°C. ESR will vary only about 2X going

from the high to low temperature limits.

INPUT CAPACITOR: An input capacitor of at least 1µF is re-

quired (ceramic recommended). The capacitor must be lo-

cated not more than one centimeter from the input pin and

returned to a clean analog ground.

PCB LAYOUT

OUTPUT CAPACITOR: An output capacitor is required for

loop stability. It must be located less than 1 centimeter from

the device and connected directly to the output and ground

pins using traces which have no other currents flowing

through them.

Good PC layout practices must be used or instability can be

induced because of ground loops and voltage drops. The in-

put and output capacitors must be directly connected to the

input, output, and ground pins of the regulator using traces

which do not have other currents flowing in them (Kelvin con-

nect).

The minimum amount of output capacitance that can be used

for stable operation is 1µF. Ceramic capacitors are recom-

mended (the LP38690/2 was designed for use with ultra low

ESR capacitors). The LP38690/2 is stable with any output

capacitor ESR between zero and 100 Ohms.

The best way to do this is to lay out C_INand C_OUTnear the

device with short traces to the V_IN, V_OUT, and ground pins. The

regulator ground pin should be connected to the external cir-

cuit ground so that the regulator and its capacitors have a

"single point ground".

ENABLE PIN (LP38692 only): The LP38692 has an Enable

pin (EN) which allows an external control signal to turn the

regulator output On and Off. The Enable On/Off threshold has

no hysteresis. The voltage signal must rise and fall cleanly,

and promptly, through the ON and OFF voltage thresholds.

The Enable pin has no internal pull-up or pull-down to estab-

lish a default condition and, as a result, this pin must be

terminated either actively or passively. If the Enable pin is

driven from a source that actively pulls high and low, the drive

voltage should not be allowed to go below ground potential or

higher than V_IN. If the application does not require the Enable

function, the pin should be connected directly to the V_INpin.

It should be noted that stability problems have been seen in

applications where "vias" to an internal ground plane were

used at the ground points of the IC and the input and output

capacitors. This was caused by varying ground potentials at

these nodes resulting from current flowing through the ground

plane. Using a single point ground technique for the regulator

and it’s capacitors fixed the problem. Since high current flows

through the traces going into V_INand coming from V_OUT

Kelvin connect the capacitor leads to these pins so there is

no voltage drop in series with the input and output capacitors.

,

Foldback Current Limiting: Foldback current limiting is built

into the LP38690/2 which reduces the amount of output cur-

rent the part can deliver as the output voltage is reduced. The

amount of load current is dependent on the differential voltage

between V_INand V_OUT. Typically, when this differential volt-

age exceeds 5V, the load current will limit at about 450 mA.

When the V_IN- V_OUTdifferential is reduced below 4V, load

current is limited to about 1500 mA.

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic

interference) can degrade any integrated circuit’s perfor-

mance because of the small dimensions of the geometries

inside the device. In applications where circuit sources are

present which generate signals with significant high frequen-

cy energy content (> 1 MHz), care must be taken to ensure

that this does not affect the IC regulator.

SELECTING A CAPACITOR

If RFI/EMI noise is present on the input side of the regulator

(such as applications where the input source comes from the

output of a switching regulator), good ceramic bypass capac-

itors must be used at the input pin of the IC.

It is important to note that capacitance tolerance and variation

with temperature must be taken into consideration when se-

lecting a capacitor so that the minimum required amount of

capacitance is provided over the full operating temperature

range.

If a load is connected to the IC output which switches at high

speed (such as a clock), the high-frequency current pulses

required by the load must be supplied by the capacitors on

the IC output. Since the bandwidth of the regulator loop is less

than 100 kHz, the control circuitry cannot respond to load

changes above that frequency. This means the effective out-

put impedance of the IC at frequencies above 100 kHz is

determined only by the output capacitor(s).

Capacitor Characteristics

CERAMIC

For values of capacitance in the 10 to 100 µF range, ceramics

are usually larger and more costly than tantalums but give

superior AC performance for bypassing high frequency noise

because of very low ESR (typically less than 10 mΩ). How-

ever, some dielectric types do not have good capacitance

characteristics as a function of voltage and temperature.

In applications where the load is switching at high speed, the

output of the IC may need RF isolation from the load. It is

recommended that some inductance be placed between the

output capacitor and the load, and good RF bypass capacitors

be placed directly across the load.

Z5U and Y5V dielectric ceramics have capacitance that drops

severely with applied voltage. A typical Z5U or Y5V capacitor

can lose 60% of its rated capacitance with half of the rated

voltage applied to it. The Z5U and Y5V also exhibit a severe

temperature effect, losing more than 50% of nominal capac-

itance at high and low limits of the temperature range.

PCB layout is also critical in high noise environments, since

RFI/EMI is easily radiated directly into PC traces. Noisy cir-

cuitry should be isolated from "clean" circuits where possible,

and grounded through a separate path. At MHz frequencies,

ground planes begin to look inductive and RFI/ EMI can cause

ground bounce across the ground plane. In multi-layer PCB

applications, care should be taken in layout so that noisy

X7R and X5R dielectric ceramic capacitors are strongly rec-

ommended if ceramics are used, as they typically maintain a

capacitance range within ±20% of nominal over full operating

13

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power and ground planes do not radiate directly into adjacent

layers which carry analog power and ground.

Attention should be paid to the units of measurement. Spot

noise is measured in units µV/root-Hz or nV/root-Hz and total

output noise is measured in µV(rms)

OUTPUT NOISE

The primary source of noise in low-dropout regulators is the

internal reference. Noise can be reduced in two ways: by in-

creasing the transistor area or by increasing the current drawn

by the internal reference. Increasing the area will decrease

the chance of fitting the die into a smaller package. Increasing

the current drawn by the internal reference increases the total

supply current (ground pin current).

Noise is specified in two ways: Spot Noise or Output Noise

Density is the RMS sum of all noise sources, measured at

the regulator output, at a specific frequency (measured with

a 1Hz bandwidth). This type of noise is usually plotted on a

curve as a function of frequency. Total Output Noise or

Broad-Band Noise is the RMS sum of spot noise over a

specified bandwidth, usually several decades of frequencies.

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14

Physical Dimensions inches (millimeters) unless otherwise noted

6-lead, LLP Package

NS Package Number SDE06A

TO-252 Package

NS Package Number TD03B

15

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SOT-223 Package

NS Package Number MP05A

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Notes

17

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型号：	LP38690SDX-5.0
厂家：	National Semiconductor
描述：	IC VREG 5 V FIXED POSITIVE LDO REGULATOR, 0.8 V DROPOUT, PDSO6, LLP-6, Fixed Positive Single Output LDO Regulator 光电二极管输出元件调节器
文件：	总18页 (文件大小：365K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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