LM5116MH/NOPB [NSC]
IC SWITCHING CONTROLLER, 590 kHz SWITCHING FREQ-MAX, PDSO20, TSSOP-20, Switching Regulator or Controller;
| 型号： | LM5116MH/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC SWITCHING CONTROLLER, 590 kHz SWITCHING FREQ-MAX, PDSO20, TSSOP-20, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总26页 (文件大小：473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 8, 2008
LM5116
Wide Range Synchronous Buck Controller
General Description
Features
The LM5116 is a synchronous buck controller intended for
step-down regulator applications from a high voltage or widely
varying input supply. The control method is based upon cur-
rent mode control utilizing an emulated current ramp. Current
mode control provides inherent line feed-forward, cycle by
cycle current limiting and ease of loop compensation. The use
of an emulated control ramp reduces noise sensitivity of the
pulse-width modulation circuit, allowing reliable control of
very small duty cycles necessary in high input voltage appli-
cations. The operating frequency is programmable from
50kHz to 1MHz. The LM5116 drives external high-side and
low-side NMOS power switches with adaptive dead-time con-
trol. A user-selectable diode emulation mode enables discon-
tinuous mode operation for improved efficiency at light load
conditions. A low quiescent current shutdown disables the
controller and consumes less than 10µA of total input current.
Additional features include a high voltage bias regulator, au-
tomatic switch-over to external bias for improved efficiency,
thermal shutdown, frequency synchronization, cycle by cycle
current limit and adjustable line under-voltage lockout. The
device is available in a power enhanced TSSOP-20 package
featuring an exposed die attach pad to aid thermal dissipation.
Emulated peak current mode
■
■
■
Wide operating range up to 100V
Low IQ shutdown (<10µA)
Drives standard or logic level MOSFETs
Robust 3.5A peak gate drive
■
■
■
■
■
■
■
■
■
■
■
■
Free-run or synchronous operation to 1MHz
Optional diode emulation mode
Programmable output from 1.215V to 80V
Precision 1.5% voltage reference
Programmable current limit
Programmable soft-start
Programmable line under-voltage lockout
Automatic switch to external bias supply
TSSOP-20EP exposed pad
Thermal shutdown
Typical Application
30007501
© 2008 National Semiconductor Corporation
300075
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Connection Diagram
30007502
Top View
See NS Package Number MXA20A
Ordering Information
Ordering Number
LM5116MH
Package Type
NSC Package Drawing
MXA20A
Supplied As
TSSOP-20EP
TSSOP-20EP
73 Units Per Anti-Static Tube
2500 units shipped as Tape & Reel
LM5116MHX
MXA20A
Pin Descriptions
Pin
1
Name Description
VIN Chip supply voltage, input voltage monitor and input to the VCC regulator.
2
UVLO If the UVLO pin is below 1.215V, the regulator will be in standby mode (VCC regulator running, switching regulator
disabled). If the UVLO pin voltage is above 1.215V, the regulator is operational. An external voltage divider can be
used to set an under-voltage shutdown threshold. There is a fixed 5µA pull up current on this pin when EN is high.
UVLO is pulled to ground in the event a current limit condition exists for 256 clock cycles.
3
RT/
The internal oscillator is set with a single resistor between this pin and the AGND pin. The recommended frequency
SYNC range is 50kHz to 1MHz. The internal oscillator can be synchronized to an external clock by AC coupling a positive
edge onto this node.
4
5
EN
If the EN pin is below 0.5V, the regulator will be in a low power state drawing less than 10µA from VIN. EN must be
pulled above 3.3V for normal operation.
RAMP Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope used
for current mode control.
6
7
AGND Analog ground.Connect to PGND through the exposed pad ground connection under the LM5116.
SS
An external capacitor and an internal 10µA current source set the soft start time constant for the rise of the error amp
reference. The SS pin is held low during VCC < 4.5V, UVLO < 1.215V, EN input low or thermal shutdown.
8
9
FB
Feedback signal from the regulated output. This pin is connected to the inverting input of the internal error amplifier.
The regulation threshold is 1.215V.
COMP Output of the internal error amplifier. The loop compensation network should be connected between this pin and the
FB pin.
10
11
VOUT Output monitor. Connect directly to the output voltage.
DEMB Low-side MOSFET source voltage monitor for diode emulation. For start-up into a pre-biased load, tie this pin to
ground at the CSG connection. For fully synchronous operation, use an external series resistor between DEMB and
ground to raise the diode emulation threshold above the low-side SW on-voltage.
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2
Pin
Name Description
12
CS
Current sense amplifier input. Connect to the top of the current sense resistor or the drain of the low-sided MOSFET
if RDS(ON) current sensing is used.
13
CSG
Current sense amplifier input. Connect to the bottom of the sense resistor or the source of the low-side MOSFET if
RDS(ON) current sensing is used.
14
15
16
17
PGND Power ground. Connect to AGND through the exposed pad ground connection under the LM5116.
LO
Connect to the gate of the low-side synchronous MOSFET through a short, low inductance path.
Locally decouple to PGND using a low ESR/ESL capacitor located as close to the controller as possible.
VCC
VCCX Optional input for an externally supplied VCC. If VCCX > 4.5V, VCCX is internally connected to VCC and the internal
VCC regulator is disabled. If VCCX is unused, it should be connected to ground.
18
HB
High-side driver supply for bootstrap gate drive. Connect to the cathode of the bootstrap diode and the positive
terminal of the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side MOSFET gate
and should be placed as close to the controller as possible.
19
20
HO
SW
Connect to the gate of the high-side synchronous MOSFET through a short, low inductance path
Switch node. Connect to the negative terminal of the bootstrap capacitor and the source terminal of the high-side
MOSFET.
EP
EP
Exposed pad. Solder to ground plane.
3
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RT to GND
EN to GND
ESD Rating
HBM (Note 2)
Storage Temperature Range
Junction Temperature
-0.3 to 7V
-0.3 to 100V
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2 kV
-55°C to +150°C
+150°C
VIN to GND
-0.3V to 100V
-0.3 to 16V
-3.0 to 100V
-0.3 to 16V
VCC, VCCX, UVLO to GND (Note 3)
SW, CS to GND
HB to SW
Operating Ratings (Note 1)
VIN
6V to 100V
4.75V to 15V
4.75V to 15V
-0.3V to 2V
HO to SW
VOUT to GND
CSG to GND
-0.3 to HB+0.3V
-0.3 to 100V
-1V to 1V
VCC, VCCX
HB to SW
DEMB to GND
Junction Temperature
LO to GND
SS to GND
-0.3 to VCC+0.3V
-0.3 to 7V
-40°C to +125°C
Note: RAMP, COMP are output pins. As such they are not specified to have
an external voltage applied.
FB to GND
-0.3 to 7V
DEMB to GND
-0.3 to VCC
Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature range of -40°C to +125°C and are provided for reference only. Unless otherwise specified, the following
conditions apply: VIN = 48V, VCC = 7.4V, VCCX = 0V, EN = 5V, RT = 16kΩ, no load on LO and HO.
Symbol
VIN Supply
Parameter
Conditions
Min
Typ
Max
Units
IBIAS
IBIASX
ISTDBY
VIN Operating Current
VIN Operating Current
VIN Shutdown Current
VCCX = 0V, VIN = 48V
VCCX = 0V, VIN = 100V
VCCX = 5V, VIN = 48V
VCCX = 5V, VIN = 100V
EN = 0V, VIN = 48V
5
5.9
1.2
1.6
1
7
mA
mA
mA
mA
µA
8
1.7
2.3
10
EN = 0V, VIN = 100V
1
µA
VCC Regulator
VCC(REG)
VCC Regulation
7.1
7.4
10.6
5.9
7.7
6.0
4.7
6.2
V
V
VCC LDO Mode Turn-off
VCC Regulation
VIN = 6V
5.0
15
V
VCC Sourcing Current Limit
VCCX Switch Threshold
VCCX Switch Hysteresis
VCCX Switch RDS(ON)
VCCX Leakage
VCC = 0V
VCCX Rising
26
mA
V
4.3
4.5
0.25
3.8
V
ICCX = 10mA
VCCX = 0V
VCCX = 3V
VCC Rising
Ω
-200
100
4.5
nA
kΩ
V
VCCX Pull- down Resistance
VCC Under-voltage Threshold
VCC Under-voltage Hysteresis
HB DC Bias Current
4.3
4.7
200
0.5
0.2
V
HB-SW = 15V
125
µA
EN Input
VIL max
VIH min
EN Input Low Threshold
EN Input High Threshold
EN Input Bias Current
EN Input Bias Current
EN Input Bias Current
V
3.3
-7.5
-1
V
VEN = 3V
-3
0
1
1
µA
µA
µA
VEN = 0.5V
VEN = 100V
20
90
UVLO Thresholds
UVLO Standby Threshold
UVLO Threshold Hysteresis
UVLO Pull-up Current Source
UVLO Pull-down RDS(ON)
UVLO Rising
UVLO = 0V
1.170
1.215 1.262
V
V
0.1
5.4
µA
Ω
80
210
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4
Symbol
Soft Start
Parameter
Conditions
Min
8
Typ
Max
14
Units
SS Current Source
SS = 0V
11
3
µA
V
SS Diode Emulation Ramp Disable
Threshold
SS Rising
SS to FB Offset
FB = 1.25V
160
45
mV
mV
SS Output Low Voltage
Sinking 100µA, UVLO = 0V
Error Amplifier
VREF
FB Reference Voltage
Measured at FB pin, FB =
COMP
1.195
3
1.215 1.231
V
FB Input Bias Current
COMP Sink/Source Current
DC Gain
FB = 2V
15
500
nA
mA
dB
AOL
fBW
80
3
Unity Gain Bandwidth
MHz
PWM Comparators
tHO(OFF)
Forced HO Off-time
320
450
100
580
ns
ns
tON(min)
Minimum HO On-time
VIN = 80V, CRAMP = 50pF
Oscillator
fSW1
Frequency 1
180
480
200
535
220
590
kHz
kHz
V
RT = 16kΩ
RT = 5kΩ
fSW2
Frequency 2
RT output voltage
RT sync positive threshold
1.191
3.0
1.215 1.239
3.5
4.0
V
Current Limit
VCS(TH)
Cycle-by-cycle Sense Voltage
Threshold (CSG-CS)
VCCX = 0V, RAMP = 0V
VCCX = 5V, RAMP = 0V
94
105
-1
110
122
126
139
mV
mV
VCS(THX)
Cycle-by-cycle Sense Voltage
Threshold (CSG-CS)
CS Bias Current
CS = 100V
CS = 0V
1
µA
µA
µA
ms
CS Bias Current
90
90
125
125
CSG Bias Current
Current Limit Fault Timer
CSG = 0V
1.28
RT = 16kΩ, (200kHz), (256
clock cycles)
RAMP Generator
IR1
IR2
RAMP Current 1
VIN = 60V, VOUT=10V
VIN = 10V, VOUT = 10V
VOUT = 36V
235
21
285
28
335
35
µA
µA
µA
mV
RAMP Current 2
VOUT Bias Current
RAMP Output Low Voltage
200
265
VIN = 60V, VOUT = 10V
Diode Emulation
SW Zero Cross Threshold
DEMB Output Current
DEMB Output Current
DEMB Output Current
-6
2.7
38
65
mV
µA
µA
µA
DEMB = 0V, SS = 1.25V
DEMB =0V, SS = 2.8V
1.6
28
45
3.8
48
85
DEMB = 0V, SS = Regulated
by FB
LO Gate Driver
VOLL
LO Low-state Output Voltage
LO High-state Output Voltage
ILO = 100mA
0.08
0.25
0.17
V
V
VOHL
ILO = -100mA, VOHL = VCC
VLO
-
LO Rise Time
C-load = 1000pF
C-load = 1000pF
VLO = 0V
18
12
ns
ns
A
LO Fall Time
IOHL
IOLL
Peak LO Source Current
Peak LO Sink Current
1.8
3.5
VLO = VCC
A
5
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Symbol
HO Gate Driver
VOLH
Parameter
Conditions
Min
Typ
Max
0.27
Units
HO Low-state Output Voltage
HO High-state Output Voltage
IHO = 100mA
0.17
0.45
V
V
VOHH
IHO = -100mA, VOHH = VHB
VHO
–
HO Rise Time
C-load = 1000pF
C-load = 1000pF
VHO = 0V
19
13
1
ns
ns
A
HO High-side Fall Time
Peak HO Source Current
Peak HO Sink Current
HB to SW under-voltage
IOHH
IOLH
VHO = VCC
2.2
3
A
V
Switching Characteristics
LO Fall to HO Rise Delay
C-load = 0
C-load = 0
75
70
ns
ns
HO Fall to LO Rise Delay
Thermal
TSD
Thermal Shutdown
Rising
170
15
°C
°C
Thermal Shutdown Hysteresis
Junction to Ambient
40
°C/W
θJA
θJC
Junction to Case
4
°C/W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. LO, HO and HB are rated at 1kV. 2kV rating for all pins
except VIN which is rated for 1.5kV.
Note 3: These pins must not exceed VIN.
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Typical Performance Characteristics
Typical Application Circuit Efficiency
Driver Source Current vs VCC
HO High RDS(ON) vs VCC
HO Low RDS(ON) vs VCC
30007503
30007504
30007506
30007508
Driver Dead-time vs Temperature
30007505
Driver Sink Current vs VCC
30007507
7
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LO High RDS(ON) vs VCC
EN Input Threshold vs Temperature
30007510
30007509
LO Low RDS(ON) vs VCC
HB to SW UVLO vs Temperature
30007512
30007511
Forced HO Off-time vs Temperature
VCCX = 5V
HB DC Bias Current vs Temperature
30007514
30007513
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Frequency vs RT
Error Amp Gain vs Frequency
30007516
30007515
30007517
30007519
Frequency vs Temperature
Error Amp Phase vs Frequency
30007518
Frequency vs Temperature
Current Limit Threshold vs Temperature
30007520
9
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VIN Operating Current vs Temperature
VCC vs Temperature
30007521
30007522
VCC UVLO vs Temperature
VCC vs VIN
30007523
30007524
VCC vs ICC
VCCX Switch RDS(ON) vs VCCX
30007525
30007526
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10
Block Diagram and Typical Application Circuit
11
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VCC regulator series pass transistor includes a diode be-
tween VCC and VIN that should not be forward biased in
normal operation. For an output voltage between 5V and 15V,
VOUT can be connected directly to VCCX. For VOUT < 5V,
a bias winding on the output inductor can be added to VOUT.
If the bias winding can supply VCCX greater than VIN, an
external blocking diode is required from the input power sup-
ply to the VIN pin to prevent VCC from discharging into the
input supply.
Detailed Operating Description
The LM5116 high voltage switching regulator features all of
the functions necessary to implement an efficient high voltage
buck regulator using a minimum of external components. This
easy to use regulator integrates high-side and low-side MOS-
FET drivers capable of supplying peak currents of 2 Amps.
The regulator control method is based on current mode con-
trol utilizing an emulated current ramp. Emulated peak current
mode control provides inherent line feed-forward, cycle by
cycle current limiting and ease of loop compensation. The use
of an emulated control ramp reduces noise sensitivity of the
pulse-width modulation circuit, allowing reliable processing of
the very small duty cycles necessary in high input voltage ap-
plications. The operating frequency is user programmable
from 50kHz to 1MHz. An oscillator/synchronization pin allows
the operating frequency to be set by a single resistor or syn-
chronized to an external clock. Fault protection features in-
clude current limiting, thermal shutdown and remote shut-
down capability. An under-voltage lockout input allows
regulator shutdown when the input voltage is below a user
selected threshold, and an enable function will put the regu-
lator into an extremely low current shutdown via the enable
input. The TSSOP-20EP package features an exposed pad
to aid in thermal dissipation.
The output of the VCC regulator is current limited to 15 mA
minimum. The VCC current is determined by the MOSFET
gate charge, switching frequency and quiescent current (see
MOSFETs section in the Application Information). To ensure
start-up, the VCC current should be less than 15 mA. The
VCC current may exceed 15 mA during normal run when VC-
CX is used, as long as the start-up requirement is met.
High Voltage Start-Up Regulator
The LM5116 contains a dual mode internal high voltage start-
up regulator that provides the VCC bias supply for the PWM
controller and a boot-strap gate drive for the high-side buck
MOSFET. The input pin (VIN) can be connected directly to an
input voltage source as high as 100 volts. For input voltages
below 10.6V, a low dropout switch connects VCC directly to
VIN. In this supply range, VCC is approximately equal to VIN.
For VIN voltages greater than 10.6V, the low dropout switch
is disabled and the VCC regulator is enabled to maintain VCC
at approximately 7.4V. The wide operating range of 6V to
100V is achieved through the use of this dual mode regulator.
30007585
FIGURE 3. Input Blocking Diode for VCCX > VIN
In high voltage applications extra care should be taken to en-
sure the VIN pin does not exceed the absolute maximum
voltage rating of 100V. During line or load transients, voltage
ringing on the VIN line that exceeds the Absolute Maximum
Ratings can damage the IC. Both careful PC board layout and
the use of quality bypass capacitors located close to the VIN
and GND pins are essential.
Upon power-up, the regulator sources current into the capac-
itor connected to the VCC pin. When the voltage at the VCC
pin exceeds 4.5V and the UVLO pin is greater than 1.215V,
the output switch is enabled and a soft-start sequence begins.
The output switch remains enabled until VCC falls below
4.5V, EN is pulled low, the UVLO pin falls below 1.215V or
the die temperature exceeds the thermal limit threshold.
Enable
The LM5116 contains an enable function allowing a very low
input current shutdown. If the enable pin is pulled below 0.5V,
the regulator enters shutdown, drawing less than 10µA from
the VIN pin. Raising the EN input above 3.3V returns the reg-
ulator to normal operation. The EN pin can be tied directly to
VIN if this function is not needed. It must not be left floating.
A 1MΩ pull-up resistor to VIN can be used to interface with
an open collector control signal.
30007548
FIGURE 2. VCCX Bias Supply with Additional Inductor
Winding
An output voltage derived bias supply can be applied to the
VCCX pin to reduce the IC power dissipation. If the bias sup-
ply voltage is greater than 4.5V, the internal regulator will
essentially shut off, reducing the IC power dissipation. The
30007549
FIGURE 4. Enable Circuit
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12
Where T = 1 / fSW and RT is in ohms. 450ns represents the
fixed minimum off time.
The LM5116WG oscillator has a maximum programmable
frequency that is dependent on the VCC voltage. If VCC is
above 6V, the frequency can be programmed up to 1 MHz. If
VCCX is used to bias VCC and VCCX < 6V, the maximum
programmable oscillator frequency is 750 kHz.
The RT/SYNC pin can be used to synchronize the internal
oscillator to an external clock. The external clock must be a
higher frequency than the free-running frequency set by the
RT resistor. The internal oscillator can be synchronized to an
external clock by AC coupling a positive edge into the RT/
SYNC pin. The voltage at the RT/SYNC pin is nominally
1.215V and must exceed 4V to trip the internal synchroniza-
tion pulse detection. A 5V amplitude signal and 100pF cou-
pling capacitor are recommended. The free-running frequen-
cy should be set nominally 15% below the external clock.
Synchronizing above twice the free-running frequency may
result in abnormal behavior of the pulse width modulator.
30007550
FIGURE 5. EN Bias Current vs Voltage
Error Amplifier and PWM
Comparator
UVLO
An under-voltage lockout pin is provided to disable the regu-
lator without entering shutdown. If the UVLO pin is pulled
below 1.215V, the regulator enters a standby mode of oper-
ation with the soft-start capacitor discharged and outputs
disabled, but with the VCC regulator running. If the UVLO in-
put is pulled above 1.215V, the controller will resume normal
operation. A voltage divider from input to ground can be used
to set a VIN threshold to disable the supply in brown-out con-
ditions or for low input faults. The UVLO pin has a 5 µA internal
pull up current that allows this pin to left open if the input un-
der-voltage lockout function is not needed. For applications
which require fast on/off cycling, the UVLO pin with an open
collector control signal may be used to ensure proper start-up
sequencing.
The internal high-gain error amplifier generates an error sig-
nal proportional to the difference between the regulated out-
put voltage and an internal precision reference (1.215V). The
output of the error amplifier is connected to the COMP pin
allowing the user to provide loop compensation components,
generally a type II network. This network creates a pole at
very low frequency, a mid-band zero, and a noise reducing
high frequency pole. The PWM comparator compares the
emulated current sense signal from the RAMP generator to
the error amplifier output voltage at the COMP pin.
Ramp Generator
The ramp signal used in the pulse width modulator for current
mode control is typically derived directly from the buck switch
current. This switch current corresponds to the positive slope
portion of the inductor current. Using this signal for the PWM
ramp simplifies the control loop transfer function to a single
pole response and provides inherent input voltage feed-for-
ward compensation. The disadvantage of using the buck
switch current signal for PWM control is the large leading
edge spike due to circuit parasitics that must be filtered or
blanked. Also, the current measurement may introduce sig-
nificant propagation delays. The filtering, blanking time and
propagation delay limit the minimal achievable pulse width. In
applications where the input voltage may be relatively large
in comparison to the output voltage, controlling small pulse
widths and duty cycles is necessary for regulation. The
LM5116 utilizes a unique ramp generator which does not ac-
tually measure the buck switch current but rather reconstructs
the signal. Representing or emulating the inductor current
provides a ramp signal to the PWM comparator that is free of
leading edge spikes and measurement or filtering delays. The
current reconstruction is comprised of two elements, a sam-
ple-and-hold DC level and an emulated current ramp.
The UVLO pin is also used to implement a “hiccup” current
limit. If a current limit fault exists for more than 256 consecu-
tive clock cycles, the UVLO pin will be internally pulled down
to 200 mV and then released, and a new SS cycle initiated.
A capacitor to ground connected to the UVLO pin will set the
timing for hiccup mode current limit. When this feature is used
in conjunction with the voltage divider, a diode across the top
resistor may be used to discharge the capacitor in the event
of an input under-voltage condition. There is a 5 µs filter at the
input to the fault comparator. At higher switching frequency
(greater than approximately 250 kHz) the hiccup timer may
be disabled if the fault capacitor is not used.
Oscillator and Sync Capability
The LM5116 oscillator frequency is set by a single external
resistor connected between the RT/SYNC pin and the AGND
pin. The resistor should be located very close to the device
and connected directly to the pins of the IC (RT/SYNC and
AGND). To set a desired oscillator frequency (fSW), the nec-
essary value for the resistor can be calculated from the fol-
lowing equation:
13
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30007546
FIGURE 6. Composition of Current Sense Signal
The sample-and-hold DC level is derived from a measure-
ment of the recirculating current through either the low-side
MOSFET or current sense resistor. The voltage level across
the MOSFET or sense resistor is sampled and held just prior
to the onset of the next conduction interval of the buck switch.
The current sensing and sample-and-hold provide the DC
level of the reconstructed current signal. The positive slope
inductor current ramp is emulated by an external capacitor
connected from the RAMP pin to the AGND and an internal
voltage controlled current source. The ramp current source
that emulates the inductor current is a function of the VIN and
VOUT voltages per the following equation:
these applications, a resistor is added between RAMP and
VCC to increase the ramp slope compensation.
IR = 5µA/V x (VIN-VOUT) + 25µA
Proper selection of the RAMP capacitor (CRAMP) depends up-
on the value of the output inductor (L) and the current sense
resistor (RS). For proper current emulation, the DC sample
and hold value and the ramp amplitude must have the same
dependence on the load current. That is:
30007547
FIGURE 7. RDS(ON) Current Sensing without Diode
Emulation
The DC current sample is obtained using the CS and CSG
pins connected to either a source sense resistor (RS) or the
RDS(ON) of the low-side MOSFET. For RDS(ON) sensing, RS =
RDS(ON) of the low-side MOSFET. In this case it is sometimes
helpful to adjust the current sense amplifier gain (A) to a lower
value in order to obtain the desired current limit. Adding ex-
ternal resistors RG in series with CS and CSG, the current
sense amplifier gain A becomes:
Where gm is the ramp generator transconductance (5µA/V)
and A is the current sense amplifier gain (10V/V). The ramp
capacitor should be located very close to the device and con-
nected directly to the pins of the IC (RAMP and AGND).
The difference between the average inductor current and the
DC value of the sampled inductor current can cause instability
for certain operating conditions. This instability is known as
sub-harmonic oscillation, which occurs when the inductor rip-
ple current does not return to its initial value by the start of
next switching cycle. Sub-harmonic oscillation is normally
characterized by observing alternating wide and narrow puls-
es at the switch node. Adding a fixed slope voltage ramp
(slope compensation) to the current sense signal prevents
this oscillation. The 25 µA of offset current provided from the
emulated current source adds the optimal slope compensa-
tion to the ramp signal for a 5V output. For higher output
voltages, additional slope compensation may be required. In
Current Limit
The LM5116 contains a current limit monitoring scheme to
protect the circuit from possible over-current conditions.
When set correctly, the emulated current sense signal is pro-
portional to the buck switch current with a scale factor deter-
mined by the current limit sense resistor. The emulated ramp
signal is applied to the current limit comparator. If the emu-
lated ramp signal exceeds 1.6V, the current cycle is termi-
nated (cycle-by-cycle current limiting). Since the ramp
amplitude is proportional to VIN - VOUT, if VOUT is shorted, there
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14
is an immediate reduction in duty cycle. To further protect the
external switches during prolonged current limit conditions,
an internal counter counts clock pulses when in current limit.
When the counter detects 256 consecutive clock cycles, the
regulator enters a low power dissipation hiccup mode of cur-
rent limit. The regulator is shut down by momentarily pulling
UVLO low, and the soft-start capacitor discharged. The reg-
ulator is restarted with a full soft-start cycle once UVLO
charges back to 1.215V. This process is repeated until the
fault is removed. The hiccup off-time can be controlled by a
capacitor to ground on the UVLO pin. In applications with low
output inductance and high input voltage, the switch current
may overshoot due to the propagation delay of the current
limit comparator. If an overshoot should occur, the sample-
and-hold circuit will detect the excess recirculating current. If
the sample-and-hold DC level exceeds the internal current
limit threshold, the buck switch will be disabled and skip puls-
es until the current has decayed below the current limit thresh-
old. This approach prevents current runaway conditions due
to propagation delays or inductor saturation since the inductor
current is forced to decay following any current overshoot.
30007543
FIGURE 8. Current Limit and Ramp Circuit
Using a current sense resistor in the source of the low-side
MOSFET provides superior current limit accuracy compared
to RDS(ON) sensing. RDS(ON) sensing is far less accurate due
to the large variation of MOSFET RDS(ON) with temperature
and part-to-part variation. The CS and CSG pins should be
Kelvin connected to the current sense resistor or MOSFET
drain and source.
This has the effect of a 10% fold-back of the peak current
during a short circuit when VCCX is powered from a 5V out-
put.
Soft-Start and Diode Emulation
The soft-start feature allows the regulator to gradually reach
the initial steady state operating point, thus reducing start-up
stresses and surges. The LM5116 will regulate the FB pin to
the SS pin voltage or the internal 1.215V reference, whichever
is lower. At the beginning of the soft-start sequence when SS
= 0V, the internal 10µA soft-start current source gradually in-
The peak current which triggers the current limit comparator
is:
creases the voltage of an external soft-start capacitor (CSS
)
connected to the SS pin resulting in a gradual rise of FB and
the output voltage.
Where tON is the on-time of the high-side MOSFET. The 1.1V
threshold is the difference between the 1.6V reference at the
current limit comparator and the 0.5V offset at the current
sense amplifier. This offset at the current sense amplifier al-
lows the inductor ripple current to go negative by 0.5V / (A x
RS) when running full synchronous operation.
Current limit hysteresis prevents chatter around the threshold
when VCCX is powered from VOUT. When 4.5V < VCC <
5.8V, the 1.6V reference is increased to 1.72V. The peak cur-
rent which triggers the current limit comparator becomes:
30007544
FIGURE 9. Diode Emulation Control
15
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During this initial charging of CSS to the internal reference
voltage, the LM5116 will force diode emulation. That is, the
low-side MOSFET will turn off for the remainder of a cycle if
the sensed inductor current becomes negative. The inductor
current is sensed by monitoring the voltage between SW and
DEMB. As the SS capacitor continues to charge beyond
1.215V to 3V, the DEMB bias current will increase from 0µA
up to 40µA. With the use of an external DEMB resistor
(RDEMB), the current sense threshold for diode emulation will
increase resulting in the gradual transition to synchronous
operation. Forcing diode emulation during soft-start allows
the LM5116 to start up into a pre-biased output without un-
necessarily discharging the output capacitor. Full syn-
chronous operation is obtained if the DEMB pin is always
biased to a higher potential than the SW pin when LO is high.
RDEMB = 10kΩ will bias the DEMB pin to 0.45V minimum,
which is adequate for most applications. The DEMB bias po-
tential should always be kept below 2V. At very light loads
with larger values of output inductance and MOSFET capac-
itance, the switch voltage may fall slowly. If the SW voltage
does not fall below the DEMB threshold before the end of the
HO fall to LO rise dead-time, switching will default to diode
emulation mode. When RDEMB = 0Ω, the LM5116 will always
run in diode emulation.
Application Information
EXTERNAL COMPONENTS
The procedure for calculating the external components is il-
lustrated with the following design example. The Bill of Mate-
rials for this design is listed in Table 1. The circuit shown in
Figure 16 is configured for the following specifications:
•
•
•
•
Output voltage = 5V
Input voltage = 7V to 60V
Maximum load current = 7A
Switching frequency = 250kHz
Simplified equations are used as a general guideline for the
design method. Comprehensive equations are provided at
the end of this section.
TIMING RESISTOR
RT sets the oscillator switching frequency. Generally, higher
frequency applications are smaller but have higher losses.
Operation at 250kHz was selected for this example as a rea-
sonable compromise for both small size and high efficiency.
The value of RT for 250kHz switching frequency can be cal-
culated as follows:
Once SS charges to 3V the SS latch is set, increasing the
DEMB bias current to 65µA. An amplifier is enabled that reg-
ulates SS to 160mV above the FB voltage. This feature can
prevent overshoot of the output voltage in the event the output
voltage momentarily dips out of regulation. When a fault is
detected (VCC under-voltage, UVLO pin < 1.215, or EN = 0V)
the soft-start capacitor is discharged. Once the fault condition
is no longer present, a new soft-start sequence begins.
The nearest standard value of 12.4kΩ was chosen for RT.
OUTPUT INDUCTOR
The inductor value is determined based on the operating fre-
quency, load current, ripple current and the input and output
voltages.
HO Ouput
The LM5116 contains a high current, high-side driver and as-
sociated high voltage level shift. This gate driver circuit works
in conjunction with an external diode and bootstrap capacitor.
A 1 µF ceramic capacitor, connected with short traces be-
tween the HB pin and SW pin, is recommended. During the
off-time of the high-side MOSFET, the SW pin voltage is ap-
proximately -0.5V and the bootstrap capacitor charges from
VCC through the external bootstrap diode. When operating
with a high PWM duty cycle, the buck switch will be forced off
each cycle for 450 ns to ensure that the bootstrap capacitor
is recharged.
The LO and HO outputs are controlled with an adaptive dead-
time methodology which insures that both outputs are never
enabled at the same time. When the controller commands HO
to be enabled, the adaptive block first disables LO and waits
for the LO voltage to drop below approximately 25% of VCC.
HO is then enabled after a small delay. Similarly, when HO
turns off, LO waits until the SW voltage has fallen to ½ of VCC.
LO is then enabled after a small delay. In the event that SW
does not fall within approximately 150 ns, LO is asserted high.
This methodology insures adequate dead-time for any size
MOSFET.
30007545
FIGURE 10. Inductor Current
Knowing the switching frequency (fSW), maximum ripple cur-
rent (IPP), maximum input voltage (VIN(MAX)) and the nominal
output voltage (VOUT), the inductor value can be calculated:
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event the maximum junction temper-
ature is exceeded. When activated, typically at 170°C, the
controller is forced into a low power reset state, disabling the
output driver and the bias regulator. This is designed to pre-
vent catastrophic failures from accidental device overheating.
The maximum ripple current occurs at the maximum input
voltage. Typically, IPP is 20% to 40% of the full load current.
When running diode emulation mode, the maximum ripple
current should be less than twice the minimum load current.
For full synchronous operation, higher ripple current is ac-
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16
ceptable. Higher ripple current allows for a smaller inductor
size, but places more of a burden on the output capacitor to
smooth the ripple current for low output ripple voltage. For this
example, 40% ripple current was chosen for a smaller sized
inductor.
The next lowest standard value of 270pF was selected for
CRAMP. A COG type capacitor with 5% or better tolerance is
recommended.
OUTPUT CAPACITORS
The output capacitors smooth the inductor ripple current and
provide a source of charge for transient loading conditions.
For this design example, five 100µF ceramic capacitors
where selected. Ceramic capacitors provide very low equiv-
alent series resistance (ESR), but can exhibit a significant
reduction in capacitance with DC bias. From the
manufacturer’s data, the ESR at 250kHz is 2mΩ / 5 =
0.4mΩ, with a 36% reduction in capacitance at 5V. This is
verified by measuring the output ripple voltage and frequency
response of the circuit. The fundamental component of the
output ripple voltage is calculated as:
The nearest standard value of 6µH will be used. The inductor
must be rated for the peak current to prevent saturation. Dur-
ing normal operation, the peak current occurs at maximum
load current plus maximum ripple. During overload conditions
with properly scaled component values, the peak current is
limited to VCS(TH) / RS (See next section). At the maximum
input voltage with a shorted output, the valley current must fall
below VCS(TH) / RS before the high-side MOSFET is allowed
to turn on. The peak current in steady state will increase to
VIN(MAX) x tON(min) / L above this level. The chosen inductor
must be evaluated for this condition, especially at elevated
temperature where the saturation current rating may drop sig-
nificantly.
CURRENT SENSE RESISTOR
The current limit is set by the current sense resistor value
(RS).
With typical values for the 5V design example:
For a 5V output, the maximum current sense signal occurs at
the minimum input voltage, so RS is calculated from:
INPUT CAPACITORS
The regulator supply voltage has a large source impedance
at the switching frequency. Good quality input capacitors are
necessary to limit the ripple voltage at the VIN pin while sup-
plying most of the switch current during the on-time. When the
buck switch turns on, the current into the switch steps to the
valley of the inductor current waveform, ramps up to the peak
value, and then drops to zero at turn-off. The input capacitors
should be selected for RMS current rating and minimum ripple
voltage. A good approximation for the required ripple current
rating is IRMS > IOUT / 2.
For this example VCCX = 0V, so VCS(TH) = 0.11V. The current
sense resistor is calculated as:
Quality ceramic capacitors with a low ESR were selected for
the input filter. To allow for capacitor tolerances and voltage
rating, four 2.2µF, 100V ceramic capacitors were used for the
typical application circuit. With ceramic capacitors, the input
ripple voltage will be triangular and peak at 50% duty cycle.
Taking into account the capacitance change with DC bias, the
input ripple voltage is approximated as:
The next lowest standard value of 10mΩ was chosen for RS.
RAMP CAPACITOR
With the inductor and sense resistor value selected, the value
of the ramp capacitor (CRAMP) necessary for the emulation
ramp circuit is:
When the converter is connected to an input power source, a
resonant circuit is formed by the line impedance and the input
capacitors. If step input voltage transients are expected near
the maximum rating of the LM5116, a careful evaluation of the
ringing and possible overshoot at the device VIN pin should
be completed. To minimize overshoot make CIN > 10 x LIN.
The characteristic source impedance and resonant frequency
are:
Where L is the value of the output inductor in Henrys, gm is
the ramp generator transconductance (5µA/V), and A is the
current sense amplifier gain (10V/V). For the 5V output design
example, the ramp capacitor is calculated as:
17
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SOFT START CAPACITOR
The capacitor at the SS pin (CSS) determines the soft-start
time, which is the time for the reference voltage and the output
voltage to reach the final regulated value. The soft-start time
tSS should be substantially longer than the time required to
charge COUT to VOUT at the maximum output current. To meet
this requirement:
The converter exhibits a negative input impedance which is
lowest at the minimum input voltage:
tSS > VOUT x COUT / (ICURRENT LIMIT – IOUT
)
The value of CSS for a given time is determined from:
The damping factor for the input filter is given by:
For this application, a value of 0.01µF was chosen for a soft-
start time of 1.2ms.
OUTPUT VOLTAGE DIVIDER
Where RIN is the input wiring resistance and ESR is the series
resistance of the input capacitors. The term ZS / ZIN will always
be negative due to ZIN.
RFB1 and RFB2 set the output voltage level, the ratio of these
resistors is calculated from:
When δ = 1, the input filter is critically damped. This may be
difficult to achieve with practical component values. With δ <
0.2, the input filter will exhibit significant ringing. If δ is zero or
negative, there is not enough resistance in the circuit and the
input filter will sustain an oscillation. When operating near the
minimum input voltage, an aluminum electrolytic capacitor
across CIN may be needed to damp the input for a typical
bench test setup. Any parallel capacitor should be evaluated
for its RMS current rating. The current will split between the
ceramic and aluminum capacitors based on the relative
impedance at the switching frequency.
RFB1 is typically 1.21kΩ for a divider current of 1mA. The di-
vider current can be reduced to 100µA with RFB1=12.1kΩ. For
the 5V output design example used here, RFB1 = 1.21kΩ and
RFB2 = 3.74kΩ.
UVLO DIVIDER
A voltage divider and filter can be connected to the UVLO pin
to set a minimum operating voltage VIN(MIN) for the regulator.
If this feature is required, the following procedure can be used
to determine appropriate resistor values for RUV2, RUV1 and
VCC CAPACITOR
The primary purpose of the VCC capacitor (CVCC) is to supply
the peak transient currents of the LO driver and bootstrap
diode (D1) as well as provide stability for the VCC regulator.
These current peaks can be several amperes. The recom-
mended value of CVCC should be no smaller than 0.47µF, and
should be a good quality, low ESR, ceramic capacitor located
at the pins of the IC to minimize potentially damaging voltage
transients caused by trace inductance. A value of 1µF was
selected for this design.
CFT
.
1. RUV2 must be large enough such that in the event of a
current limit, the internal UVLO switch can pull UVLO <
200mV. This can be guaranteed if:
RUV2 > 500 x VIN(MAX)
Where VIN(MAX) is the maximum input voltage and RUV2
is in ohms.
2. 2. With an appropriate value for RUV2, RUV1 can be
selected using the following equation:
BOOTSTRAP CAPACITOR
The bootstrap capacitor (CHB) between the HB and SW pins
supplies the gate current to charge the high-side MOSFET
gate at each cycle’s turn-on as well as supplying the recovery
charge for the bootstrap diode (D1). These current peaks can
be several amperes. The recommended value of the boot-
strap capacitor is at least 0.1µF, and should be a good quality,
low ESR, ceramic capacitor located at the pins of the IC to
minimize potentially damaging voltage transients caused by
trace inductance. The absolute minimum value for the boot-
strap capacitor is calculated as:
Where VIN(MIN) is the desired shutdown voltage.
3. Capacitor CFT provides filtering for the divider and
determines the off-time of the “hiccup” duty cycle during
current limit. When CFT is used in conjunction with the
voltage divider, a diode across the top resistor should be
used to discharge CFT in the event of an input under-
voltage condition.
Where Qg is the high-side MOSFET gate charge and ΔVHB is
the tolerable voltage droop on CHB, which is typically less than
5% of VCC. A value of 1µF was selected for this design.
If under-voltage shutdown is not required, RUV1 and RUV2 can
be eliminated and the off-time becomes:
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18
fall times of 10ns and 12ns respectively. In applications where
a high step-down ratio is maintained for normal operation, ef-
ficiency may be optimized by choosing a high-side MOSFET
with lower Qg, and low-side MOSFET with lower RDS(ON)
.
The voltage at the UVLO pin should never exceed 16V when
using an external set-point divider. It may be necessary to
clamp the UVLO pin at high input voltages. For the design
example, RUV2 = 102kΩ and RUV1 = 21kΩ for a shut-down
voltage of 6.6V. If sustained short circuit protection is re-
quired, CFT ≥ 1µF will limit the short circuit power dissipation.
For higher voltage MOSFETs which are not true logic level, it
is important to use the UVLO feature. Choose a minimum op-
erating voltage which is high enough for VCC and the boot-
strap (HB) supply to fully enhance the MOSFET gates. This
will prevent operation in the linear region during power-on or
power-off which can result in MOSFET failure. Similar con-
sideration must be made when powering VCCX from the
output voltage. For the high-side MOSFET, the gate threshold
should be considered and careful evaluation made if the gate
threshold voltage exceeds the HO driver UVLO.
D2 may be installed when using CFT with RUV1 and RUV2
.
MOSFETs
Selection of the power MOSFETs is governed by the same
tradeoffs as switching frequency. Breaking down the losses
in the high-side and low-side MOSFETs is one way to deter-
mine relative efficiencies between different devices. When
using discrete SO-8 MOSFETs the LM5116 is most efficient
for output currents of 2A to 10A. Losses in the power MOS-
FETs can be broken down into conduction loss, gate charging
loss, and switching loss. Conduction, or I2R loss PDC, is ap-
proximately:
MOSFET SNUBBER
A resistor-capacitor snubber network across the low-side
MOSFET reduces ringing and spikes at the switching node.
Excessive ringing and spikes can cause erratic operation and
couple spikes and noise to the output. Selecting the values
for the snubber is best accomplished through empirical meth-
ods. First, make sure the lead lengths for the snubber con-
nections are very short. Start with a resistor value between
5Ω and 50Ω. Increasing the value of the snubber capacitor
results in more damping, but higher snubber losses. Select a
minimum value for the snubber capacitor that provides ade-
quate damping of the spikes on the switch waveform at high
load.
PDC(HO-MOSFET) = D x (IO2 x RDS(ON) x 1.3)
PDC(LO-MOSFET) = (1 - D) x (IO2 x RDS(ON) x 1.3)
Where D is the duty cycle. The factor 1.3 accounts for the
increase in MOSFET on-resistance due to heating. Alterna-
tively, the factor of 1.3 can be ignored and the on-resistance
of the MOSFET can be estimated using the RDS(ON) vs Tem-
perature curves in the MOSFET datasheet. Gate charging
loss, PGC, results from the current driving the gate capaci-
tance of the power MOSFETs and is approximated as:
ERROR AMPLIFIER COMPENSATION
RCOMP, CCOMP and CHF configure the error amplifier gain
characteristics to accomplish a stable voltage loop gain. One
advantage of current mode control is the ability to close the
PGC = n x VCC x Qg x fSW
loop with only two feedback components, RCOMP and CCOMP
.
Qg refer to the total gate charge of an individual MOSFET,
and ‘n’ is the number of MOSFETs. If different types of MOS-
FETs are used, the ‘n’ term can be ignored and their gate
charges summed to form a cumulative Qg. Gate charge loss
differs from conduction and switching losses in that the actual
dissipation occurs in the LM5116 and not in the MOSFET it-
self. Further loss in the LM5116 is incurred as the gate driving
current is supplied by the internal linear regulator. The gate
drive current supplied by the VCC regulator is calculated as:
The voltage loop gain is the product of the modulator gain and
the error amplifier gain. For the 5V output design example,
the modulator is treated as an ideal voltage-to-current con-
verter. The DC modulator gain of the LM5116 can be modeled
as:
DC Gain(MOD) = RLOAD / (A x RS)
The dominant low frequency pole of the modulator is deter-
mined by the load resistance (RLOAD) and output capacitance
(COUT). The corner frequency of this pole is:
IGC = VCC x (Qgh + Qgl) x fSW
fP(MOD) = 1 / (2π x RLOAD x COUT
For RLOAD = 5V / 7A = 0.714Ω and COUT = 320µF (effective)
then fP(MOD) = 700Hz
)
Where Qgh + Qgl represent the gate charge of the HO and LO
MOSFETs at VGS = VCC. To ensure start-up, IGC should be
less than the VCC current limit rating of 15mA minimum when
powered by the internal 7.4V regulator. Failure to observe this
rating may result in excessive MOSFET heating and potential
damage. The IGC run current may exceed 15 mA when VCC
is powered by VCCX.
DC Gain(MOD) = 0.714Ω / (10 x 10mΩ) = 7.14 = 17dB
For the 5V design example the modulator gain vs. frequency
characteristic was measured as shown in Figure 11.
PSW = 0.5 x VIN x IO x (tR + tF) x fSW
Where tR and tF are the rise and fall times of the MOSFET.
Switching loss is calculated for the high-side MOSFET only.
Switching loss in the low-side MOSFET is negligible because
the body diode of the low-side MOSFET turns on before the
MOSFET itself, minimizing the voltage from drain to source
before turn-on. For this example, the maximum drain-to-
source voltage applied to either MOSFET is 60V. VCC pro-
vides the drive voltage at the gate of the MOSFETs. The
selected MOSFETs must be able to withstand 60V plus any
ringing from drain to source, and be able to handle at least
VCC plus ringing from gate to source. A good choice of MOS-
FET for the 60V input design example is the Si7850DP. It has
an RDS(ON) of 20 mΩ, total gate charge of 14nC, and rise and
19
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30007565
30007563
FIGURE 13. Overall Voltage Loop Gain and Phase
FIGURE 11. Modulator Gain and Phase
If a network analyzer is available, the modulator gain can be
measured and the error amplifier gain can be configured for
the desired loop transfer function. If a network analyzer is not
available, the error amplifier compensation components can
be designed with the guidelines given. Step load transient
tests can be performed to verify acceptable performance. The
step load goal is minimum overshoot with a damped re-
sponse. CHF can be added to the compensation network to
decrease noise susceptibility of the error amplifier. The value
of CHF must be sufficiently small since the addition of this ca-
pacitor adds a pole in the error amplifier transfer function. This
pole must be well beyond the loop crossover frequency. A
good approximation of the location of the pole added by CHF
is: fP2 = fZEA x CCOMP / CHF. The value of CHF was selected as
100pF for the design example.
Components RCOMP and CCOMP configure the error amplifier
as a type II configuration. The DC gain of the amplifier is 80dB
which has a pole at low frequency and a zero at fZEA = 1 /
(2π x RCOMP x CCOMP). The error amplifier zero cancels the
modulator pole leaving a single pole response at the
crossover frequency of the voltage loop. A single pole re-
sponse at the crossover frequency yields a very stable loop
with 90° of phase margin. For the design example, a target
loop bandwidth (crossover frequency) of one-tenth the
switching frequency or 25kHz was selected. The compensa-
tion network zero (fZEA) should be selected at least an order
of magnitude less than the target crossover frequency. This
constrains the product of RCOMP and CCOMP for a desired
compensation network zero 1 / (2π x RCOMP x CCOMP) to be
2.5kHz. Increasing RCOMP, while proportionally decreasing
CCOMP, increases the error amp gain. Conversely, decreasing
RCOMP while proportionally increasing CCOMP, decreases the
error amp gain. For the design example CCOMP was selected
as 3300pF and RCOMP was selected as 18kΩ. These values
configure the compensation network zero at 2.7kHz. The er-
PCB LAYOUT AND THERMAL CONSIDERATIONS
In a buck regulator the primary switching loop consists of the
input capacitor, MOSFETs and current sense resistor. Mini-
mizing the area of this loop reduces the stray inductance and
minimizes noise and possible erratic operation. The input ca-
pacitor should be placed as close as possible to the MOS-
FETs, with the VIN side of the capacitor connected directly to
the high-side MOSFET drain, and the GND side of the ca-
pacitor connected as close as possible to the low-side source
or current sense resistor ground connection. A ground plane
in the PC board is recommended as a means to connect the
quiet end (input voltage ground side) of the input filter capac-
itors to the output filter capacitors and the PGND pin of the
regulator. Connect all of the low power ground connections
(CSS, RT, CRAMP) directly to the regulator AGND pin. Connect
the AGND and PGND pins together through to a topside cop-
per area covering the entire underside of the device. Place
several vias in this underside copper area to the ground plane.
ror amp gain at frequencies greater than fZEA is: RCOMP
RFB2, which is approximately 4.8 (13.6dB).
/
The highest power dissipating components are the two power
MOSFETs. The easiest way to determine the power dissipat-
ed in the MOSFETs is to measure the total conversion losses
(PIN - POUT), then subtract the power losses in the output in-
ductor and any snubber resistors. The resulting power losses
are primarily in the switching MOSFETs.
30007564
If a snubber is used, the power loss can be estimated with an
oscilloscope by observation of the resistor voltage drop at
both turn-on and turn-off transitions. Assuming that the RC
FIGURE 12. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in
dB) of the modulator gain and the error amp gain.
time constant is << 1 / fSW
.
P = C x V2 x fSW
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20
The regulator has an exposed thermal pad to aid power dis-
sipation. Selecting MOSFETs with exposed pads will aid the
power dissipation of these devices. Careful attention to RDS
(ON) at high temperature should be observed. Also, at 250 kHz,
a MOSFET with low gate capacitance will result in lower
switching losses.
Calculate VRAMP at the nominal input voltage.
For VOUT > 7.5V, install a resistor from the RAMP pin to VCC.
Comprehensive Equations
CURRENT SENSE RESISTOR AND RAMP CAPACITOR
T = 1 / fSW, gm = 5µA/V, A = 10V/V. IOUT is the maximum output
current at current limit.
General Method for VOUT < 5V:
30007573
FIGURE 14. RRAMP to VCC for VOUT > 7.5V
For VOUT < 7.5V, a negative VCC is required. This can be
made with a simple charge pump from the LO gate output.
Install a resistor from the RAMP pin to the negative VCC.
General Method for 5V < VOUT < 7.5V:
Best Performance Method:
This minimizes the current limit deviation due to changes in
line voltage, while maintaining near optimal slope compen-
sation.
30007575
FIGURE 15. RRAMP to -VCC for VOUT < 7.5V
Calculate optimal slope current, IOS = (VOUT / 3) x 10µA/V. For
example, at VOUT = 7.5V, IOS = 25µA.
If a large variation is expected in VCC, say for VIN < 11V, a
Zener regulator may be added to supply a constant voltage
for RRAMP
.
21
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MODULATOR TRANSFER FUNCTION
sampling gain is characterized by ωn and Q, which accounts
for the high frequency inductor pole.
The following equations can be used to calculate the control-
to-output transfer function:
For VSL without RRAMP, use IOS = 25 µA
For VSL with RRAMP to VCC, use IOS = 25 µA + VCC/RRAMP
For VSL with RRAMP to -VCC, use IOS = 25 µA - VCC/RRAMP
ERROR AMPLIFIER TRANSFER FUNCTION
The following equations are used to calculate the error am-
plifier transfer function:
Km is the effective DC gain of the modulating comparator. The
duty cycle D = VOUT / VIN. KSL is the proportional slope com-
pensation term. VSL is the fixed slope compensation term.
Slope compensation is set by mc, which is the ratio of the ex-
ternal ramp to the natural ramp. The switching frequency
Where AOL = 10,000 (80dB) and ωBW = 2π x fBW. GEA(S) is the
ideal error amplifier gain, which is modified at DC and high
frequency by the open loop gain of the amplifier and the feed-
back divider ratio.
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22
23
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TABLE 1. Bill of Materials for 7V-60V Input, 5V 7A Output, 250kHz
ID
C1, C2, C14
C3
Part Number
Type
Size
0805
0603
0603
0603
Parameters
1µF, 25V, X7R
Qty
3
Vendor
TDK
C2012X7R1E105K
VJ0603Y103KXAAT
VJ0603A271JXAAT
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
0.01µF, 50V, X7R
270pF, 50V, COG, 5%
100pF, 50V, X7R
1
Vishay
Vishay
Vishay
C4
1
C5, C15
VJ0603Y101KXAT
W1BC
2
C6
C7
VJ0603Y332KXXAT
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
0603
0603
1812
3300pF, 25V, X7R
Not Used
1
0
4
Vishay
TDK
C8, C9, C10,
C11
C4532X7R2A225M
2.2µF, 100V X7R
C12
C13
C3225X7R2A105M
C2012X7R2A104M
Capacitor, Ceramic
Capacitor, Ceramic
Capacitor, Ceramic
1210
0805
1812
1µF, 100V X7R
0.1µF, 100V X7R
1
1
5
TDK
TDK
TDK
C16, C17, C18, C4532X6S0J107M
C19, C20
100µF, 6.3V, X6S, 105°C
C21, C22
C23
Capacitor, Tantalum
Capacitor, Ceramic
Diode, Switching
D Case
0805
Not Used
Not Used
0
0
1
D1
CMPD2003
CMPD2003
SOT-23
200mA, 200V
Central
Semi
D2
Diode, Switching
SOT-23
Not Used
0
Central
Semi
JMP1
L1
Connector, Jumper
Inductor
2 pin sq. post
6µH, 16.5A
1
1
4
5
2
HC2LP-6R0
1514-2
Cooper
Keystone
Keystone
P1-P4
TP1-TP5
Q1, Q2
Turret Terminal
Test Point
.090” dia.
.040” dia.
5012
Si7850DP
N-CH MOSFET
SO-8 Power PAK
10.3A, 60V
Vishay
Siliconix
R1
R2
CRCW06031023F
CRCW06032102F
CRCW06033741F
CRCW06031211F
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
0603
0603
0603
0603
0603
0603
0603
0603
0603
2010
1
1
1
1
0
2
1
1
1
1
Vishay
Vishay
Vishay
Vishay
102kΩ, 1%
21.0kΩ, 1%
3.74kΩ, 1%
1.21kΩ, 1%
Not Used
0Ω
R3
R4
R5
R6, R7
R8
CRCW06030R0J
CRCW0603103J
CRCW06031242F
CRCW0603183J
Vishay
Vishay
Vishay
Vishay
IRC
10kΩ, 5%
12.4kΩ, 1%
18kΩ, 5%
0.010Ω, 1%
R9
R10
R11
LRC-LRF2010-01-
R010-F
R12
R13
R14
U1
Resistor
Resistor
Resistor
0603
0603
Not Used
1MΩ, 5%
Not Used
0
1
0
1
CRCW0603105J
LM5116MHX
Vishay
NSC
1206
Synchronous Buck
Controller
TSSOP-20EP
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24
Physical Dimensions inches (millimeters) unless otherwise noted
TSSOP-20EP Outline Drawing
NS Package Number MXA20A
25
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