LM3370 [NSC]
Dual Synchronous Step-Down DC-DC Converter with Dynamic Voltage Scaling Function; 双路同步降压型DC - DC转换器的动态电压缩放功能
| 型号： | LM3370 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual Synchronous Step-Down DC-DC Converter with Dynamic Voltage Scaling Function |
| 文件： | 总23页 (文件大小：1958K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
December 2005
LM3370
Dual Synchronous Step-Down DC-DC Converter with
Dynamic Voltage Scaling Function
General Description
Features
n I2C compatible interface
LM3370 is a dual step-down DC-DC converter optimized for
powering an ultra-low voltage circuits from a single Li-Ion
battery and input rail ranging from 2.7V to 5.5V. It provides
two outputs with 600mA load per channel. The output volt-
age range varies from 1V to 3.3V and can be dynamically
controlled using the I2C compatible interface. This dynamic
voltage scaling function allows processors to achieve maxi-
mum performance at the lowest power level. The I2C com-
patible interface can also be used to control auto PFM-PWM/
PWM mode selection and other performance enhancing
features.
— VOUT1 = 1V to 2V in 50mV steps
— VOUT2 = 2.3V to 3.3V in 100mV steps
— Automatic PFM/PWM mode switching & Forced PWM
mode for low noise operation
— Spread Spectrum capability using I2C
n 600mA load per channel
n 2MHz PWM fixed switching frequency (typ.)
n Internal synchronous rectification for high efficiency
n Internal soft start
n Power-on-reset function for both outputs
The LM3370 offers superior features and performance for
portable systems with complex power management require-
ments. Automatic intelligent switching between PWM low-
noise and PFM low-current mode offers improved system
efficiency. Internal synchronous rectification enhances the
converter efficiency without the use of futher external device.
n 2.7V ≤ VIN ≤ 5.5V
n Operates from a single Li-Ion cell or 3 cell NiMH/NiCd
batteries and 3.3V/5.5V fixed rails
n 2.2µH Inductor, 4.7µF Input and 10µF Output Capacitor
per channel
n 16-lead LLP Package (4mm x 5mm x 0.8mm)
There is a power-on-reset function that monitors the level of
the output voltage to avoid unexpected power losses. The
independent enable pin for each output allows for simple and
effective power sequencing.
Applications
n Baseband Processors
n Application Processors (Video, Audio)
n I/O Power
LM3370 is available in a 4mm by 5mm 16-lead non-pullback
LLP package.
A
high switching frequency—2MHz
(typ)—allows use of tiny surface-mount components includ-
ing a 2.2µH inductor.
n FPGA Power and CPLD
Default fixed voltages for the 2 voltage outputs can be
customized to fit system requirements by contacting National
Semiconductor Corporation.
© 2005 National Semiconductor Corporation
DS201673
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Typical Application
20167301
FIGURE 1. Typical Application Circuit
Functional Block Diagram
20167302
FIGURE 2. Functional Diagram
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2
Package Marking Information
16-Lead LLP Package
20167343
FIGURE 3. Top Marking
20167342
FIGURE 4. Top View
3
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Pin Descriptions
Pin #
Name
Description
1
VIN2
SW2
Main Battery Power Input for Buck 2
Buck 2 Switch Pin
2
3
PGND2
VDD
Buck 2 Power Ground
4
Analog and Digital VDD Battery Input
Analog GND
5
SGND
PGND1
SW1
6
Buck 1 Power Ground
7
Buck 1 Switch Pin
8
VIN1
Main Battery Power Input for Buck 1
Analog Feedback Input for Buck 1
9
FB1
10
11
12
SDA
I2C Compatible Data, a 2 kΩ pull up resistor is required.
I2C Compatible Clock, a 2 kΩ pull up resistor is required.
Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of
target output. A 100 kΩ pull up resistor is required
Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of
target output. A 100 kΩ pull up resistor is required
Buck 1 Enable
SCL
nPOR1
13
nPOR2
14
15
16
EN1
EN2
FB2
Buck 2 Enable
Analog feedback for Buck 2
I2C Controlled Features
Features
Parameter
VOUT1 & VOUT2
Comments
Output voltage is controlled via I2C compatible
Mode can be controlled via I2C
Output Voltage
Modes
Buck 1 & Buck 2
compatible by either forcing device
in Auto mode or forced PWM mode
Spread Spectrum
Buck 1 & Buck 2
Spread Spectrum capability via I2C compatible for noise reduction
Ordering Information
Order Number
LM3370SD-3013*
LM3370SDX-3013*
LM3370SD-3021
LM3370SDX-3021
LM3370SD-3416*
LM3370SDX-3416*
LM3370SD-4221*
LM3370SDX-4221*
Voltage Option
Package Marking
Supplied As
1.2V & 2.5V
250 units, Tape-and-Reel
3000 units, Tape and Reel
250 units, Tape-and-Reel
3000 units, Tape-and-Reel
250 units, Tape-and-Reel
3000 units, Tape-and-Reel
250 units, Tape-and-Reel
3000 units, Tape-and-Reel
1.2V & 3.3V
1.4V & 2.8V
1.8V & 3.3V
S0003TB
S0003TB
Note the LM3370SD-3013 has the following default output voltages where VOUT1 = 1.2V & VOUT2 = 2.5V
* Contact National Semiconductor for availability
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Absolute Maximum Ratings (Notes 1,
ESD Ratings (Note 5)
All Pins
2 kV HBM
200V MM
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Notes 1, 2)
Input Voltage Range ((Note 10))
VIN1 , VIN2 VDD to PGND &
2.7V to 5.5V
0mA to 600mA
−30˚C to +125˚C
SGND
−0.2V to 6V
Recommended Load Current Per Channel
Junction Temperature (TJ) Range
PGND to SGND
-0.2V to +0.2V
SDA, SCL, EN, EN2, nPOR1,
nPOR2, SW1, SW2, FB1 &
FB2
Ambient Temperature (TA) Range (Note 6) −30˚C to +85˚C
(GND - 0.2) to (VIN
+
0.2V)
Thermal Properties (Note 7)
Junction-to-Ambient Thermal Resistance
Maximum Continuous Power
Dissipation (PD_MAX) (Note 3)
Internally Limited
125˚C
Junction Temperature (TJ-MAX
Storage Temperature Range
Maximum Lead Temperature
(Soldering)
)
(θJA
)
26˚C/W
−65˚C to +150˚C
(Note 4)
Electrical Characteristics (Notes 2, 8, 10)Typical limits appearing in normal type apply for TJ = 25˚C. Lim-
its appearing in boldface type apply over the entire junction temperature range (TA = TJ = −30˚C to +85˚C). Unless otherwise
noted, VIN1 = VIN2 = 3.6V.
Symbol
VFB
Parameter
Feedback Voltage
Conditions
Min
-3.5
Typ
Max
+3.5
Units
%
(Note 11)
VOUT
Line Regulation
2.7V ≤ VIN ≤ 5.5V
0.031
0.0013
%/V
IO = 10mA, VOUT = 1.8V
100mA ≤ IO ≤ 600mA
VIN = 3.6V, VOUT = 1.8V
PFM Mode, Both Bucks ON
EN1 = EN2 = 0V
Load Regulation
%/mA
IQ PFM
IQ SD
ILIM
Quiescient Current “On”
Quiescient Current “Off”
Peak Switching Current Limit
PFET
34
0.2
µA
µA
3
1400
500
350
2.4
1
VIN = 3.6V
850
1.5
1.0
1200
390
240
2.0
mA
RDS_ON
VIN = 3.6V, ISW = 200mA
VIN = 3.6V, ISW = 200mA
mΩ
NFET
FOSC
IEN
Internal Oscillator Frequency
Enable (EN) Input Current
Enable Logic Low
MHz
µA
V
0.01
VIL
0.4
VIH
Enable Logic High
V
POWER ON RESET THRESHOLD/FUNCTION (POR)
nPOR1 &
nPOR2
nPOR1 = Power ON Reset
for Buck 1
50 mS (default)
50
mS
%
Delay Time
nPOR2 = Power ON Reset
for Buck 2
Can be pre-trimmd to 50 uS, 100
mS & 200 mS
POR
Percentage of Target VOUT
VOUT Rising
94
85
Threshold
VOUT Falling, 85% (default), Can
be pre-trimmed to 70% or 94%
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. The thermal shutdown engages at T = 150˚C (typ.) and disengages at
J
T
= 140˚C(typ.).
J
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP)
(AN-1187).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200 pF
capacitor discharged directly into each pin. (EAIJ)
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Electrical Characteristics (Notes 2, 8, 10)Typical limits appearing in normal type apply for TJ = 25˚C. Limits
appearing in boldface type apply over the entire junction temperature range (TA = TJ = −30˚C to +85˚C). Unless otherwise
noted, VIN1 = VIN2 = 3.6V. (Continued)
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
de-rated. Maximum ambient temperature (T
) is dependent on the maximum operating junction temperature (T
= 125oC), the maximum power
A-MAX
J-MAX-OP
dissipation of the device in the application (P
), and the junction-to-ambient thermal resistance of the part/package in the application (θ ), as given by the
D-MAX
JA
following equation: T
= T
– (θ x P
).
A-MAX
J-MAX-OP
JA
D-MAX
Note 7: Junction-to-ambient thermal resistance (θ ) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
JA
standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2 x 1 array of thermal vias. Thickness of copper layers
are 2/1/1/2oz.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design.
The value of θ of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power
JA
dissipation exists (high V , high I
), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note
IN
OUT
1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
Note 8: Min. and Max are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during
production with T = 25˚C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying
J
statistical process control.
Note 9: Guaranteed by design.
Note 10: Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages:
V
IN
= 2.7V to 5.5V for 1V ≤ V
≤ 1.7V and for V
= 1.8V or greater, V = V
+ 1V
OUT
OUT
OUT
IN
or
V
IN,MIN
= I
* (R
+ R
) + V
DCR_INDUCTOR OUT
LOAD
DSON_PFET
Note 11: Test condition: for V
less than 2.5V, V = 3.6V; for V
greater than or equal to 2.5V, V = V
IN
+ 1V
OUT
OUT
IN
OUT
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Typical Performance Characteristics LM3370, Circuit of Figure1, VIN = 3.6V, VOUT1 = 1.5V & VOUT2
= 2.5V, L = 2,2µH (NR3015T2R2M), CIN = 4.7µF (0805) and COUT = 10µF (0805) & TA = 25˚C, unless otherwise noted.
IQ_PFM (Non Switching)
Both Channels
IQ_PWM (Non Switching)
Both Channels
20167358
20167357
IQ_PWM (Switching)
Both Channels
IQ_SD (EN1 = EN2 = 0V)r
20167359
20167349
RDS_ON (PFET) vs Temperature
VIN = 3.6V
RDS_ON (NFET) vs Temperature
VIN = 3.6V
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20167347
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Typical Performance Characteristics LM3370, Circuit of Figure1, VIN = 3.6V, VOUT1 = 1.5V & VOUT2
= 2.5V, L = 2,2µH (NR3015T2R2M), CIN = 4.7µF (0805) and COUT = 10µF (0805) & TA = 25˚C, unless otherwise
noted. (Continued)
RDS_ON vs VIN
Current Limit vs VIN
20167348
20167353
Output Voltage vs Output Current
VIN = 3.6V (Forced PWM)
Switching Frequency vs VIN
20167360
20167370
Efficiency vs Output Current
Forced PWM Mode, VOUT1 = 1.2V
Efficiency vs Output Current
Auto Mode, VOUT1 = 1.2V
20167362
20167361
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Typical Performance Characteristics LM3370, Circuit of Figure1, VIN = 3.6V, VOUT1 = 1.5V & VOUT2
= 2.5V, L = 2,2µH (NR3015T2R2M), CIN = 4.7µF (0805) and COUT = 10µF (0805) & TA = 25˚C, unless otherwise
noted. (Continued)
Efficiency vs Output Current
Auto Mode, VOUT1 = 1.8V
Efficiency vs Output Current
Forced PWM Mode, VOUT1 = 1.8V
20167363
20167364
Efficiency vs Output Current
Auto Mode, VOUT2 = 3.3V
Efficiency vs Output Current
Forced PWM Mode, VOUT2 = 3.3V
20167367
20167366
Typical Operation Waveform
Typical Operation Waveform
VIN = 3.6V, VOUT1 = 1.8V & VOUT2 = 1.8V
Load = 400mA
VIN = 4.8V, VOUT1 = 1V & VOUT2 = 3.3V
Load = 400mA
20167320
20167321
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Typical Performance Characteristics LM3370, Circuit of Figure1, VIN = 3.6V, VOUT1 = 1.5V & VOUT2
= 2.5V, L = 2,2µH (NR3015T2R2M), CIN = 4.7µF (0805) and COUT = 10µF (0805) & TA = 25˚C, unless otherwise
noted. (Continued)
Typical Operation Waveform
VIN = 3.6V, VOUT1 = 1.5V, VOUT2 = 2.5V,
Load = 600mA Each
Start-up at PWM for BUCK1
( VIN = 3.6V, VOUT = 1.5V, Load = 200mA )
20167322
20167327
Start-up at PWM for BUCK2
( VIN = 3.6V, VOUT = 2.5V, Load = 200mA )
Line Transient
( VOUT1 = 1.2V )
20167330
20167325
Line Transient
( VOUT2 = 1.8V )
Load Transient in PFM MODE
( VOUT1 = 1.5V )
20167331
20167332
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Typical Performance Characteristics LM3370, Circuit of Figure1, VIN = 3.6V, VOUT1 = 1.5V & VOUT2
= 2.5V, L = 2,2µH (NR3015T2R2M), CIN = 4.7µF (0805) and COUT = 10µF (0805) & TA = 25˚C, unless otherwise
noted. (Continued)
Load Transient in PFM MODE
( VOUT1 = 1.5V )
Load Transient in PFM MODE
( VOUT1 = 1.8V )
20167333
20167334
Load Transient in PWM MODE
( VIN = 3.6V, VOUT1 = 1.2V )
Load Transient in PFM MODE ( VOUT1 = 1.8V )
20167335
20167338
Load Transient in PWM MODE
( VIN = 3.6V, VOUT1 = 1.5V )
Load Transient in PWM MODE
( VIN = 3.6V, VOUT2 = 2.5V )
20167339
20167341
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Typical Performance Characteristics LM3370, Circuit of Figure1, VIN = 3.6V, VOUT1 = 1.5V & VOUT2
= 2.5V, L = 2,2µH (NR3015T2R2M), CIN = 4.7µF (0805) and COUT = 10µF (0805) & TA = 25˚C, unless otherwise
noted. (Continued)
Spread Spectrum Enabling
( VOUT Signal at 2 MHz)
VOUT Stepping
( From 1.8V to 3.3V )
20167371
20167375
VOUT Stepping
( From 3.3V to 1.8V )
20167372
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CURRENT LIMITING
Operation Description
A current limit feature allows the LM3370 to protect itself and
external components during overload conditions. PWM
mode implements cycle-by-cycle current limiting using an
internal comparator that trips at 1200mA (typ.). If the outputs
are shorted to ground the device enters a timed current limit
mode where the NFET is turned on for a longer duration until
the inductor current falls below a low threshold, ensuring
inductor has more time to decay, thereby preventing run-
away.
DEVICE INFORMATION
The LM3370, a dual high efficiency step down DC-DC con-
verter, delivers regulated voltages from input rails between
2.7V to 5.5V. Using voltage mode architecture with synchro-
nous rectification, the LM3370 has the ability to deliver up to
600mA per channel. The performance is optimized for sys-
tems where efficiency and space are critical.
There are three modes of operation depending on the cur-
rent required—PWM, PFM, and shutdown. PWM mode
handles loads of approximately 70mA or higher with 90%
efficiency or better. Lighter loads cause the device to auto-
matically switch into PFM mode to maintain high efficiency
with low supply current (IQ = 20µA typ.) per channel.
PFM OPERATION
At very light loads, the converter enters PFM mode and
operates with reduced switching frequency and supply cur-
rent to maintain high efficiency.
The part will automatically transition into PFM mode when
either of two conditions are true, for a duration of 32 or more
clock cycles:
The LM3370 can operate up to a 100% duty cycle (PFET
switch always on) for low drop out control of the output
voltage. In this way the output voltage will be controlled
down to the lowest possible input voltage.
1. The NFET current reaches zero.
2. The peak PFET switch current drops below the IMODE
level .
Additional features include soft-start, under voltage lock out,
current overload protection, and thermal overload protection.
CIRCUIT OPERATION
During the first portion of each switching cycle, the control
block in the LM3370 turns on the internal PFET switch. This
allows current to flow from the input through the inductor to
the output filter capacitor and load. The inductor limits the
current to a ramp with a slope of
Supply current during this PFM mode is less than 20µA per
channel, which allows the part to achieve high efficiency
under extremely light load conditions. When the output drops
below the ‘low’ PFM threshold, the cycle repeats to restore
the output voltage to ∼1.2% above the nominal PWM output
voltage.
If the load current should increase during PFM mode (see
Figure 5) causing the output voltage to fall below the ‘low2’
PFM threshold, the part will automatically transition into
fixed-frequency PWM mode.
by storing energy in a magnetic field. During the second
portion of each cycle, the controller turns the PFET switch
off, blocking current flow from the input, and then turns the
NFET synchronous rectifier on. The inductor draws current
from ground through the NFET to the output filter capacitor
and load, which ramps the inductor current down with a
slope of
During PFM operation, the converter positions the output
voltage slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The
PFM comparators sense the output voltage via the feedback
pin and control the switching of the output FETs such that the
output voltage ramps between 0.8% and 1.6% (typical)
above the nominal PWM output voltage. If the output voltage
is below the ‘high’ PFM comparator threshold, the PFET
power switch is turned on. It remains on until the output
voltage exceeds the ‘high’ PFM threshold or the peak current
exceeds the IPFM level set for PFM mode. The typical peak
current in PFM mode is:
The output filter stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across
the load.
PWM OPERATION
IPFM = 115mA + VIN/57Ω
During PWM operation the converter operates as a voltage-
mode controller with input voltage feed forward. This allows
the converter to achieve excellent load and line regulation.
The DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, feed forward in-
versely proportional to the input voltage is introduced.
Once the PFET power switch is turned off, the NFET power
switch is turned on until the inductor current ramps to zero.
When the NFET zero-current condition is detected, the
NFET power switch is turned off. If the output voltage is
below the ‘high’ PFM comparator threshold (see Figure 5),
the PFET switch is again turned on and the cycle is repeated
until the output reaches the desired level. Once the output
reaches the ‘high’ PFM threshold, the NFET switch is turned
on briefly to ramp the inductor current to zero and then both
output switches are turned off and the part enters an ex-
tremely low power mode.
INTERNAL SYNCHRONOUS RECTIFICATION
While in PWM mode, the LM3370 uses an internal NFET as
a synchronous rectifier to reduce rectifier forward voltage
drop and associated power loss. Synchronous rectification
provides a significant improvement in efficiency whenever
the output voltage is relatively low compared to the voltage
drop across an ordinary rectifier diode.
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LDO - LOW DROP OUT OPERATION
Operation Description (Continued)
FORCED PWM MODE
The LM3370 can operate at 100% duty cycle (no switching,
PFET switch completely on) for low drop out support of the
output voltage. In this way the output voltage will be con-
trolled down to the lowest possible input voltage. The mini-
mum input voltage needed to support the output voltage is
VIN,MIN = ILOAD*(RDSON,PFET + RINDUCTOR) + VOUT
The LM3370 auto mode can be bypassed by forcing the
device to operate in PWM mode, this can be implemented
through the I2C compatible interface; see Output Table on
page 19.
• ILOAD
load current
SOFT-START
• RDSON/PFET drain to source resistance of PFET switch in
the triode region
The LM3370 has a soft start circuit that limits in-rush current
during start up. Soft start is activated only if EN goes from
logic low to logic high after VIN reaches 2.7V.
• RINDUCTOR inductor resistance
20167303
FIGURE 5. Operation in PFM Mode and Transfer to PWM Mode
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I2C Compatible Interface Electrical Specifications
Unless otherwise noted, VBATT = 2.7V to 5.5V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −30˚C to +125˚C. (Notes 2, 8, 9)
Symbol
FCLK
Parameter
Conditions
Min
Typ
Max
Units
kHz
µS
Clock Frequency
400
tBF
Bus-Free Time between Start and Stop
Hold Time Repeated Start Condition
CLK Low Period
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
1.3
0.6
1.3
0.6
0.6
200
200
0.6
tHOLD
tCLKLP
tCLKHP
tSU
µS
µS
CLK High Period
µS
Set Up Time Repeated Start Condition
Data Hold Time
µS
tDATAHLD
tCLKSU
TSU
nS
Data Set Up Time
nS
Set Up Time for Start Condition
Maximum Pulse Width of Spikes that Must be
Suppressed by the Input Filter of Both DATA & CLK
signals.
µS
TTRANS
50
nS
VDD_I2C I2C Logic High Level
1
VIN
V
I2C COMPATIBLE DATA VALIDITY
I2C Compatible Interface
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
In I2C compatible mode, the SCL pin is used for the I2C clock
and the SDA pin is used for the I2C data. Both these signals
need a pull-up resistor according to I2C specification. The
values of the pull-up resistor are determined by the capaci-
tance of the bus (typ. ∼1.8k). Signal timing specifications are
according to the I2C bus specification. Maximum frequency
is 400 kHz.
20167306
I2C COMPATIBLE START AND STOP CONDITIONS
generates START and STOP bits. The I2C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I2C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I2C master always
20167307
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I2C Compatible Interface (Continued)
TRANSFERRING DATA
ceiver must pull down the SDA line during the 9th clock
pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte
has been received.
After the START condition, I2C master sends a chip address.
This address is seven bits long followed by an eighth bit
which is a data direction bit (R/W). For the eighth bit, a “0”
indicates a WRITE and a “1” indicates a READ. The second
byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte of data has to be followed by an
acknowledge bit. The acknowledge related clock pulse is
generated by the master. The transmitter releases the SDA
line (HIGH) during the acknowledge clock pulse. The re-
I2C Compatible Write Cycle
20167309
W = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated startxx=36h
However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the read
cycle waveform.
I2C Compatible Read Cycle
20167310
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16
Device Register Information
Register Information
Register Name
Location
Type
R/W
R/W
R/W
Function
Control
00
01
02
Control signal for Buck 1 and Buck 2
Buck 1
Output setting & Mode selection for Buck 1
Output setting & Mode selection for Buck 2 and POR disable
Buck 2
I2C CHIP ADDRESS INFORMATION
20167308
REGISTER 00
20167311
17
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Device Register Information
(Continued)
REGISTER 01
20167312
REGISTER 02
20167313
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18
Output Selection Table via I2C Programing
Buck Output Voltage Selection Codes
Buck Output Voltage Selection Codes
Data Code
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
Buck_1 (V)
NA
Buck_2 (V)
NA
Data Code
Buck_1 (V)
1.40
Buck_2 (V)
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
3.0
3.1
3.2
3.3
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
1.45
NA
NA
1.50
NA
NA
1.55
NA
NA
1.60
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
NA
1.65
2.3
1.70
2.4
1.75
2.5
1.80
2.6
1.85
2.7
1.90
2.8
1.95
2.9
2.00
19
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For low-cost applications, an unshielded bobbin inductor is
suggested. For noise critical applications, a toroidal or
shielded-bobbin inductor should be used. A good practice is
to lay out the board with overlapping footprints of both types
for design flexibility. This allows substitution of a low-noise
toroidal inductor, in the event that noise from low-cost bobbin
models is unacceptable.
Application Information
SETTING OUTPUT VOLTAGE VIA I2C Compatible
The outputs of the LM3370 can be programmed through
Buck 1 & Buck 2 registers via I2C. Buck 1 output voltage can
be dynamically adjusted between 1V to 2V in 50mV steps
and Buck 2 output voltage can be adjusted between 2.3V to
3.3V in 100mV steps. Please refer to voltage selection table
on page 19 for programming the desire output voltage. If the
I2C compatible feature is not used, the default output voltage
will be the pre-trimmed voltage. For example, LM3370SD-
3021 refers to 1.2V for Buck 1 and 3.3V for Buck 2.
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 4.7µF, 6.3V is sufficient for most
applications. A larger value may be used for improved input
voltage filtering. The input filter capacitor supplies current to
the PFET switch of the LM3370 in the first half of each cycle
and reduces voltage ripple imposed on the input power
source. A ceramic capacitor’s low ESR provides the best
noise filtering of the input voltage spikes due to this rapidly
changing current. Select an input filter capacitor with a surge
current rating sufficient for the power-up surge from the input
power source. The power-up surge current is approximately
the capacitor’s value (µF) times the voltage rise rate (V/µs).
Micro-Stepping:
The Micro-Stepping feature minimizes output voltage
overshoot/undershoot during large output transients or large
iumps in output voltage. If Micro-stepping is enabled through
I2C, the output voltage automatically ramps at 50mV per
step for Buck 1 and 100mV per step for Buck 2. The steps
are summarized as follow:
Buck 1: 50mV/step and 32µs/step
Buck 2: 100mV/step and 32µs/step
The input current ripple can be calculated as:
For example if changing Buck 1 voltage from 1V to 1.8V
yields 20 steps [(1.8 - 1)/ 0.05 = 20]. This translates to 640µs
[(20 x 32µs) = 640µs] needed to reach the final target
voltage.
INDUCTOR SELECTION
There are two main considerations when choosing an induc-
tor; the inductor should not saturate, and the inductor current
ripple is small enough to achieve the desired output voltage
ripple.
Below are some suggested inductor manufacturers include
but are not limited to:
There are two methods to choose the inductor current rating.
method 1:
The total current is the sum of the load and the inductor
ripple current. This can be written as
TABLE 1. Suggested Inductors and Suppliers
Model
Vendor
Coilcraft
Cooper
Dimensions
(mm)
ISAT
DO3314-222
LPO3310-222
SD3114-2R2
3.3 x 3.3 x 1.4
3.3 x 3.3 x 1.0
3.1 x 3.1 x 1.4
1.6A
1.1A
1.48A
1.1A
NR3010T2R2M Taiyo Yuden 3.0 x 3.0 x 1.0
NR3015T2R2M
VLF3010AT-
2R2M1R0
3.0 x 3.0 x 1.5
2.6 x 2.8 x 1.0
1.48A
1.0A
•
•
•
•
ILOAD load current
VIN input voltage
L inductor
TDK
f switching frequency
OUTPUT CAPACITOR SELECTION
method 2:
DC bias characteristics of ceramic capacitors must be con-
sidered when selecting case sizes like 0805 and 0603. DC
bias characteristics vary from manufacturer to manufacturer
and dc bias curves should be requested from them as part of
the capacitor selection process.
A more conservative approach is to choose an inductor that
can handle the maximum current limit of 1400mA.
Given a peak-to-peak current ripple (IPP) the inductor needs
to be at least
The output filter capacitor smoothes out current flow from the
inductor to the load, helps maintain a steady output voltage
during transient load changes and reduces output voltage
ripple. These capacitors must be selected with sufficient
capacitance and sufficiently low ESR to perform these func-
tions. The output ripple current can be calculated as:
A 2.2µH inductor with a saturation current rating of at least
1400mA is recommended for most applications. The induc-
tor’s resistance should be less than around 0.2Ω for good
efficiency. Table 1 lists suggested inductors and suppliers.
Voltage peak-to-peak ripple due to capacitance =
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20
(rising VOUT) or 85% (falling VOUT) of the desire output. The
inherent delay between the output (at 94% of VOUT) to the
time at which the nPOR is enabled is about 50ms. A pull up
resistor of 100kΩ at nPOR pin is required. Please refer to the
electrical specification table for other timing options. The
diagram below illustrates the timing response of the POR
function.
Application Information (Continued)
Voltage peak-to-peak ripple due to ESR = VPP-ESR
IPP*RESR
=
Voltage peak-to-peak ripple, root mean squared =
Note that the output ripple is dependent on the current ripple
and the equivalent series resistance of the output capacitor
(RESR). The RESR is frequency dependent (as well as tem-
perature dependent); make sure that the frequency of the
RESR given is the same order of magnitude as the switching
frequency.
20167319
SPREAD SPECTRUM (SS)
TABLE 2. Suggested Capacitors and Their Suppliers
The LM3370 features Spread Spectrum capability, via I2C, to
reduce the noise amplitude of the switching frequency during
data transmission. The feature can be enabled by activating
the appropriate control register bit (see register information
section for detail). The main clock of the LM3370 features
spread spectrum, where : FOSC = 2MHz 22kHz. This help
reduce noise caused by the harmonics present in the wave-
forms at the switch pins of the buck regulators. It is controlled
by I2C in the following manner:
Model
Description
Case
Size
Vendor
4.7µF for CIN
C1608X5R0J475 Ceramic,
X5R, 6.3V
0603
0805
TDK
Rating
C2012X5R0J475 Ceramic,
X5R, 6.3V
I2C bit
Modulation Frequency
Rating
SS_fmod = 1 (default)
SS_fmod = 0
1 kHz
2 kHz
JMK212BJ475 Ceramic,
X5R, 6.3V
0805
Taiyo
Yuden
Rating
BOARD LAYOUT CONSIDERATIONS
GRM21BR60J475 Ceramic,
X5R, 6.3V
0805
PC board layout is an important part of DC-DC converter
design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to
EMI, ground bounce, and resistive voltage loss in the traces.
These can send erroneous signals to the DC-DC converter
IC, resulting in poor regulation or instability.
Rating
muRata
TDK
GRM219R60J- Ceramic,
0805(Thin)
<
1mm
Height
475KE19D
X5R, 6.3V
Rating
Good layout for the LM3370 can be implemented by follow-
ing a few simple design rules:
10µF COUT
C2012X5R0J106 Ceramic,
X5R, 6.3V
0805
1. Place the LM3370, inductor and filter capacitors close
together and make the traces short. The traces between
these components carry relatively high switching cur-
rents and act as antennas. Following this rule reduces
radiated noise. Place the capacitors and inductor within
0.2 in. (5mm) of the LM3370.
Rating
JMK212BJ106 Ceramic,
X5R, 6.3V
0805
0805
Taiyo
Yuden
Rating
2. Arrange the components so that the switching current
loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor,
through the LM3370 and inductor to the output filter
capacitor and back through ground, forming a current
loop. In the second half of each cycle, current is pulled
up from ground, through the LM3370 by the inductor, to
the output filter capacitor and then back through ground,
forming a second current loop. Routing these loops so
the current curls in the same direction prevents mag-
netic field reversal between the two half-cycles and re-
duces radiated noise.
GRM21BR60J106 Ceramic,
X5R, 6.3V
Rating
muRata
GRM219R60J- Ceramic,
0805(Thin)
<
106KE19D
X5R, 6.3V
Rating
1mm
Height
POR (POWER ON RESET)
The LM3370 has an independent POR functions (nPOR) for
each buck converter. The nPOR1 and nPOR2 are open
drain circuits which pull low when the outputs are below 94%
21
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close to the LM3370 circuit and should be direct but
should be routed opposite to noisy components. This
reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace.
Application Information (Continued)
3. Connect the ground pins of the LM3370, and filter ca-
pacitors together using generous component-side cop-
per fill as a pseudo-ground plane. Then, connect this to
the ground-plane (if one is used) with several vias. This
reduces ground-plane noise by preventing the switching
currents from circulating through the ground plane. It
also reduces ground bounce at the LM3370 by giving it
a low-impedance ground connection.
6. Place noise sensitive circuitry, such as radio IF blocks,
away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-
sensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to
place the DC-DC converter on one corner of the board,
arrange the CMOS digital circuitry around it (since this also
generates noise), and then place sensitive preamplifiers and
IF stages on the diagonally opposing corner. Often, the
sensitive circuitry is shielded with a metal pan and power to
it is post-regulated to reduce conducted noise, using low-
dropout linear regulators.
4. Use wide traces between the power components and for
power connections to the DC-DC converter circuit. This
reduces voltage errors caused by resistive losses across
the traces.
5. Route noise sensitive traces, such as the voltage feed-
back path, away from noisy traces between the power
components. The voltage feedback trace must remain
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22
Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor Web
Page (www.national.com)
2. Maximum allowable metal burn on lead tips at the package edges is 76 microns.
3. No JEDEC registration as of December 2004.
16-Lead LLP Package
4 mm x 5 mm x 0.75 mm
NS Package Number SDA16B
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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