LM3370SD-3621 [NSC]
Dual Synchronous Step-Down DC-DC Converter with Dynamic Voltage Scaling Function; 双路同步降压型DC - DC转换器的动态电压缩放功能型号: | LM3370SD-3621 |
厂家: | National Semiconductor |
描述: | Dual Synchronous Step-Down DC-DC Converter with Dynamic Voltage Scaling Function |
文件: | 总26页 (文件大小:5408K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
January 4, 2008
LM3370
Dual Synchronous Step-Down DC-DC Converter with
Dynamic Voltage Scaling Function
General Description
Features
The LM3370 is a dual step-down DC-DC converter optimized
for powering ultra-low voltage circuits from a single Li-Ion bat-
tery and input rail ranging from 2.7V to 5.5V. It provides two
outputs with 600 mA load per channel. The output voltage
range varies from 1V to 3.3V and can be dynamically con-
trolled using the I2C compatible interface. This dynamic volt-
age scaling function allows processors to achieve maximum
performance at the lowest power level. The I2C compatible
interface can also be used to control auto PFM-PWM/PWM
mode selection and other performance enhancing features.
I2C compatible interface
■
VOUT1 = 1V to 2V in 50 mV steps
—
—
—
VOUT2 = 1.8V to 3.3V in 100 mV steps
Automatic PFM/PWM mode switching & Forced PWM
mode for low noise operation
Spread Spectrum capability using I2C
—
600 mA load per channel
■
■
■
■
■
■
■
2 MHz PWM fixed switching frequency (typ.)
Internal synchronous rectification for high efficiency
Internal soft start
The LM3370 offers superior features and performance for
portable systems with complex power management require-
ments. Automatic intelligent switching between PWM low-
noise and PFM low-current mode offers improved system
efficiency. Internal synchronous rectification enhances the
converter efficiency without the use of further external de-
vices.
Power-on-reset function for both outputs
2.7V ≤ VIN ≤ 5.5V
Operates from a single Li-Ion cell or 3 cell NiMH/NiCd
batteries and 3.3V/5.5V fixed rails
2.2 µH Inductor, 4.7 µF Input and 10 µF Output Capacitor
per channel
■
There is a power-on-reset function that monitors the level of
the output voltage to avoid unexpected power losses. The in-
dependent enable pin for each output allows for simple and
effective power sequencing.
16-lead LLP Package (4 mm x 5 mm x 0.8 mm)
■
■
20-Bump micro SMD Package (3.0 mm x 2.0 mm x 0.6
mm)
LM3370 is available in a 4 mm by 5 mm 16-lead non-pullback
LLP and a 20-Bump micro SMD, 3.0 mm x 2.0 mm x 0.6 mm,
package. A high switching frequency—2 MHz (typ)—allows
use of tiny surface-mount components including a 2.2 µH in-
ductor.
Applications
Baseband Processors
■
■
■
Application Processors (Video, Audio)
I/O Power
Default fixed voltages for the 2 output voltages combination
can be customized to fit system requirements by contacting
National Semiconductor Corporation.
FPGA Power and CPLD
■
Typical Performance Curve
20167379
Dimensions: 3.0 mm x 2.0 mm x 0.60 mm
Efficiency vs. Output Current, VOUT1=2101.627V381
© 2008 National Semiconductor Corporation
201673
www.national.com
Typical Application
20167301
FIGURE 1. Typical Application Circuit
Functional Block Diagram
20167302
FIGURE 2. Functional Diagram
www.national.com
2
Package Marking Information
16-Lead LLP Package
20167343
FIGURE 3. Top Marking
20167342
FIGURE 4. Top View
Pin Descriptions (LLP)
Pin #
Name
VIN2
Description
1
2
Power supply voltage input to PFET and NFET switches for Buck 2
Buck 2 Switch Pin
SW2
3
PGND2
VDD
Buck 2 Power Ground
4
Signal supply voltage input, VDD must be equal or greater of the two inputs (VIN1 & VIN2
Signal GND
)
5
SGND
PGND1
SW1
6
Buck 1 Power Ground
7
Buck 1 Switch Pin
8
VIN1
Power supply voltage input to PFET and NFET switches for Buck 1
Analog Feedback Input for Buck 1
9
FB1
I2C Compatible Data, a 2 kΩ pull up resistor is required
10
SDA
I2C Compatible Clock, a 2 kΩ pull up resistor is required
11
12
SCL
nPOR1
Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of target
output. A 100 kΩ pull up resistor is required
Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of target
output. A 100 kΩ pull up resistor is required
Buck 1 Enable
13
nPOR2
14
15
16
EN1
EN2
FB2
Buck 2 Enable
Analog feedback for Buck 2
3
www.national.com
Package Marking Information (micro SMD)
micro SMD Marking
20167379
Top View
XY = Date Code
TT = Die Run Traceability
S = Switcher Family
PSB = LM3370TL-3013
20167377
20167378
Top View
Bottom View
Pin Descriptions (micro SMD)
Pin #
A1
Name
SW1
Description
Buck 1 Switch Pin
A2
VIN1
Power supply voltage input to PFET and NFET switches for Buck 1
Signal GND
A3
SGND
FB1
A4
Analog Feedback Input for Buck 1
Buck 1 Power Ground
B1
PGND1
PGND1_S
SDA
B2
Buck 1 Power Ground Sense
I2C Compatible Data, a 2 kΩ pull up resistor is required
B3
I2C Compatible Clock, a 2 kΩ pull up resistor is required
Signal supply voltage input, VDD must be equal or greater of the two inputs ( VIN1 & VIN2
Signal GND
B4
SCL
C1
C2
C3
VDD
)
SGND
nPOR1
Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of target
output. A 100 kΩ pull up resistor is required
Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of target
output. A 100 kΩ pull up resistor is required
Buck 2 Power Ground
C4
nPOR2
D1
D2
D3
D4
E1
E2
E3
E4
PGND2
PGND2_S
EN2
Buck 2 Power Ground Sense
Buck 2 Enable
EN1
Buck 1 Enable
SW2
Buck 2 Switch Pin
VIN2
Power supply voltage input to PFET and NFET switches for Buck 2
SGND
FB2
Signal GND
Analog feedback for Buck 2
www.national.com
4
I2C Controlled Features
Features
Output Voltage
Modes
Parameter
VOUT1 & VOUT2
Buck 1 & Buck 2
Comments
Output voltage is controlled via I2C compatible
Mode can be controlled via I2C
compatible by either forcing device
in Auto mode or forced PWM mode
Spread Spectrum
Buck 1 & Buck 2
Spread Spectrum capability via I2C compatible for noise reduction
Ordering Information
(LLP)
Order Number
LM3370SD-3013
LM3370SDX-3013
LM3370SD-3021
LM3370SDX-3021
LM3370SD-3416
LM3370SDX-3416
LM3370SD-3621
LM3370SDX-3621
LM3370SD-3806
LM3370SDX-3806
LM3370SD-4221
LM3370SDX-4221
Voltage Option
Package Marking
S0003UB
S0003UB
S0003TB
S0003TB
S0003VB
S0003VB
S0004AB
S0004AB
S0003XB
S0003XB
S0003YB
S0003YB
Supplied As
1.2V & 2.5V
1.2V & 3.3V
1.4V & 2.8V
1.5V & 3.3V
1.6V & 1.8V
1.8V & 3.3V
1000 units, Tape-and-Reel
4500 units, Tape and Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
(micro SMD)
Order Number
Voltage Option
Package Marking
SPSB
Supplied As
LM3370TL-3607 NOPB
LM3370TLX-3607 NOPB
LM3370TL-3008 NOPB
LM3370TLX-3008 NOPB
LM3370TL-3006 NOPB
LM3370TLX-3006 NOPB
LM3370TL-3806 NOPB
LM3370TLX-3806 NOPB
LM3370TL-3206 NOPB
LM3370TLX-3206 NOPB
LM3370TL-3022 NOPB
LM3370TLX-3022 NOPB
1.5V & 1.9V
1000 units, Tape-and-Reel
3000 units, Tape-and-Reel
1000 units, Tape-and-Reel
3000 units, Tape-and-Reel
1000 units, Tape-and-Reel
3000 units, Tape-and-Reel
1000 units, Tape-and-Reel
3000 units, Tape-and-Reel
1000 units, Tape-and-Reel
3000 units, Tape-and-Reel
1000 units, Tape-and-Reel
3000 units, Tape-and-Reel
SPSB
1.2V & 2.0V
1.2V & 1.8V
1.6V & 1.8V
1.3V & 1.8V
1.2V & 1.85V
SPTB
SPTB
SPUB
SPUB
SPVB
SPVB
SPXB
SPXB
STHB
STHB
Note the LM3370TL-3607 has the following default output voltages where VOUT1 = 1.5V & VOUT2 = 1.9V
5
www.national.com
ESD Ratings (Note 5)
All Pins
Absolute Maximum Ratings (Notes 1, 2)
2 kV HBM
200V MM
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Notes 1, 2)
Input Voltage Range ((Note 10))
Recommended Load Current Per
Channel
Junction Temperature (TJ) Range
VIN1 , VIN2 VDD to PGND &
2.7V to 5.5V
0 mA to 600 mA
SGND
−0.2V to 6V
PGND to SGND
-0.2V to +0.2V
SDA, SCL, EN, EN2, nPOR1,
nPOR2, SW1, SW2, FB1 & FB2
−30°C to +125°C
(GND - 0.2) to (VIN + 0.2V)
Ambient Temperature (TA) Range (Note −30°C to +85°C
6)
Maximum Continuous Power
Dissipation (PD_MAX) (Note 3)
Internally Limited
125°C
−65°C to +150°C
Junction Temperature (TJ-MAX
Storage Temperature Range
)
Thermal Properties (Note 7)
Maximum Lead Temperature
(Soldering)
Junction-to-Ambient Thermal Resistance
(Note 4)
ꢀθJA (LLP-16)
26°C/W
50°C/W
ꢀθJA (20-Bump micro SMD)
Electrical Characteristics (Notes 2, 8, 10)Typical limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range (TA = TJ = −30°C to +85°C). Unless otherwise noted,
VIN1 = VIN2 = 3.6V.
Symbol
VFB
Parameter
Feedback Voltage
Conditions
Min
-3.5
Typ
0.031
0.0013
Max
+3.5
Units
%
(Note 11)
VOUT
Line Regulation
%/V
2.7V ≤ VIN ≤ 5.5V
IO = 10 mA, VOUT = 1.8V
Load Regulation
%/mA
100 mA ≤ IO ≤ 600 mA
VIN = 3.6V, VOUT = 1.8V
IQ PFM
IQ SD
ILIM
Quiescent Current “On”
Quiescent Current “Off”
Peak Switching Current Limit
PFET
PFM Mode, Both Bucks ON
EN1 = EN2 = 0V
34
0.2
µA
µA
3
1400
500
350
400
210
2.4
1
VIN = 3.6V
850
1200
390
240
350
170
2.0
mA
RDS_ON
(LLP)
VIN = 3.6V, ISW = 200 mA
VIN = 3.6V, ISW = 200 mA
VIN = 3.6V, ISW = 200 mA
VIN = 3.6V, ISW = 200 mA
mΩ
mΩ
NFET
RDS_ON
PFET
(micro SMD)
NFET
FOSC
IEN
Internal Oscillator Frequency
Enable (EN) Input Current
Enable Logic Low
Enable Logic High
1.5
1.0
MHz
µA
V
0.01
VIL
0.4
VIH
V
POWER ON RESET THRESHOLD/FUNCTION (POR)
nPOR1 &
nPOR2
Delay Time
nPOR1 = Power ON Reset
for Buck 1
50 mS (default)
50
mS
%
nPOR2 = Power ON Reset
for Buck 2
Can be pre-trimmd to 50 uS, 100
mS & 200 mS
POR
Threshold
Percentage of Target VOUT
VOUT Rising
94
85
VOUT Falling, 85% (default), Can be
pre-trimmed to 70% or 94%
www.national.com
6
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. The thermal shutdown engages at TJ = 150°C (typ.) and disengages
at TJ = 140°C(typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP)
(AN-1187).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200
pF capacitor discharged directly into each pin. (EAIJ)
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be de-
rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125ºC), the maximum power dissipation
of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following
equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Note 7: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the
JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2 x 1 array of thermal vias. Thickness of copper
layers are 2/1/1/2oz.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special
care must be paid to thermal dissipation issues in board design.
The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum
power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to
Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
Note 8: Min. and Max are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during
production with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
Note 9: Guaranteed by design.
Note 10: Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages:
VIN = 2.7V to 5.5V for 1V ≤ VOUT ≤ 1.7V and for VOUT = 1.8V or greater, VIN = VOUT + 1V
or
VIN,MIN = ILOAD * (RDSON_PFET + RDCR_INDUCTOR) + VOUT
Note 11: Test condition: for VOUT less than 2.5V, VIN = 3.6V; for VOUT greater than or equal to 2.5V, VIN = VOUT + 1V.
Dissipation Rating Table
TA = 60°C
Power Rating
TA = 85°C
Power Rating
1538 mW
θJA
26°C/W (4-Layer Board) LLP-16
50°C/W (4-Layer Board) 20-bump micro SMD
1300 mW
800 mW
7
www.national.com
Typical Performance Characteristics LM3370SD/TL, Circuit of Figure 1, VIN = 3.6V, VOUT1 = 1.5V &
VOUT2 = 2.5V, L = 2,2 µH (NR3015T2R2M), CIN = 4.7 µF (0805) and COUT = 10 µF (0805) & TA = 25°C, unless otherwise noted.
IQ_PFM (Non Switching)
Both Channels
IQ_PWM (Non Switching)
Both Channels
20167358
20167357
IQ_PWM (Switching)
Both Channels
IQ_SD (EN1 = EN2 = 0V)
20167349
20167359
RDS_ON (PFET) vs. Temperature
VIN = 3.6V
RDS_ON (NFET) vs. Temperature
VIN = 3.6V
20167347
20167346
www.national.com
8
RDS_ON (LLP) vs. VIN
Current Limit vs. VIN
20167348
20167353
Switching Frequency vs. VIN
Output Voltage vs. Output Current
VIN = 3.6V (Forced PWM)
20167360
20167370
Efficiency vs. Output Current
Forced PWM Mode, VOUT1 = 1.2V
Efficiency vs. Output Current
Forced PWM Mode, VOUT1 = 1.8V
20167362
20167363
9
www.national.com
Efficiency vs. Output Current
Auto Mode, VOUT1 = 1.5V
Efficiency vs. Output Current
Auto Mode, VOUT2 = 1.9V
20167380
20167381
Efficiency vs. Output Current
Auto Mode, VOUT2 = 3.3V
Efficiency vs. Output Current
Forced PWM Mode, VOUT2 = 3.3V
20167367
20167366
Typical Operation Waveform
VIN = 3.6V, VOUT1 = 1.8V & VOUT2 = 1.8V
Load = 400 mA
Typical Operation Waveform
VIN = 4.8V, VOUT1 = 1V & VOUT2 = 3.3V
Load = 400 mA
20167321
20167320
www.national.com
10
Typical Operation Waveform
VIN = 3.6V, VOUT1 = 1.5V, VOUT2 = 2.5V,
Load = 600 mA Each
Start-up at PWM for BUCK1
( VIN = 3.6V, VOUT = 1.5V, Load = 200 mA )
20167327
20167322
Start-up at PWM for BUCK2
( VIN = 3.6V, VOUT = 2.5V, Load = 200 mA )
Line Transient
( VOUT1 = 1.2V )
20167330
20167325
Line Transient
( VOUT2 = 1.8V )
Load Transient in PFM MODE
( VOUT1 = 1.5V )
20167331
20167332
11
www.national.com
Load Transient in PFM MODE
( VOUT1 = 1.5V )
Load Transient in PFM MODE
( VOUT1 = 1.8V )
20167333
20167334
20167338
20167341
Load Transient in PFM MODE ( VOUT1 = 1.8V )
Load Transient in PWM MODE
( VIN = 3.6V, VOUT1 = 1.2V )
20167335
Load Transient in PWM MODE
( VIN = 3.6V, VOUT1 = 1.5V )
Load Transient in PWM MODE
( VIN = 3.6V, VOUT2 = 2.5V )
20167339
www.national.com
12
Spread Spectrum Enabling
( VOUT Signal at 2 MHz)
VOUT Stepping
( From 1.8V to 3.3V )
20167371
20167375
VOUT Stepping
( From 3.3V to 1.8V )
20167372
13
www.national.com
CURRENT LIMITING
Operation Description
A current limit feature allows the LM3370 to protect itself and
external components during overload conditions. PWM mode
implements cycle-by-cycle current limiting using an internal
comparator that trips at 1200 mA (typ.). If the outputs are
shorted to ground the device enters a timed current limit mode
where the NFET is turned on for a longer duration until the
inductor current falls below a low threshold, ensuring inductor
has more time to decay, thereby preventing runaway.
DEVICE INFORMATION
The LM3370, a dual high efficiency step down DC-DC con-
verter, delivers regulated voltages from input rails between
2.7V to 5.5V. Using voltage mode architecture with syn-
chronous rectification, the LM3370 has the ability to deliver
up to 600 mA per channel. The performance is optimized for
systems where efficiency and space are critical.
There are three modes of operation depending on the current
required—PWM, PFM, and shutdown. PWM mode handles
loads of approximately 70 mA or higher with 90% efficiency
or better. Lighter loads cause the device to automatically
switch into PFM mode to maintain high efficiency with low
supply current (IQ = 20 µA typ.) per channel.
PFM OPERATION
At very light loads, the converter enters PFM mode and op-
erates with reduced switching frequency and supply current
to maintain high efficiency.
The part will automatically transition into PFM mode when ei-
ther of two conditions are true, for a duration of 32 or more
clock cycles:
The LM3370 can operate up to a 100% duty cycle (PFET
switch always on) for low drop out control of the output volt-
age. In this way the output voltage will be controlled down to
the lowest possible input voltage.
1. The NFET current reaches zero.
2. The peak PFET switch current drops below the IMODE
level .
Additional features include soft-start, under voltage lock out,
current overload protection, and thermal overload protection.
CIRCUIT OPERATION
During the first portion of each switching cycle, the control
block in the LM3370 turns on the internal PFET switch. This
allows current to flow from the input through the inductor to
the output filter capacitor and load. The inductor limits the
current to a ramp with a slope of
Supply current during this PFM mode is less than 20 µA per
channel, which allows the part to achieve high efficiency un-
der extremely light load conditions. When the output drops
below the ‘low’ PFM threshold, the cycle repeats to restore
the output voltage to ∼1.2% above the nominal PWM output
voltage.
If the load current should increase during PFM mode (see
Figure 5) causing the output voltage to fall below the ‘low2’
PFM threshold, the part will automatically transition into fixed-
frequency PWM mode.
by storing energy in a magnetic field. During the second por-
tion of each cycle, the controller turns the PFET switch off,
blocking current flow from the input, and then turns the NFET
synchronous rectifier on. The inductor draws current from
ground through the NFET to the output filter capacitor and
load, which ramps the inductor current down with a slope of
During PFM operation, the converter positions the output volt-
age slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The PFM
comparators sense the output voltage via the feedback pin
and control the switching of the output FETs such that the
output voltage ramps between 0.8% and 1.6% (typical) above
the nominal PWM output voltage. If the output voltage is be-
low the ‘high’ PFM comparator threshold, the PFET power
switch is turned on. It remains on until the output voltage ex-
ceeds the ‘high’ PFM threshold or the peak current exceeds
the IPFM level set for PFM mode. The typical peak current in
PFM mode is:
The output filter stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across
the load.
PWM OPERATION
IPFM = 115 mA + VIN/57Ω
During PWM operation the converter operates as a voltage-
mode controller with input voltage feed forward. This allows
the converter to achieve excellent load and line regulation.
The DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, feed forward inversely
proportional to the input voltage is introduced.
Once the PFET power switch is turned off, the NFET power
switch is turned on until the inductor current ramps to zero.
When the NFET zero-current condition is detected, the NFET
power switch is turned off. If the output voltage is below the
‘high’ PFM comparator threshold (see Figure 5), the PFET
switch is again turned on and the cycle is repeated until the
output reaches the desired level. Once the output reaches the
‘high’ PFM threshold, the NFET switch is turned on briefly to
ramp the inductor current to zero and then both output switch-
es are turned off and the part enters an extremely low power
mode.
INTERNAL SYNCHRONOUS RECTIFICATION
While in PWM mode, the LM3370 uses an internal NFET as
a synchronous rectifier to reduce rectifier forward voltage
drop and associated power loss. Synchronous rectification
provides a significant improvement in efficiency whenever the
output voltage is relatively low compared to the voltage drop
across an ordinary rectifier diode.
www.national.com
14
FORCED PWM MODE
output voltage. In this way the output voltage will be controlled
down to the lowest possible input voltage. The minimum input
The LM3370 auto mode can be bypassed by forcing the de-
vice to operate in PWM mode, this can be implemented
through the I2C compatible interface, see Table 1.
voltage needed to support the output voltage is VIN,MIN
ILOAD*(RDSON,PFET + RINDUCTOR) + VOUT
=
• ILOAD
load current
SOFT-START
• RDSON/PFET
drain to source resistance of PFET switch in the
triode region
The LM3370 has a soft start circuit that limits in-rush current
during start up. Soft start is activated only if EN goes from
logic low to logic high after VIN reaches 2.7V.
• RINDUCTOR
inductor resistance
LDO - LOW DROP OUT OPERATION
The LM3370 can operate at 100% duty cycle (no switching,
PFET switch completely on) for low drop out support of the
20167303
FIGURE 5. Operation in PFM Mode and Transfer to PWM Mode
15
www.national.com
I2C Compatible Interface Electrical Specifications
Unless otherwise noted, VBATT = 2.7V to 5.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −30°C to +125°C. (Notes 2, 8, 9)
Symbol
FCLK
Parameter
Conditions
Min
Typ
Max
Units
kHz
µS
Clock Frequency
400
tBF
Bus-Free Time between Start and Stop
Hold Time Repeated Start Condition
CLK Low Period
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
1.3
0.6
1.3
0.6
0.6
200
200
0.6
tHOLD
tCLKLP
tCLKHP
tSU
µS
µS
CLK High Period
µS
Set Up Time Repeated Start Condition
Data Hold Time
µS
tDATAHLD
tCLKSU
TSU
nS
Data Set Up Time
nS
Set Up Time for Start Condition
µS
TTRANS
Maximum Pulse Width of Spikes that Must be
Suppressed by the Input Filter of Both DATA & CLK
signals.
50
nS
VDD_I2C I2C Logic High Level
1
VIN
V
according to the I2C bus specification. Maximum frequency is
400 kHz.
I2C Compatible Interface
In I2C compatible mode, the SCL pin is used for the I2C clock
and the SDA pin is used for the I2C data. Both these signals
need a pull-up resistor according to I2C specification. The
values of the pull-up resistor are determined by the capaci-
tance of the bus (typ. ∼1.8k). Signal timing specifications are
I2C COMPATIBLE DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
20167306
I2C COMPATIBLE START AND STOP CONDITIONS
START and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates
20167307
www.national.com
16
TRANSFERRING DATA
acknowledge. A receiver which has been addressed must
generate an acknowledge after each byte has been received.
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. The
number of bytes that can be transmitted per transfer is unre-
stricted. Each byte of data has to be followed by an acknowl-
edge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH)
during the acknowledge clock pulse. The receiver must pull
down the SDA line during the 9th clock pulse, signifying an
After the START condition, I2C master sends a chip address.
This address is seven bits long followed by an eighth bit which
is a data direction bit (R/W). For the eighth bit, a “0” indicates
a WRITE and a “1” indicates a READ. The second byte se-
lects the register to which the data will be written. The third
byte contains data to write to the selected register.
I2C Compatible Write Cycle
20167309
W = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated startxx=36h
However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the read
cycle waveform.
I2C Compatible Read Cycle
20167310
17
www.national.com
Device Register Information
Register Information
Register Name
Control
Location
00
Type
R/W
Function
Control signal for Buck 1 and Buck 2
Buck 1
Buck 2
01
02
R/W
R/W
Output setting & Mode selection for Buck 1
Output setting & Mode selection for Buck 2 and POR disable
I2C CHIP ADDRESS INFORMATION
20167308
REGISTER 00
20167311
www.national.com
18
REGISTER 01
20167312
REGISTER 02
20167313
19
www.national.com
TABLE 1. Output Selection Table via I2C Programing
Buck Output Voltage Selection Codes
Data Code
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
Buck_1 (V)
NA
Buck_2 (V)
NA
NA
1.8
NA
1.85 or 1.9*
2.0
NA
NA
2.1
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
NA
NA
NA
NA
NA
NA
NA
NA
NA
* Can be trimmed at the factory at 1.85V or 1.9V using the same trim code.
www.national.com
20
method 2:
Application Information
SETTING OUTPUT VOLTAGE VIA I2C Compatible
A more conservative approach is to choose an inductor that
can handle the maximum current limit of 1400 mA.
Given a peak-to-peak current ripple (IPP) the inductor needs
to be at least
The outputs of the LM3370 can be programmed through Buck
1 & Buck 2 registers via I2C. Buck 1 output voltage can be
dynamically adjusted between 1V to 2V in 50 mV steps and
Buck 2 output voltage can be adjusted between 1.8V to 3.3V
in 100 mV steps. Finer adjustments to the output of Buck 2
can be achieved with the placement of a resistor betweeen
VOUT2 and the FB2 pin. Typically by placing a 20KΩ resistor,
R, between these nodes will result in the programmed Output
A 2.2 µH inductor with a saturation current rating of at least
1400 mA is recommended for most applications. The
inductor’s resistance should be less than around 0.2Ω for
good efficiency. Table 2 lists suggested inductors and sup-
pliers.
Voltage increasing by approximately 45mV,ΔVTYP
.
ΔVTYP= R × 500mV / 234KΩ
Please refer to for programming the desire output voltage. If
the I2C compatible feature is not used, the default output volt-
age will be the pre-trimmed voltage. For example,
LM3370SD-3021 refers to 1.2V for Buck 1 and 3.3V for Buck
2.
For low-cost applications, an unshielded bobbin inductor is
suggested. For noise critical applications, a toroidal or shield-
ed-bobbin inductor should be used. A good practice is to lay
out the board with overlapping footprints of both types for de-
sign flexibility. This allows substitution of a low-noise toroidal
inductor, in the event that noise from low-cost bobbin models
is unacceptable.
VDD Pin
VDD is the power supply to the internal control circuit, if VDD
pin is not tied to VIN during normal operating condition, VDD
must be set equal or greater of the two inputs ( VIN1 or VIN2 ).
An optional capacitor can be used for better noise immunity
at VDD pin or when VDD is not tied to either VIN pins. Addition-
ally, for reasons of noise suppression, it is advisable to tie the
Below are some suggested inductor manufacturers include
but are not limited to:
TABLE 2. Suggested Inductors and Suppliers
EN1/EN2 pins to VDD rather than VIN
.
Model
Vendor
Dimensions
(mm)
ISAT
SDA, SCL Pins
When not using I2C the SDA and SCL pins should be tied
directly to the VDD pin.
DO3314-222
LPO3310-222
SD3114-2R2
Coilcraft
3.3 x 3.3 x 1.4
3.3 x 3.3 x 1.0
3.1 x 3.1 x 1.4
1.6A
1.1A
Micro-Stepping:
Cooper
1.48A
1.1A
The Micro-Stepping feature minimizes output voltage over-
shoot/undershoot during large output transients. If Micro-
stepping is enabled through I2C, the output voltage automat-
ically ramps at 50 mV per step for Buck 1 and 100 mV per
step for Buck 2. The steps are summarized as follow:
NR3010T2R2M Taiyo Yuden 3.0 x 3.0 x 1.0
NR3015T2R2M
3.0 x 3.0 x 1.5
2.6 x 2.8 x 1.0
1.48A
1.0A
VLF3010AT-
2R2M1R0
TDK
Buck 1: 50 mV/step and 32 µs/step
Buck 2: 100 mV/step and 32 µs/step
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 4.7 μF, 6.3V is sufficient for most
applications. A larger value may be used for improved input
voltage filtering. The input filter capacitor supplies current to
the PFET switch of the LM3370 in the first half of each cycle
and reduces voltage ripple imposed on the input power
source. A ceramic capacitor's low ESR provides the best
noise filtering of the input voltage spikes due to this rapidly
changing current. Select an input filter capacitor with a surge
current rating sufficient for the power-up surge from the input
power source. The power-up surge current is approximately
the capacitor’s value (µF) times the voltage rise rate (V/µs).
For example if changing Buck 1 voltage from 1V to 1.8V yields
20 steps [(1.8 - 1)/ 0.05 = 20]. This translates to 640μs [(20 x
32 µs) = 640 µs] needed to reach the final target voltage.
INDUCTOR SELECTION
There are two main considerations when choosing an induc-
tor; the inductor should not saturate, and the inductor current
ripple is small enough to achieve the desired output voltage
ripple.
There are two methods to choose the inductor current rating.
method 1:
The input current ripple can be calculated as:
The total current is the sum of the load and the inductor ripple
current. This can be written as
•
•
•
•
ILOAD load current
VIN input voltage
L inductor
OUTPUT CAPACITOR SELECTION
DC bias characteristics of ceramic capacitors must be con-
sidered when selecting case sizes like 0805 and 0603. DC
f switching frequency
21
www.national.com
bias characteristics vary from manufacturer to manufacturer
and dc bias curves should be requested from them as part of
the capacitor selection process.
VOUT) or 85% (falling VOUT) of the desire output. The inherent
delay between the output (at 94% of VOUT) to the time at which
the nPOR is enabled is about 50 ms. A pull up resistor of 100
kΩ at nPOR pin is required. Please refer to the electrical
specification table for other timing options. The diagram be-
low illustrates the timing response of the POR function.
The output filter capacitor smoothes out current flow from the
inductor to the load, helps maintain a steady output voltage
during transient load changes and reduces output voltage
ripple. These capacitors must be selected with sufficient ca-
pacitance and sufficiently low ESR to perform these functions.
The output ripple voltage can be calculated as:
Voltage peak-to-peak ripple due to capacitance =
Voltage peak-to-peak ripple due to ESR = VPP-ESR = IPP*RESR
Voltage peak-to-peak ripple, root mean squared =
20167319
SPREAD SPECTRUM (SS)
The LM3370 features Spread Spectrum capability, via I2C, to
reduce the noise amplitude of the switching frequency during
data transmission. The feature can be enabled by activating
the appropriate control register bit (see register information
section for detail). The main clock of the LM3370 features
spread spectrum at FOSC = 2 MHz ± 22 kHz ( peak frequency
deviation) with the modulation frequency of either 1 kHz(de-
fault) or 2 kHz via I2C. This help reduce noise caused by the
harmonics present in the waveforms at the switch pins of the
buck regulators. It is controlled by I2C in the following manner:
Note that the output ripple is dependent on the current ripple
and the equivalent series resistance of the output capacitor
(RESR). The RESR is frequency dependent (as well as temper-
ature dependent); make sure that the frequency of the RESR
given is the same order of magnitude as the switching fre-
quency.
TABLE 3. Suggested Capacitors and Their Suppliers
Model
Description
Case
Size
Vendor
I2C bit
Modulation Frequency
4.7 µF for CIN
SS_fmod = 1 (default)
SS_fmod = 0
1 kHz
2 kHz
C1608X5R0J475
Ceramic, X5R,
6.3V Rating
0603
0805
0805
0805
TDK
BOARD LAYOUT CONSIDERATIONS
C2012X5R0J475
JMK212BJ475
Ceramic, X5R,
6.3V Rating
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce, and resistive voltage loss in the traces. These
can send erroneous signals to the DC-DC converter IC, re-
sulting in poor regulation or instability.
Ceramic, X5R,
6.3V Rating
Taiyo
Yuden
GRM21BR60J475 Ceramic, X5R,
6.3V Rating
GRM219R60J-
475KE19D
Ceramic, X5R,
6.3V Rating
0805
(Thin)
<1mm
Height
Good layout for the LM3370 can be implemented by following
a few simple design rules:
muRata
1. Place the LM3370, inductor and filter capacitors close
together and make the traces short. The traces between
these components carry relatively high switching
currents and act as antennas. Following this rule reduces
radiated noise. Place the capacitors and inductor within
0.2 in. (5mm) of the LM3370.
10µF COUT
C2012X5R0J106
Ceramic, X5R,
6.3V Rating
0805
0805
0805
TDK
2. Arrange the components so that the switching current
loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor,
through the LM3370 and inductor to the output filter
capacitor and back through ground, forming a current
loop. In the second half of each cycle, current is pulled
up from ground, through the LM3370 by the inductor, to
the output filter capacitor and then back through ground,
forming a second current loop. Routing these loops so
the current curls in the same direction prevents magnetic
field reversal between the two half-cycles and reduces
radiated noise.
JMK212BJ106
Ceramic, X5R,
6.3V Rating
Taiyo
Yuden
GRM21BR60J106 Ceramic, X5R,
6.3V Rating
GRM219R60J-
106KE19D
Ceramic, X5R,
6.3V Rating
0805
(Thin)
< 1mm
Height
muRata
POR (POWER ON RESET)
The LM3370 has an independent POR functions (nPOR) for
each buck converter. The nPOR1 and nPOR2 are open drain
circuits which pull low when the outputs are below 94% (rising
3. Connect the ground pins of the LM3370, and filter
capacitors together using generous component-side
www.national.com
22
copper fill as a pseudo-ground plane. Then, connect this
to the ground-plane (if one is used) with several vias. This
reduces ground-plane noise by preventing the switching
currents from circulating through the ground plane. It also
reduces ground bounce at the LM3370 by giving it a low-
impedance ground connection.
Refer to the section "Surface Mount Technology (SMD) As-
sembly Considerations". For best results in assembly, align-
ment ordinals on the PC board should be used to facilitate
placement of the device. The pad style used with Micro SMD
package must be the NSMD (non-solder mask defined) type.
This means that the solder-mask opening is larger than the
pad size. This prevents a lip that otherwise forms if the solder-
mask and pad overlap, from holding the device off the surface
of the board and interfering with mounting. See Application
Note 1112 for specific instructions how to do this. The 20-
Bump package used for LM3370TL has 300 micron solder
balls and requires 10.82 mils pads for mounting on the circuit
board. The trace to each pad should enter the pad with a 90°
entry angle to prevent debris from being caught in deep cor-
ners. Initially, the trace to each pad should be 7 mil wide, for
a section approximately 7 mil long or longer, as a thermal re-
lief. Then each trace should neck up or down to its optimal
width. The important criteria is symmetry. This ensures the
solder bumps on the LM3370TL re-flow evenly and that the
device solders level to the board. In particular, special atten-
tion must be paid to the pads for bumps A2/B1 of VOUT1, and
E2/D1 of VOUT2, because VIN and PGND are typically con-
nected to large copper planes, inadequate thermal relief can
result in late or inadequate re-flow of these bumps.
4. Use wide traces between the power components and for
power connections to the DC-DC converter circuit. This
reduces voltage errors caused by resistive losses across
the traces.
5. Route noise sensitive traces, such as the voltage
feedback path, away from noisy traces between the
power components. The voltage feedback trace must
remain close to the LM3370 circuit and should be direct
but should be routed opposite to noisy components. This
reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace.
6. Place noise sensitive circuitry, such as radio IF blocks,
away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-
sensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to place
the DC-DC converter on one corner of the board, arrange the
CMOS digital circuitry around it (since this also generates
noise), and then place sensitive preamplifiers and IF stages
on the diagonally opposing corner. Often, the sensitive cir-
cuitry is shielded with a metal pan and power to it is post-
regulated to reduce conducted noise, using low-dropout
linear regulators.
The Micro SMD package is optimized for the smallest possi-
ble size in applications with red or infrared opaque cases.
Because the Micro SMD package lacks the plastic encapsu-
lation characteristic of larger devices, it is vulnerable to light.
Backside metallization and/or epoxy coating, along with front-
side shading by the printed circuit board, reduce this sensi-
tivity. However, the package has exposed die edges. In
particular, Micro SMD devices are sensitive to light, in the red
and infrared range, shining on the package’s exposed die
edges.
Micro SMD PACKAGE ASSEMBLY AND USE
Use of the Micro SMD package requires specialized board
layout, precision mounting and careful re-flow techniques, as
detailed in National Semiconductor Application Note 1112.
23
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor Web Page (www.national.com)
1.
Maximum allowable metal burn on lead tips at the package edges is 76 microns.
2.
No JEDEC registration as of December 2004.
3.
16-Lead LLP Package
NS Package Number SDA16B
4 mm x 5 mm x 0.75 mm
www.national.com
24
NOTE: UNLESS OTHERWISE SPECIFIED
1. EPOXY COATING
2. FOR SOLDER BUMP COMPOSITION, SEE “SOLDER INFORMATION” IN THE PACKAGE SECTION OF THE NATIONAL SEMICONDUCTOR WEB PAGE
(www.national.com)
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS PACK-
AGE HEIGHT.
6. REFERENCE JEDEC REGISTRATION MO-211, VARIATION DG.
20-Bump micro SMD Package, 0.5mm Pitch
NS Package Number TLA20CWA
X1 = 2.047 mm ± 0.030 mm
X2 = 3.000 mm ± 0.030 mm
X3 = 0.600 mm ± 0.075 mm
25
www.national.com
Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
Products
www.national.com/amplifiers
Design Support
Amplifiers
WEBENCH
www.national.com/webench
www.national.com/AU
Audio
www.national.com/audio
www.national.com/timing
www.national.com/adc
Analog University
App Notes
Clock Conditioners
Data Converters
Displays
www.national.com/appnotes
www.national.com/contacts
www.national.com/quality/green
www.national.com/packaging
Distributors
www.national.com/displays
www.national.com/ethernet
www.national.com/interface
www.national.com/lvds
Green Compliance
Packaging
Ethernet
Interface
Quality and Reliability www.national.com/quality
LVDS
Reference Designs
Feedback
www.national.com/refdesigns
www.national.com/feedback
Power Management
Switching Regulators
LDOs
www.national.com/power
www.national.com/switchers
www.national.com/ldo
LED Lighting
PowerWise
www.national.com/led
www.national.com/powerwise
Serial Digital Interface (SDI) www.national.com/sdi
Temperature Sensors
Wireless (PLL/VCO)
www.national.com/tempsensors
www.national.com/wireless
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2008 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
Email:
new.feedback@nsc.com
Tel: 1-800-272-9959
National Semiconductor Europe
Technical Support Center
Email: europe.support@nsc.com
German Tel: +49 (0) 180 5010 771
English Tel: +44 (0) 870 850 4288
National Semiconductor Asia
Pacific Technical Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Technical Support Center
Email: jpn.feedback@nsc.com
www.national.com
相关型号:
LM3370SD-3621/NOPB
Dual Synchronous Step-Down DC-DC Converter with Dynamic Voltage Scaling Function 16-WSON
TI
LM3370SD-3806/NOPB
Dual Synchronous Step-Down DC-DC Converter with Dynamic Voltage Scaling Function 16-WSON -30 to 85
TI
LM3370SDX-3021/NOPB
Dual Synchronous Step-Down DC-DC Converter with Dynamic Voltage Scaling Function 16-WSON -30 to 85
TI
©2020 ICPDF网 联系我们和版权申明