LM2984CT [NSC]
LM2984C Microprocessor Power Supply System; LM2984C微处理器电源系统
| 型号： | LM2984CT |
| 厂家： | 
National Semiconductor |
| 描述： | LM2984C Microprocessor Power Supply System |
| 文件： | 总14页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1989
LM2984C Microprocessor Power Supply System
General Description
The LM2984C positive voltage regulator features three in-
dependent and tracking outputs capable of delivering the
power for logic circuits, peripheral sensors and standby
memory in a typical microprocessor system. The LM2984C
includes circuitry which monitors both its own high-current
output and also an external mP. If any error conditions are
sensed in either, a reset error flag is set and maintained until
the malfunction terminates. Since these functions are in-
cluded in the same package with the three regulators, a
great saving in board space can be realized in the typical
microprocessor system. The LM2984C also features very
low dropout voltages on each of its three regulator outputs
(0.6V at the rated output current). Furthermore, the quies-
cent current can be reduced to 1 mA in the standby mode.
also provided. Fixed outputs of 5V are available in the plas-
tic TO-220 power package.
Features
Y
Three low dropout tracking regulators
Y
Output current in excess of 500 mA
Y
Low quiescent current standby regulator
Y
Microprocessor malfunction RESET flag
Y
Delayed RESET on power-up
Y
Accurate pretrimmed 5V outputs
Y
Reverse battery protection
Y
Overvoltage protection
Y
Reverse transient protection
Y
Designed also for vehicular applications, the LM2984C and
all regulated circuitry are protected from reverse battery in-
stallations or 2-battery jumps. Familiar regulator features
such as short circuit and thermal overload protection are
Short circuit protection
Y
Internal thermal overload protection
Y
ON/OFF switch for high current outputs
Y
100% electrical burn-in in thermal limit
Typical Application Circuit
LM2984C
C
must be at least 10 mF to
OUT
maintain stability. May be increased
without bound to maintain regulation
during transients. Locate as close as
possible to the regulator. This capac-
itor must be rated over the same op-
erating temperature range as the
regulator. The equivalent series re-
sistance (ESR) of this capacitor is
critical; see curve.
TL/H/8821–1
Order Number LM2984CT
See NS Package Number TA11B
C
1995 National Semiconductor Corporation
TL/H/8821
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Internal Power Dissipation
Internally Limited
a
0 C to 125 C
Operating Temperature Range (T )
A
§
§
Maximum Junction Temperature (Note 1)
Storage Temperature Range
150 C
§
Input Voltage
Survival Voltage ( 100 ms)
b
a
65 C to 150 C
§
§
k
Operational Voltage
35V
26V
Lead Temperature (Soldering, 10 sec.)
ESD rating is to be determined.
230 C
§
Electrical Characteristics
e
e
e
e
10 mF, T 25 C (Note 6) unless otherwise indicated
j
V
IN
14V, I
5 mA, C
§
OUT
OUT
Tested
Limit
Design
Limit
Parameter
Conditions
Typical
Units
(Note 2)
(Note 3)
V
(Pin 11)
OUT
s
s
500 mA
Output Voltage
5 mA
I
4.85
5.15
4.75
5.25
V
min
o
5.00
s
s
s
s
s
s
6V
9V
7V
V
IN
V
IN
V
IN
26V
16V
26V
V
max
Line Regulation
2
5
25
50
50
mV
mV
mV
max
max
max
s
s
500 mA
Load Regulation
5 mA
I
12
OUT
Output Impedance
250 mA and 10 mA
dc
,
rms
24
mX
e
f
o
120 Hz
e
e
Quiescent Current
I
I
500 mA
250 mA
38
14
100
50
mA
mA
OUT
OUT
max
max
e
Output Noise Voltage
Long Term Stability
Ripple Rejection
10 Hz–100 kHz, I
OUT
100 mA
100
20
mV
mV/1000 hr
e
f
o
120 Hz
70
60
dB
min
max
max
e
e
Dropout Voltage
I
I
500 mA
250 mA
0.53
0.28
0.92
0.80
0.50
0.75
1.00
0.60
V
V
OUT
OUT
Current Limit
A
min
V
min
V
min
V
min
Maximum Operational
Input Voltage
Continuous DC
32
45
26
35
26
35
s
e
Maximum Line Transient
V
V
6V, R
100X
OUT
OUT
t
b
e
100X
Reverse Polarity
Input Voltage DC
0.6V, R
OUT
OUT
b
b
b
b
b
b
30
55
15
35
15
35
s
e
Reverse Polarity Input
Voltage Transient
T
100 ms, R
OUT
100X
V
min
2
Electrical Characteristics (Continued)
e
e
e
e
10 mF, T 25 C (Note 6) unless otherwise indicated
j
V
14V, I
5 mA, C
§
IN
buf
buf
Tested
Limit
Design
Limit
Parameter
(Pin 10)
Conditions
Typical
Units
(Note 2)
(Note 3)
V
buffer
s
s
100 mA
Output Voltage
5 mA
I
4.85
5.15
4.75
5.25
V
min
o
5.00
s
s
s
s
s
s
6V
9V
7V
V
IN
V
IN
V
IN
26V
16V
26V
V
max
Line Regulation
2
25
50
50
mV
mV
mV
max
max
max
5
s
s
100 mA
Load Regulation
Output Impedance
Quiescent Current
5 mA
I
15
buf
50 mA and 10 mA
dc rms
,
200
8.0
100
20
mX
e
I
100 mA
15.0
mA
max
buf
e
Output Noise Voltage
Long Term Stability
Ripple Rejection
Dropout Voltage
Current Limit
10 Hz–100 kHz, I
100 mA
mV
mV/1000 hr
OUT
e
f
o
120 Hz
70
60
dB
min
e
I
100 mA
0.35
0.23
0.50
0.15
0.60
V
max
buf
A
min
min
Maximum Operational
Input Voltage
Continuous DC
32
45
26
35
26
35
V
s
e
100X
Maximum Line
Transient
V
V
T
6V, R
buf
buf
V
min
V
min
V
min
t
b
e
100X
Reverse Polarity
Input Voltage DC
0.6V, R
buf
buf
b
b
b
b
b
b
30
55
15
35
15
35
s
e
100X
Reverse Polarity Input
Voltage Transient
100 ms, R
buf
Electrical Characteristics
e
e
e
e
10 mF, T 25 C (Note 6) unless otherwise indicated
j
V
IN
14V, I
1 mA, C
§
stby
stby
Tested
Limit
Design
Limit
Parameter
Conditions
Typical
Units
(Note 2)
(Note 3)
V
standby
(Pin 9)
s
s
7.5 mA
Output Voltage
1 mA
I
4.85
5.15
4.75
5.25
V
min
o
5.00
s
s
s
s
s
s
6V
9V
7V
V
V
V
26V
V
max
IN
Line Regulation
16V
2
5
25
50
50
mV
mV
mV
IN
max
max
max
26V
IN
s
s
Load Regulation
Output Impedance
Quiescent Current
0.5 mA
I
7.5 mA
6
stby
e
5 mA and 1 mA , f
rms o
120 Hz
0.9
1.2
0.9
X
dc
e
I
7.5 mA
2 mA
2.0
1.5
mA
stby
stby
max
max
e
I
mA
3
Electrical Characteristics (Continued)
e
e
e
e
10 mF, T 25 C (Note 6) unless otherwise indicated
j
V
14V, I
1 mA, C
§
IN
stby
stby
Tested
Limit
Design
Limit
Parameter
Conditions
Typical
Units
(Note 2)
(Note 3)
V
(Continued)
standby
e
Output Noise Voltage
Long Term Stability
Ripple Rejection
Dropout Voltage
Dropout Voltage
Current Limit
10 Hz–100 kHz, I
stby
1 mA
100
20
mV
mV/1000 hr
e
f
o
120 Hz
70
60
0.50
0.60
12
dB
min
max
max
e
e
I
I
1 mA
0.26
0.38
15
0.50
0.70
V
V
stby
stby
7.5 mA
mA
min
s
s
6V
Maximum Operational
Input Voltage
4.5V
V
stby
45
45
35
35
35
35
V
V
V
V
min
e
R
stby
1000X
s
e
Maximum Line
Transient
V
stby
6V,
min
min
min
R
stby
1000X
t
e
b
Reverse Polarity
Input Voltage DC
V
stby
0.6V,
b
b
b
b
b
b
30
55
15
35
15
35
R
stby
1000X
s
e
Reverse Polarity Input
Voltage Transient
T
100 ms, R
1000X
stby
Electrical Characteristics
e
e
e
e
e
10 mF, C 10 mF unless otherwise specified
stby
V
IN
14V, T
25 C (Note 6) C
§
10 mF, C
j
OUT
buf
Tested
Limit
Design
Parameter
Conditions
Typical
Limit
Units
(Note 2)
(Note 3)
Tracking and Isolation
s
s
e
Tracking
I
I
500 mA, I
7.5 mA
5 mA,
OUT
buf
g
g
g
g
g
g
30
30
30
100
100
100
mV
mV
max
max
max
V
–V
OUT
Tracking
–V
stby
stby
s
e
s
I
I
5 mA, I
100 mA,
OUT
buf
V
7.5 mA
buf
Tracking
–V
stby
stby
s
e
s
100 mA,
I
I
500 mA, I
1 mA
OUT
buf
mV
V
OUT
Isolation*
from V
buf
stby
s
e
R
R
R
R
1X, I
100 mA
4.50
5.50
V
min
OUT
buf
5.00
5.00
5.00
5.00
V
V
max
buf
Isolation*
from V
OUT
s
e
1X, I
7.5 mA
500 mA
7.5 mA
4.50
5.50
V
min
OUT
stby
V
V
max
stby
Isolation*
from V
OUT
s
e
1X, I
4.50
5.50
V
min
buf
buf
OUT
stby
V
V
max
OUT
Isolation*
from V
buf
s
e
1X, I
4.50
5.50
V
min
V
stby
V
max
buf
*Isolation refers to the ability of the specified output to remain within the tested limits when the other output is shorted to ground.
4
Electrical Characteristics (Continued)
e
e
otherwise specified
e
e
e
e
e
e
0.47 mF, T 25 C (Note 6) unless
j
V
14V, I
5 mA, I
5 mA, I
5 mA, R
130k, C
0.33 mF, C
§
IN
OUT
buf
stby
t
t
mon
Tested
Limit
Design
Limit
Parameter
Conditions
Typical
Units
(Note 2)
(Note 3)
Computer Monitor/Reset Functions
e
e
e
0.4V
I
Low
V
V
4V, V
rst
5
2
1
mA
min
reset
IN
e
V
Low
4V, I
1 mA
0.10
1.22
1.22
50
0.40
1.15
1.30
45
V
max
reset
IN
rst
R
(Pin 2)
V
min
t voltage
V
max
e
Power On Reset
Delay
VmP
5V
ms
mon
e
min
max
min
(T
dly
1.2 R C )
t t
50
55
ms
V
Low
(Note 4)
(Note 4)
4.00
4.00
5.50
5.50
3.60
4.40
5.25
6.00
V
OUT
Reset Threshold
V
max
V
High
V
min
OUT
Reset Threshold
V
max
e
e
12V
Reset Output
Leakage
VmP
5V, V
mon
rst
0.01
1
mA
max
e
e
mP
Input
VmP
VmP
2.4V
0.4V
7.5
0.01
1.22
1.22
50
25
10
mA
mA
mon
Current (Pin 4)
mon
mon
max
max
min
mP
Input
0.80
2.00
45
0.80
2.00
V
mon
Threshold Voltage
V
max
e
e
mP Monitor Reset
VmP
0V
ms
min
mon
Oscillator Period
(T
window
0.82 R C
t
)
mon
50
55
ms
max
e
mP Monitor Reset
VmP
0V
e
1.0
0.7
1.3
0.5
2.0
ms
min
mon
Oscillator Pulse Width
(RESET
2000 C
)
pw
mon
1.0
ms
max
Minimum mP Monitor
(Note 5)
2
ms
max
Input Pulse Width
s
e
e
e
e
Reset Fall Time
Reset Rise Time
R
R
10k, V
10k, V
2.4V
5V, C
5V, C
10 pF
10 pF
0.20
0.60
7.5
1.00
1.00
25
ms
ms
rst
rst
rst
max
s
rst
rst
rst
max
e
On/Off Switch Input
Current (Pin 8)
V
mA
mA
ON
ON
max
max
min
e
V
0.4V
0.01
1.22
1.22
10
On/Off Switch Input
Threshold Voltage
0.80
2.00
0.80
2.00
V
V
max
Note 1: Thermal resistance without a heatsink for junction-to-case temperature is 3 C/W. Thermal resistance case-to-ambient is 40 C/W.
§
§
Note 2: Tested Limits are guaranteed and 100% production tested.
Note 3: Design Limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are not used to
calculate outgoing quality levels.
Note 4: An internal comparator detects when the main regulator output (V ) drops below 4.0V or rises above 5.5V. If either condition exists at the output, the
OUT
Reset Error Flag is held low until the error condition has terminated. The Reset Error Flag is then allowed to go high again after a delay set by R and C . (See
t
t
Applications Section.)
Note 5: This parameter is a measure of how short a pulse can be detected at the mP Monitor Input. This parameter is primarily influenced by the value of C
.
mon
(See Typical Performance Characteristics and Applications Section.)
Note 6: To ensure constant junction temperature, low duty cycle pulse testing is used.
5
Block Diagram
TL/H/8821–2
Pin Description
Pin No. Pin Name
Comments
1
2
3
4
5
V
R
C
Positive supply input voltage
Sets internal timing currents
Sets power-up reset delay timing
Microcomputer monitor input
Sets mC monitor timing
IN
t
t
mP
mon
C
mon
6
7
8
9
10
11
Ground
Reset
ON/OFF
Regulator ground
Reset error flag output
Enables/disables high current regulators
Standby regulator output (7.5 mA)
Buffer regulator output (100 mA)
Main regulator output (500 mA)
V
V
V
standby
buffer
OUT
External Components
Component Typical Value Component Range
Comments
C
R
1 mF
130k
0.47 mF–10 mF
24k–1.2M
Required if device is located far from power supply filter.
Sets internal timing currents.
IN
t
C
C
R
0.33 mF
0.01 mF
10k
0.033 mF–3.3 mF
0.001 mF–0.1 mF
1k–100k
Sets power-up reset delay.
t
Establishes time constant of AC coupled computer monitor.
tc
tc
Establishes time constant of AC coupled computer monitor. (See
applications section.)
C
R
C
C
C
0.47 mF
10k
0.047 mF–4.7 mF
5k–100k
Sets time window for computer monitor. Also determines period and pulse
width of computer malfunction reset. (See applications section.)
mon
rst
Load for open collector reset output. Determined by computer reset input
requirements.
10 mF
10 mF
10 mF
10 mF–no bound
10 mF–no bound
10 mF–no bound
A 10 mF is required for stability but larger values can be used to maintain
regulation during transient conditions.
stby
buf
A 10 mF is required for stability but larger values can be used to maintain
regulation during transient conditions.
A 10 mF is required for stability but larger values can be used to maintain
regulation during transient conditions.
OUT
6
Typical Circuit Waveforms
TL/H/8821–3
Connection Diagram
TL/H/8821–4
Order Number LM2984CT
See NS Package Number TA11B
7
Typical Performance Characteristics
Dropout Voltage (V
)
Dropout Voltage (V
)
buf
Dropout Voltage (V )
stby
OUT
)
y
TL/H/8821–5
8
Typical Performance Characteristics (Continued)
Quiescent Current (V
)
Quiescent Current (V
)
buf
Quiescent Current (V )
stby
OUT
)
tby
TL/H/8821–6
9
Typical Performance Characteristics (Continued)
Line Transient
Response (V
Line Transient
Response (V
Line Transient
Response (V
)
OUT
)
buf
)
stby
TL/H/8821–7
10
Typical Performance Characteristics (Continued)
Device Dissipation vs
Ambient Temperature
Output Voltage
TL/H/8821–9
TL/H/8821–8
Output Capacitor ESR
(Standby Output, Pin 9)
Output Capacitor ESR
(Buffer Output, Pin 10)
Output Capacitor ESR
(Main Output, Pin 11)
TL/H/8821–13
TL/H/8821–14
TL/H/8821–15
Application Hints
OUTPUT CAPACITORS
outputs are controlled with the ON/OFF pin described later,
the standby output remains on under all conditions as long
as sufficient input voltage is supplied to the IC. Thus, memo-
ry and other circuits powered by this output remain unaffect-
ed by positive line transients, thermal shutdown, etc.
The LM2984C output capacitors are required for stability.
Without them, the regulator outputs will oscillate, sometimes
by many volts. Though the 10 mF shown are the minimum
recommended values, actual size and type may vary de-
pending upon the application load and temperature range.
Capacitor effective series resistance (ESR) also affects the
IC stability. Since ESR varies from one brand to the next,
some bench work may be required to determine the mini-
mum capacitor value to use in production. Worst case is
usually determined at the minimum ambient temperature
and the maximum load expected.
The standby regulator circuit is designed so that the quies-
k
cent current to the IC is very low ( 1.5 mA) when the other
regulator outputs are off.
The capacitor on the output of this regulator can be in-
creased without bound. This will help maintain the output
voltage during negative input transients and will also help to
reduce the noise on all three outputs. Because the other
two track the standby output: therefore any noise reduction
here will also reduce the other two noise voltages.
Output capacitors can be increased in size to any desired
value above the minimum. One possible purpose of this
would be to maintain the output voltages during brief condi-
tions of negative input transients that might be characteris-
tic of a particular system.
BUFFER OUTPUT
The buffer output is designed to drive peripheral sensor cir-
cuitry in a mP system. It will track the standby and main
regulator within a few millivolts in normal operation. There-
fore, a peripheral sensor can be powered off this supply and
have the same operating voltage as the mP system. This is
important if a ratiometric sensor system is being used.
Capacitors must also be rated at all ambient temperatures
expected in the system. Many aluminum type electrolytics
b
will freeze at temperatures less than 30 C, reducing their
effective capacitance to zero. To maintain regulator stability
§
b
down to 40 C, capacitors rated at that temperature (such
as tantalums) must be used.
§
The buffer output can be short circuited while the other two
outputs are in normal operation. This protects the mP sys-
tem from disruption of power when a sensor wire, etc. is
temporarily shorted to ground, i.e. only the sensor signal
would be interrupted, while the mP and memory circuits
would remain operational.
Each output must be terminated by a capacitor, even if it is
not used.
STANDBY OUTPUT
The standby output is intended for use in systems requiring
standby memory circuits. While the high current regulator
The buffer output is similar to the main output in that it is
controlled by the ON/OFF switch in order to save power in
11
Application Hints (Continued)
the standby mode. It is also fault protected against overvolt-
age and thermal overload. If the input voltage rises above
approximately 30V (e.g. load dump), this output will auto-
matically shut down. This protects the internal circuitry and
enables the IC to survive higher voltage transients than
would otherwise be expected. Thermal shutdown is neces-
sary since this output is one of the dominant sources of
power dissipation in the IC.
DELAYED RESET
Resistor R and capacitor C set the period of time that the
RESET output is held low after a main output error condition
has been sensed. The delay is given by the formula:
t
t
e
T
1.2 R C (seconds)
t t
dly
The delayed RESET will be initiated any time the main out-
put is outside the 4V to 5.5V window, i.e. during power-up,
short circuit, overvoltage, low line, thermal shutdown or
power-down. The mP is therefore RESET whenever the out-
put voltage is out of regulation. (It is important to note that a
RESET is only initiated when the main output is in error. The
buffer and standby outputs are not directly monitored for
error conditions.)
MAIN OUTPUT
The main output is designed to power relatively large loads,
i.e. approximately 500 mA. It is therefore also protected
against overvoltage and thermal overload.
This output will track the other two within a few millivolts in
normal operation. It can therefore be used as a reference
voltage for any signal derived from circuitry powered off the
standby or buffer outputs. This is important in a ratiometric
sensor system or any system requiring accurate matching of
power supply voltages.
mP MONITOR RESET
There are two distinct and independent error monitoring
systems in the LM2984C. The one described above moni-
tors the main regulator output and initiates a delayed RE-
SET whenever this output is in error. The other error moni-
toring system is the mP watchdog. These two systems are
OR’d together internally and both force the RESET output
low when either type of error occurs.
ON/OFF SWITCH
The ON/OFF switch controls the main output and the buffer
output. The threshold voltage is compatible with most logic
families and has about 20 mV of hysteresis to insure ‘clean’
switching from the standby mode to the active mode and
vice versa. This pin can be tied to the input voltage through
a 10 kX resistor if the regulator is to be powered continu-
ously.
This watchdog circuitry continuously monitors a pin on the
mP that generates a positive going pulse during normal op-
eration. The period of this pulse is typically on the order of
milliseconds and the pulse width is typically on the order of
10’s of microseconds. If this pulse ever disappears, the
watchdog circuitry will time out and a RESET low will be
sent to the mP. The time out period is determined by two
POWER DOWN OVERRIDE
Another possible approach is to use a diode in series with
the ON/OFF signal and another in series with the main out-
put in order to maintain power for some period of time after
the ON/OFF signal has been removed (seeFigure 1). When
the ON/OFF switch is initially pulled high through diode D1,
the main output will turn on and supply power through diode
D2 to the ON/OFF switch effectively latching the main out-
put. An open collector transistor Q1 is connected to the
ON/OFF pin along with the two diodes and forces the regu-
lators off after a period of time determined by the mP. In this
way, the mP can override a power down command and store
data, do housekeeping, etc. before reverting back to the
standby mode.
external components, R and C
t
la:
, according to the formu-
mon
e
T
0.82 R C (seconds)
mon
window
t
The width of the RESET pulse is set by C
nal resistor according to the following:
and an inter-
mon
e
RESET
pw
2000 C
mon
(seconds)
A square wave signal can also be monitored for errors by
filtering the C input such that only the positive edges of
mon
the signal are detected. Figure 2 is a schematic diagram of a
typical circuit used to differentiate the input signal. Resistor
R
and capacitor C pass only the rising edge of the
tc
tc
square wave and create a short positive pulse suitable for
the mP monitor input. If the incoming signal continues in a
high state or in a low state for too long a period of time, a
RESET low will be generated.
TL/H/8821–10
FIGURE 1. Power Down Override
RESET OUTPUT
TL/H/8821–11
This output is an open collector NPN transistor which is
forced low whenever an error condition is present at the
main output or when a mP error is sensed (see mP Monitor
section). If the main output voltage drops below 4V or rises
above 5.5V, the RESET output is forced low and held low
FIGURE 2. Monitoring Square Wave mP Signals
The threshold voltage and input characteristics of this pin
are compatible with nearly all logic families.
There is a limit on the width of a pulse that can be reliably
detected by the watchdog circuit. This is due to the output
for a period of time set by two external components, R and
t
C . There is a slight amount of hysteresis in these two
t
threshold voltages so that the RESET output has a fast rise
and fall time compatible with the requirements of most mP
RESET inputs.
resistance of the transistor which discharges C
when a
mon
high state is detected at the input. The minimum detectable
pulse width can be determined by the following formula:
e
PW
min
20 C (seconds)
mon
12
Equivalent Schematic Diagram
13
Ý
Lit. 108032-1
Physical Dimensions inches (millimeters)
Molded TO-220 Package (TA)
Order Number LM2984CT
NS Package Number TA11A
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