LM2833XMYX_技术文档

January 13, 2009

LM2833

1.5MHz/3MHz 3.0A Step-Down DC-DC Switching Regulator

General Description

Features

The LM2833 regulator is a monolithic, high frequency, PWM

step-down DC/DC converter available in a 10-pin LLP or eM-

SOP package. It contains all the active functions to provide

local DC/DC conversion with fast transient response and ac-

curate regulation in the smallest possible PCB area. With a

minimum of external components, the LM2833 is easy to use.

The ability to drive 3.0A loads with an internal 56 mΩ PMOS

switch using state-of-the-art 0.5µm BiCMOS technology re-

sults in the best power density available. The world-class

control circuitry allows on-times as low as 30ns, thus sup-

porting exceptionally high frequency conversion over the en-

tire 3V to 5.5V input operating range down to the minimum

output voltage of 0.6V. Switching frequency is internally set

to 1.5MHz or 3.0MHz, allowing the use of extremely small

surface mount inductors and capacitors. Even though the op-

erating frequency is high, efficiencies up to 93% are easy to

achieve. External shutdown is included, featuring an ultra-low

stand-by current of 300nA. The LM2833 utilizes peak current-

mode control and internal compensation to provide high-

performance regulation over a wide range of operating

conditions. Additional features include internal soft-start cir-

Input voltage range of 3.0V to 5.5V

■

Output voltage range of 0.6V to 4.5V

Tiny eMSOP-10 or LLP-10 package

3.0A steady-state output current

High switching frequencies

1.5MHz (LM2833X)

3.0MHz (LM2833Z)

■

Enable pin

■

56mΩ PMOS switch

0.6V, 2% internal voltage reference over line and

temperature

Internal soft-start

■

Internally compensated peak current-mode control

Cycle-by-cycle current limit and thermal shutdown

Frequency foldback protection

Input voltage UVLO (Under-voltage lockout)

Output over-voltage protection

cuitry to reduce inrush current, cycle-by-cycle current limit, Applications

frequency foldback, thermal shutdown, and output over-volt-

age protection.

Multimedia Set Top Box

■

Broadband Communications

Core Power in HDDs

Data Acquisition/Telemetry

USB Powered Devices

DSL Modems

Typical Application Circuit

30013201

30013212

300132

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Connection Diagrams

30013203

30013202

10-pin LLP

10-pin eMSOP

Ordering Information

Frequency

Order Number

NSC Package

Drawing

Package Type

eMSOP-10

LLP-10

Top Mark

SPYB

Supplied As

Option

LM2833XMY

1000 units Tape and Reel

3500 units Tape and Reel

1000 units Tape and Reel

4500 units Tape and Reel

1000 units Tape and Reel

3500 units Tape and Reel

1000 units Tape and Reel

4500 units Tape and Reel

MUC10A

SDA10A

MUC10A

SDA10A

LM2833XMYX

1.5MHz

LM2833XSD

2833X

SPZB

LM2833XSDX

LM2833ZMY

eMSOP-10

LLP-10

LM2833ZMYX

3MHz

LM2833ZSD

2833Z

LM2833ZSDX

Pin Descriptions

Pin(s)

Name

Description

1

VINC

Input supply for internal bias and control circuitry. Need to locally bypass this pin to GND.

Enable control input. Logic high enables operation. Do not allow this pin to float or subject

to voltages greater than V_IN+ 0.3V.

2

3

EN

Signal (analog) ground. Place the bottom resistor of the feedback network as close as

possible to this pin for good load regulation.

SGND

4

5

NC

FB

No user function, connect this pin to GND.

Feedback pin. Connect this pin to the external resistor divider to set output voltage.

Power ground pin. Provides ground return path for the internal driver.

Switch pins. Connect these pins to the inductor and catch diode.

Input supply voltage. Connect a bypass capacitor locally from these pins to PGND.

6

PGND

SW

7, 8

9, 10

VIND

Connect to system ground for low thermal impedance, but it cannot be used as a primary

GND connection.

DAP

Die Attach Pad

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2

Junction Temperature (Note 2)

Storage Temperature

Soldering Information

150°C

−65°C to +150°C

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Infrared/Convection Reflow (15sec)

220°C

VINC, VIND

FB Voltage

EN Voltage

SW Voltage

-0.5V to 7V

-0.5V to 3V

-0.5V to 7V

2kV

Operating Ratings

VINC, VIND

3V to 5.5V

−40°C to +125°C

Junction Temperature

ESD Susceptibility (Note 4)

Electrical Characteristics Unless otherwise specified under the Conditions column, V_IN= 5V. Limits in standard

type are for T_J= 25°C only; limits in boldface type apply over the junction temperature (T_J) range of -40°C to +125°C. Minimum

and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely

parametric norm, and are provided for reference purposes only.

Symbol

Parameter

Feedback Voltage

Conditions

LLP-10 Package

eMSOP-10 Package

V_IN= 3V to 5.5V

Min

Typ

0.600

0.08

Max

0.612

0.616

Units

0.588

0.584

V_FB

V

Feedback Voltage Line Regulation

Feedback Input Bias Current

%/V

nA

ΔV_FB/(ΔV_INxV_FB

)

I_B

0.1

2.70

2.35

0.35

1.5

3.0

95

100

V_INRising

V_INFalling

2.90

Undervoltage Lockout

UVLO Hysteresis

V

UVLO

1.85

LM2833X

1.1

2.25

86

1.95

3.75

f_SW

Switching Frequency

MHz

LM2833Z

LM2833X

D_MAX

D_MIN

R_DS(ON)

I_CL

Maximum Duty Cycle

Minimum Duty Cycle

Switch On Resistance

%

LM2833Z

80

90

LM2833X

5

LM2833Z

7

LLP-10 Package

eMSOP-10 Package

58

90

mΩ

A

56

Switch Current Limit

Enable Threshold Voltage

Shutdown Threshold Voltage

Switch Leakage

3.4

1.8

4.4

V_{EN_TH}

V

0.4

I_SW

I_EN

100

3.2

nA

Enable Pin Current

Sink/Source

LM2833X, V_FB= 0.55

LM2833Z, V_FB= 0.55

All Options V_EN= 0V

All Options

5

Quiescent Current (switching)

mA

I_Q

4.3

6.5

Quiescent Current (shutdown)

300

0.32

400

800

nA

V

V_{FB_F}

f_FB

FB Frequency Foldback Threshold

LM2833X, V_FB= 0V

LM2833Z, V_FB= 0V

Foldback Frequency

kHz

3

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Symbol

Parameter

Junction to Ambient

0 LFPM Air Flow (Note 3)

Junction to Case (Note 3)

Thermal Shutdown Threshold

Conditions

LLP-10 Package

Min

Typ

53

Max

Units

θ_JA

°C/W

eMSOP-10 Package

LLP-10 Package

50

12

θ_JC

°C/W

°C

eMSOP-10 Package

11

T_SD

Junction Temperature

Rising

165

15

T_{SD_HYS}

Thermal Shutdown Hysteresis

Junction Temperature

Falling

°C

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be

operated beyond such conditions.

Note 2: Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.

Note 3: Applies for packages soldered directly onto a 4” x 3” 4-layer standard JEDEC board in still air.

Note 4: Human body model, 1.5kΩ in series with 100pF.

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Typical Performance Characteristics

Unless otherwise specified, V_IN= 5V and T_A= 25°C.

Efficiency vs Load Current - "LM2833X" and "LM2833Z"

Efficiency vs Load Current - "LM2833X"

30013213

30013214

Efficiency vs Load Current - "LM2833Z"

Oscillator Frequency vs Temperature - "LM2833X"

30013215

30013225

Oscillator Frequency vs Temperature - "LM2833Z"

Current Limit vs Temperature

30013226

30013227

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R_DS(ON)vs Temperature (LLP-10 Package)

R_DS(ON)vs Temperature (eMSOP-10 Package)

30013229

30013230

LM2833X I_Q(Quiescent Current)

LM2833Z I_Q(Quiescent Current)

30013231

30013232

V_FBvs Temperature

Frequency Foldback

30013228

30013233

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Loop Gain and Phase - "LM2833X"

Loop Gain and Phase - "LM2833Z"

30013235

30013236

Load Step Response - "LM2833X"

Line Transient Response - "LM2833X"

30013247

30013248

Startup by EN - "LM2833X"

Shutdown by EN - "LM2833X"

30013252

30013253

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Startup with EN tied to V_IN- "LM2833X"

Short-circuit Triggering - "LM2833X"

30013250

30013254

Short-circuit Release - "LM2833X"

Recovery from Thermal Shutdown - "LM2833X"

30013251

30013240

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8

Block Diagram

30013269

FIGURE 1. Simplified Block Diagram

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required to initiate switching. Do not allow this pin to float or

rise to 0.3V above V_IN. It should be noted that when the EN

pin voltage rises above 1.8V while the input voltage is greater

than UVLO, there is 15µs delay before switching starts. Dur-

ing this delay the LM2833 will go through a power on reset

state after which the internal soft-start process commences.

During soft-start, the error amplifier’s reference voltage ramps

from 0V to its nominal value of 0.6V in approximately 600µs.

This forces the regulator output to ramp up in a controlled

fashion, which helps reduce inrush current seen at the input

and minimizes output voltage overshoot.

Application Information

THEORY OF OPERATION

The LM2833 is a constant frequency PWM buck regulator IC

that delivers a 3.0A load current. The regulator is available in

preset switching frequencies of 1.5MHz or 3.0MHz. This high

frequency allows the LM2833 to operate with small surface

mount capacitors and inductors, resulting in a DC/DC con-

verter that requires a minimum amount of board space. The

LM2833 is internally compensated, therefore it is simple to

use and requires few external components. The LM2833 uses

peak current-mode control to regulate the output voltage. The

following description of operation of the LM2833 will refer to

the Typical Application Circuit, to the waveforms in Figure 2

and simplified block diagram in Figure 1. The LM2833 sup-

plies a regulated output voltage by switching the internal

PMOS power switch at a constant frequency and variable du-

ty cycle. A switching cycle begins at the falling edge of the

reset pulse generated by the internal oscillator. When this

pulse goes low, the output control logic turns on the internal

PMOS power switch. During this on-time, the SW pin voltage

(V_SW) swings up to approximately V_IN, and the inductor cur-

rent (I_L) increases with a linear slope. I_Lis measured by the

current sense amplifier, which generates an output propor-

tional to the switch current. The sense signal is summed with

the regulator’s corrective ramp and compared to the error

amplifier’s output, which is proportional to the difference be-

tween the feedback voltage and V_REF. When the PWM com-

parator output goes high, the internal power switch turns off

until the next switching cycle begins. During the switch off-

time, the inductor current discharges through the catch diode

D1, which forces the SW pin to swing below ground by the

forward voltage (V_D) of the catch diode. The regulator loop

adjusts the duty cycle (D) to maintain a constant output volt-

age.

The simplest way to enable the operation of the LM2833 is to

connect the EN pin to V_INwhich allows self start-up of the

LM2833 whenever the input voltage is applied. However,

when an input voltage of slow rise time is used to power the

application and if both the input voltage and the output voltage

are not fully established before the soft-start time elapses, the

control circuit will command maximum duty cycle operation of

the internal power switch to bring up the output voltage rapid-

ly. When the feedback pin voltage exceeds 0.6V, the duty

cycle will have to reduce from the maximum value according-

ly, to maintain regulation. It takes a finite amount of time for

this reduction of duty cycle and this can result in a transient

in output voltage for a short duration, as shown in Figure 3. In

applications where this output voltage overshoot is undesir-

able, one simple solution is to add a feed-forward capacitor

(C_FF) across the top feedback resistor R1 to speed Gm Am-

plifier recovery. In practice, a 27nF to 100nF ceramic capac-

itor is usually a good choice to remove the overshoot

completely or limit the overshoot to an insignificant level dur-

ing startup, as shown in Figure 4. Another more effective

solution is to control EN pin voltage by a separate logic signal,

and pull the signal high only after V_INis fully established. In

this way, the chip can execute a normal, complete soft start

process, minimizing any output voltage overshoot. Under

some circumstances at cold temperature, this approach may

also be required to minimize any unwanted output voltage

transients that may occur when the input voltage rises slowly.

For a fast rising input voltage (100µs for example), there is no

need to control EN separately or add a feed-forward capacitor

since the soft-start can bring up output voltage smoothly as

shown in Figure 5.

During startup, the LM2833 gradually increases the switching

frequency from 400kHz (LM2833X) or 800kHz (LM2833Z) to

the nominal fixed value, as the feedback voltage increases

(see Frequency Foldback section for more information).

Since the internal corrective ramp signal adjusts its slope dy-

namically, and is proportional to the switching frequency dur-

ing startup, a larger output capacitance may be required to

insure a smooth output voltage rise, at low programmed out-

put voltage and high output load current.

30013266

FIGURE 2. SW Pin Voltage and Inductor Current

Waveforms

SOFT-START/SHUTDOWN

The LM2833 has both enable and shutdown modes that are

controlled by the EN pin. Connecting a voltage source greater

than 1.8V to the EN pin enables the operation of the LM2833,

while reducing this voltage below 0.4V places the part in a low

quiescent current (300nA typical) shutdown mode. There is

no internal pull-up on EN pin, therefore an external signal is

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FREQUENCY FOLDBACK

The LM2833 uses frequency foldback to help limit switch cur-

rent and power dissipation during start-up, short-circuit and

over load conditions by sensing if the feedback voltage is be-

low 0.32V (typical). The LM2833 will reduce the switching

frequency from the nominal fixed value (1.5MHz or 3.0MHz)

down to 400kHz (LM2833X) or 800kHz (LM2833Z) when the

feedback voltage drops to 0V. See the Frequency Foldback

plot in the Typical Performance Characteristics section.

LOAD STEP RESPONSE

The LM2833 has a fixed internal loop compensation, which

results in a small-signal loop bandwidth highly related to the

output voltage level. In general, the loop bandwidth at low

voltage is larger than at high voltage due to the increased

overall loop gain. The limited bandwidth at high output voltage

may pose a challenge when loop step response is concerned.

In this case, one effective approach to improving loop step

response is to add a feed-forward capacitor (C_FF) in the range

of 27nF to 100nF in parallel with the upper feedback resistor

(assuming the lower feedback resistor is 2kΩ), as shown in

Figure 6. The feed-forward capacitor introduces a zero-pole

pair which helps compensate the loop. The position of the

zero-pole pair is a function of the feedback resistors and ca-

pacitor:

30013260

FIGURE 3. Startup Response to V_IN

Note the factor in parenthesis is the ratio of the output voltage

to the feedback voltage. As the output voltage gets close to

0.6V, the pole moves towards the zero, tending to cancel it

out. Consequently, adding C_FFwill have less effect on the step

response at lower output voltages.

30013261

As an example, Figure 8 shows that at the output voltage of

3.3V, a 47nF of C_FFcan boost the loop bandwidth to 117kHz,

from the original 23kHz as shown in Figure 7. Correspond-

ingly, the responses to a load step between 0.3A and 3A

without and with C_FFare shown in Figure 9 and Figure 10

respectively. The higher loop bandwidth as a result of C_FFre-

duces the total output excursion by more than half.

FIGURE 4. Startup Response to V_INwith C_FF

Aside from the above approach, increasing the output capac-

itance is generally also effective to reduce the excursion in

output voltage caused by a load step. This approach remains

valid for applications where the desired output voltages are

close to the feedback voltage.

30013262

FIGURE 5. Startup Response to V_INwith 100µs rise time

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30013255

FIGURE 6. Adding a C_FFCapacitor

30013245

FIGURE 9. Load Step Response without C_FF

30013237

FIGURE 7. Loop Gain and Phase without C_FF

30013246

FIGURE 10. Load Step Response with C_FF

OUTPUT OVER-VOLTAGE PROTECTION

The LM2833 has a built in output over-voltage comparator

that compares the FB pin voltage to a threshold voltage that

is 15% higher than the internal reference V_REF. Once the FB

pin voltage exceeds this threshold level (typically 0.69V), the

internal PMOS power switch is turned off, which allows the

output voltage to decrease towards regulation.

UNDER-VOLTAGE LOCKOUT

Under-voltage lockout (UVLO) prevents the LM2833 from op-

erating until the input voltage exceeds 2.70V (typical). The

UVLO threshold has approximately 350mV of hysteresis, so

the part will operate until V_INdrops below 2.35V (typical).

Hysteresis prevents the part from turning off during power up

if V_INis non-monotonic.

30013238

CURRENT LIMIT

FIGURE 8. Loop Gain and Phase with C_FF

The LM2833 uses cycle-by-cycle current limiting to protect

the internal power switch. During each switching cycle, a cur-

rent limit comparator detects if the power switch current ex-

ceeds 4.4A (typical), and turns off the switch until the next

switching cycle begins.

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THERMAL SHUTDOWN

steep down slope of inductor current, which will result in an

insufficient slope compensation, and cause instability known

as sub-harmonic oscillation. Another consideration is at low

load current, one needs to ensure that the inductance value

given by the guideline should not exceed 10µH for the

LM2833X and 4.7µH for the LM2833Z, since too much induc-

tance effectively flattens the down slope of the inductor cur-

rent, and may significantly limit the system bandwidth and

phase margin resulting in instability.

Thermal shutdown limits total power dissipation by turning off

the internal power switch when the IC junction temperature

typically exceeds 165°C. After thermal shutdown occurs, the

power switch does not turn on again until the junction tem-

perature drops below approximately 150°C.

Design Guide

The LM2833 operates at frequencies allowing the use of ce-

ramic output capacitors without compromising transient re-

sponse. Ceramic capacitors allow higher inductor ripple

without significantly increasing output ripple. See the output

capacitor section for more details on calculating output volt-

age ripple.

INDUCTOR SELECTION

The Duty Cycle (D) can be approximated quickly using the

ratio of output voltage (V_OUT) to input voltage (V_IN):

Now that the ripple current is determined, the inductance is

calculated by:

The catch diode (D1) forward voltage drop and the voltage

drop across the internal PMOS must be included to calculate

a more accurate duty cycle. Calculate D by using the following

formula:

where f_SWis the switching frequency. When selecting an in-

ductor, make sure that it is capable of supporting the peak

output current without saturating. Inductor saturation will re-

sult in a sudden reduction in inductance and prevent the

regulator from operating properly. Because of the operating

frequency of the LM2833, ferrite based inductors are pre-

ferred to minimize core losses. This presents little restriction

since the variety and availability of ferrite-based inductors is

large. Lastly, inductors with lower series resistance (DCR) will

provide better operating efficiency. For recommended induc-

tor selection, refer to Design Examples.

V_SWcan be approximated by:

V_SW= I_OUTx R_DS(ON)

Where I_OUTis output load current. The diode forward drop

(V_D) can range from 0.3V to 0.7V depending on the quality of

the diode. The lower the V_D, the higher the operating efficien-

cy of the converter.

The inductor value determines the output ripple current (Δi_L,

as defined in Figure 2). Lower inductor values decrease the

size of the inductor, but increase the output ripple current. An

increase in the inductor value will decrease the output ripple

current. In general, the ratio of ripple current to the output

current is optimized when it is set between 0.2 and 0.4 for

output currents above 2A. This ratio r is defined as:

INPUT CAPACITOR

An input capacitor is necessary to ensure that V_INdoes not

drop excessively during switching transients. The primary

specifications of the input capacitor are capacitance, voltage

rating, RMS current rating, and ESL (Equivalent Series In-

ductance). The input voltage rating is specifically stated by

the capacitor manufacturer. Make sure to check any recom-

mended deratings and also verify if there is any significant

change in capacitance at the operating input voltage and the

operating temperature. The input capacitor maximum RMS

input current rating (I_RMS-IN) must be greater than:

One must ensure that the minimum current limit (3.4A) is not

exceeded, so the peak current in the inductor must be calcu-

lated. The peak current (I_LPK) in the inductor is calculated by:

I_LPK= I_OUT+ Δi_L/2

Neglecting inductor ripple simplifies the above equation to:

When the designed maximum output current is reduced, the

ratio r can be increased. At a current of 0.1A, r can be made

as high as 0.9. The ripple ratio can be increased at lighter

loads because the net ripple is actually quite low, and if r re-

mains constant the inductor value can be made quite large.

An equation empirically developed for the maximum ripple

ratio at any current below 2A is:

It can be shown from the above equation that maximum RMS

capacitor current occurs when D = 0.5. Always calculate the

RMS at the point where the duty cycle D is closest to 0.5. The

ESL of an input capacitor is usually determined by the effec-

tive cross sectional area of the current path. As a rule of

thumb, a large leaded capacitor will have high ESL and a 1206

ceramic chip capacitor will have very low ESL. At the operat-

ing frequencies of the LM2833, leaded capacitors may have

an ESL so large that the resulting impedance (2πfL) will be

higher than that required to provide stable operation. It is

strongly recommended to use ceramic capacitors due to their

low ESR and low ESL. A 22µF multilayer ceramic capacitor

-0.3667

r = 0.387 x I_OUT

Note that this is just a guideline, and it needs to be combined

with two important factors for proper selection of inductance

values at any operating condition. The first consideration is at

output voltage above 2.5V, one needs to ensure that the in-

ductance given by the above guideline should not be less than

1µH for the LM2833X or 0.5µH for the LM2833Z. Since the

LM2833 has a fixed internal corrective ramp signal, a very low

inductance value at high output voltage will generate a very

13

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(MLCC) is a good choice for most applications. In cases

where large capacitance is required, use surface mount ca-

pacitors such as Tantalum capacitors and place at least a

4.7µF ceramic capacitor close to the V_INpin. For MLCCs it is

recommended to use X7R or X5R dielectrics. Consult capac-

itor manufacturer datasheet to see how rated capacitance

varies over operating conditions.

V_REF= 0.60V

EFFICIENCY ESTIMATION

The complete LM2833 DC/DC converter efficiency can be

calculated in the following manner:

OUTPUT CAPACITOR

The output capacitor is selected based upon the desired out-

put ripple and transient response. The initial current of a load

transient is provided mainly by the output capacitor. The out-

put ripple of the converter is:

Or

When using MLCCs, the ESR is typically so low that the ca-

pacitive ripple may dominate. When this occurs, the output

ripple will be approximately sinusoidal and 90° phase shifted

from the switching action. Given the availability and quality of

MLCCs and the expected output voltage of designs using the

LM2833, there is really no need to review any other capacitor

technologies. Another benefit of ceramic capacitors is their

ability to bypass high frequency noise. A certain amount of

switching edge noise will couple through parasitic capaci-

tances in the inductor to the output. A ceramic capacitor will

bypass this noise while a tantalum will not. Since the output

capacitor is one of the two external components that control

the stability of the regulator control loop, most applications will

require a minimum of 22µF output capacitance. In the case of

low output voltage, a larger output capacitance is required to

ensure sufficient phase margin. Capacitance can often, but

not always, be increased significantly with little detriment to

the regulator stability. Like the input capacitor, recommended

multilayer ceramic capacitors are X7R or X5R types. Again,

verify actual capacitance at the desired operating voltage and

temperature. Check the RMS current rating of the capacitor.

The maximum RMS current rating of the capacitor is:

Calculations for determining the most significant power loss-

es are shown below. Other losses totaling less than 2% are

not discussed.

The main power loss (P_LOSS) in the converter includes two

basic types of losses: switching loss and conduction loss. In

addition, there is loss associated with the power required for

the internal circuitry of IC. Conduction losses usually domi-

nate at higher output loads, whereas switching losses domi-

nate at lower output loads. The first step in determining the

losses is to calculate the duty cycle (D):

V_SWis the voltage drop across the internal power switch when

it is on, and is equal to:

V_SW= I_OUTx R_DS(ON)

V_Dis the forward voltage drop across the catch diode. It can

be obtained from the diode manufactures Electrical Charac-

teristics section. If the DC voltage drop across the inductor

(V_DCR) is accounted for, the equation becomes:

One may select a 1206 size MLCC for output capacitor, since

its current rating is typically above 1A, more than enough for

the requirement.

CATCH DIODE

The catch diode conducts during the switch off-time. A Schot-

tky diode is recommended for its fast switching time and low

forward voltage drop. The catch diode should be chosen such

that its current rating is greater than:

The conduction losses in the catch diode are calculated as

follows:

I_D= I_OUTx (1-D)

P_DIODE= V_Dx I_OUTx (1-D)

The reverse breakdown rating of the diode must be at least

the maximum input voltage plus appropriate margin. To im-

prove efficiency, choose a Schottky diode with a low forward

voltage drop.

Often this is the single most significant power loss in the cir-

cuit. Care should be taken to choose a Schottky diode with a

low forward voltage drop.

OUTPUT VOLTAGE

Another significant external power loss is the conduction loss

in the output inductor. The equation can be simplified to:

The output voltage is set using the following equation where

R2 is connected between the FB pin and GND, and R1 is

connected between V_OUTand the FB pin. A good value for R2

is 2kΩ.

P_IND= I_OUT²x R_DCR

The LM2833 conduction loss is mainly associated with the

internal power switch:

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PCB LAYOUT CONSIDERATIONS

When planning layout there are a few things to consider to

achieve a clean, regulated output. The most important con-

sideration is the close coupling of the GND connections of the

input capacitor C1 and the catch diode D1. These ground

ends should be close to one another and be connected to the

GND plane with at least two through-holes. Place these com-

ponents as close to the IC as possible. The next consideration

is the location of the GND connection of the output capacitor

C2, which should be near the GND connections of C1 and D1.

There should be a continuous ground plane on the bottom

layer of a two-layer board except under the switching node

island. The signal ground SGND (pin 3) and power ground

PGND (pin 6) should be tied together and connected to

ground plane through vias.

If the inductor ripple current is fairly small, the conduction

losses can be simplified to:

P_COND= I_OUT²x R_DS(ON)x D

Switching losses are also associated with the internal power

switch. They occur during the switch on and off transition pe-

riods, where voltages and currents overlap resulting in power

loss. The simplest means to determine this loss is to empiri-

cally measuring the rise and fall times (10% to 90%) of the

switch at the switch node.

Switching Power Loss is calculated as follows:

P_SWR= 0.5 x (V_INx I_OUTx f_SWx T_RISE

)

The FB pin is a high impedance node and care should be

taken to make the FB trace short to avoid noise pickup that

causes inaccurate regulation. The feedback resistors should

be placed as close as possible to the IC, with the GND of R2

placed as close as possible to the SGND of the IC. The

V_OUTtrace to R1 should be routed away from the inductor and

any other traces that are switching.

P_SWF= 0.5 x (V_INx I_OUTx f_SWx T_FALL

P_SW= P_SWR+ P_SWF

)

The power loss required for operation of the internal circuitry

is given by:

P_Q= I_Qx V_IN

High AC currents flow through the V_IN, SW and V_OUTtraces,

so they should be as short and wide as possible. Radiated

noise can be decreased by choosing a shielded inductor.

I_Qis the quiescent operating current, and is typically around

3.2mA for the LM2833X, and 4.3mA for the LM2833Z.

An example of efficiency calculation for a typical application

is shown in Table 1:

The remaining components should also be placed as close

as possible to the IC. Please see Application Note AN-1229

for further considerations and the LM2833 demo board as an

example of a four-layer layout.

TABLE 1. Power Loss Tabulation

Conditions

Power loss

V_IN

V_OUT

I_OUT

V_D

5V

3.3V

3.0A

P_OUT

P_DIODE

P_COND

9.9W

0.33V

277mW

363mW

R_DS(ON)

f_SW

56mΩ

1.5MHz

10ns

T_RISE

T_FALL

IND_DCR

I_Q

P_SW

225mW

10ns

P_IND

P_Q

252mW

16mW

28mΩ

3.2mA

89.7%

η

D is calculated to be 0.72

P_LOSS= Σ ( P_COND+ P_SW+ P_Q+ P_IND+ P_DIODE

)

P_LOSS= 1.133W

15

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LM2833X Design Example 1

30013207

FIGURE 11. LM2833X (1.5MHz): V_IN= 3.3V, Output = 1.2V/3.0A

Bill of Materials

Part ID

Part Value

Manufacturer

NSC

Part Number

LM2833X

U1

3.0A Buck Regulator

22µF, 6.3V, X5R

47µF, 6.3V, X5R

0.22µF, 10V, X7R

Schottky, 0.33V at 3A, V_R=30V

1.8µH, 3.6A

C1, Input Cap

TDK

C3216X5R0J226M

C3216X5R0J476M

GRM216R71A224KC01D

CMS01

C2, Output Cap

TDK

C3, Bypass Cap

Murata

Toshiba

TDK

D1, Catch Diode

L1

R1

R2

R3

LTF5022T-1R8N3R6

CRCW08052K00FKEA

CRCW080510R0FKEA

Vishay

2.0kΩ, 1%

10Ω, 1%

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16

LM2833X Design Example 2

30013267

FIGURE 12. LM2833X (1.5MHz): V_IN= 5V, Output = 3.3V/3.0A

Bill of Materials

Part ID

Part Value

Manufacturer

NSC

Part Number

LM2833X

U1

3.0A Buck Regulator

22µF, 6.3V, X5R

47µF, 6.3V, X5R

0.22µF, 10V, X7R

47nF, 10V, X7R

Schottky, 0.43V at 3A, V_R=30V

1.2µH, 4.2A

C1, Input Cap

TDK

C3216X5R0J226M

C3216X5R0J476M

GRM216R71A224KC01D

0805ZC473JAZ2A

SSA33L-E3/61T

C2, Output Cap

TDK

C3, Bypass Cap

Murata

AVX

C_FF, Feed-forward Cap

D1, Catch Diode

Vishay

TDK

L1

R1

R2

R3

LTF5022T-1R2N4R2

CRCW080510K2FKEA

CRCW08052K26FKEA

CRCW080510R0FKEA

Vishay

10.2kΩ, 1%

2.26kΩ, 1%

10Ω, 1%

17

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LM2833Z Design Example 3

30013208

FIGURE 13. LM2833Z (3MHz): V_IN= 3.3V, Output = 1.2V/3.0A

Bill of Materials

Part ID

Part Value

Manufacturer

NSC

Part Number

LM2833Z

U1

3.0A Buck Regulator

22µF, 6.3V, X5R

47µF, 6.3V, X5R

0.22µF, 10V, X7R

Schottky, 0.33V at 3A, V_R=30V

1.0µH, 4.0A

C1, Input Cap

TDK

C3216X5R0J226M

C3216X5R0J476M

GRM216R71A224KC01D

CMS01

C2, Output Cap

TDK

C3, Bypass Cap

Murata

Toshiba

Taiyo Yuden

Vishay

D1, Catch Diode

L1

R1

R2

R3

NP04SZB1R0N

CRCW08052K00FKEA

CRCW080510R0FKEA

2.0kΩ, 1%

Vishay

2.0kΩ, 1%

Vishay

10Ω, 1%

www.national.com

18

LM2833Z Design Example 4

30013268

FIGURE 14. LM2833Z (3MHz): V_IN= 5V, Output = 3.3V/3.0A

Bill of Materials

Part ID

Part Value

Manufacturer

NSC

Part Number

LM2833Z

U1

3.0A Buck Regulator

22µF, 6.3V, X5R

47µF, 6.3V, X5R

0.22µF, 10V, X7R

47nF, 10V, X7R

Schottky, 0.43V at 3A, V_R=30V

1.0µH, 4.0A

C1, Input Cap

TDK

C3216X5R0J226M

C3216X5R0J476M

GRM216R71A224KC01D

0805ZC473JAZ2A

SSA33L-E3/61T

C2, Output Cap

TDK

C3, Bypass Cap

Murata

AVX

C_FF, Feed-forward Cap

D1, Catch Diode

Vishay

Taiyo Yuden

Vishay

L1

R1

R2

R3

NP04SZB1R0N

CRCW080510K2FKEA

CRCW08052K26FKEA

CRCW080510R0FKEA

10.2kΩ, 1%

2.26kΩ, 1%

10Ω, 1%

19

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Physical Dimensions inches (millimeters) unless otherwise noted

10-Lead eMSOP Package

NS Package Number MUC10A

10-Lead LLP Package

NS Package Number SDA10A

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20

Notes

21

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型号：	LM2833XMYX
厂家：	National Semiconductor
描述：	IC 4.4 A SWITCHING REGULATOR, 1.95 kHz SWITCHING FREQ-MAX, PDSO10, MSOP-10, Switching Regulator or Controller 信息通信管理开关光电二极管
文件：	总22页 (文件大小：576K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM2833XMYX [NSC]

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