LM1770UMFX_技术文档

September 2005

LM1770

SOT-23 Synchronous Buck Controller

General Description

Features

n Input voltage range of 2.8V to 5.5V

n 0.8V reference voltage

The LM1770 is an efficient synchronous buck switching con-

troller in a tiny SOT23 package. The constant on-time control

scheme provides a simple design free of compensation com-

ponents, allowing minimal component count and board

space. It also incorporates a unique input feed-forward to

maintain a constant frequency independent of the input volt-

age. The LM1770 is optimized for a low voltage input range

of 2.8V to 5.5V and can provide an adjustable output as low

as 0.8V. Driving an external high side PFET and low side

NFET it can provide efficiencies as high as 95%.

n No compensation required

n Constant frequency across input range

n Low quiescent current of 400µA

n Internal soft-start

n Short circuit protection

n Tiny SOT-23 package

Applications

Three versions of the LM1770 are available depending on

the switching frequency desired for the application. Nominal

switching frequencies are in the range of 100kHz to

1000kHz.

n Simple To Design, High Efficiency Step Down Switching

Regulators

n Set-Top Boxes

n Cable Modems

n Printers

n Digital Video Recorders

n Servers

Typical Application Circuit

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Connection Diagram

Ordering Information

Top View

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SOT23-5 Package

NS Package Number MA05B

Order Number

LM1770SMF

LM1770SMFX

LM1770TMF

LM1770TMFX

LM1770UMF

LM1770UMFX

Package Type

NSC Package Drawing

MF05A

On-time

500ns

Supplied As

SOT23-5

1000 units Tape and Reel

3000 units Tape and Reel

1000 units Tape and Reel

3000 units Tape and Reel

1000 units Tape and Reel

3000 units Tape and Reel

MF05A

500ns

MF05A

1000ns

2000ns

MF05A

Pin Descriptions

Pin #

Name

Function

1

2

3

4

5

V_IN

GND

LG

Input supply

Ground

NFET Gate Drive

PFET Gate Drive

Feedback Pin

HG

FB

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Junction Temperature

150˚C

260˚C

2.5kV

Lead Temperature (soldering, 10sec)

ESD Rating

V_IN

-0.3V to 6V

Operating Ratings

Storage Temperature Range

−65˚C to 150˚C

V_INto GND

2.8V to 5.5V

−40˚C to

+125˚C

Junction Temperature Range (T_J)

Electrical Characteristics Specifications with standard typeface are for T_J= 25˚C, and those in bold face

type apply over the full Junction Temperature Range (−40˚C to +125˚C). Minimum and Maximum limits are guaranteed

through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25˚C and are

provided for reference purposes only. Unless otherwise specified V_IN= 3.3V.

Symbol

Parameter

Feedback pin voltage

Conditions

V_IN= 3.3V

Min

Typ

0.80

0.79

-5

Max

0.818

0.808

Unit

VFB

0.782

0.772

V

V_IN= 5.0V

∆V_FB/ ∆V_IN

Line Regulation

V_IN= 2.8V to 5.5V

V_FB= 0.9V

mV/V

µA

I_Q

Operating Quiescent current

Switch On-Time

400

0.5

1.0

2.0

150

135

120

70

600

0.6

T_ON

LM1770S - (500ns)

LM1770T - (1000ns)

LM1770U - (2000ns)

LM1770S - (500ns)

LM1770T - (1000ns)

LM1770U - (2000ns)

0.4

0.8

1.6

µs

1.2

2.4

T_{OFF_MIN}

Minimum Off-Time

250

225

220

ns

T_D

I_FB

Gate Drive Dead-Time

ns

nA

V

Feedback pin bias current

Under-voltage lock out

V_FB= 0.9V

50

V_UVLO

V_{UVLO_HYS}

V_{SC_TH}

V_INRising Edge

2.6

30

2.8

Under-voltage lock out hysteresis

Feedback pin Short Circuit Latch

Threshold

mV

V

0.5

0.55

0.65

R_{DS(ON) 1}

R_{DS(ON) 2}

R_{DS(ON) 3}

R_{DS(ON) 4}

HG FET driver pull-up On resistance

I_HG= 20 mA

5

9

5

Ω

HG FET driver pull-down On resistance I_HG= 20 mA

LG FET driver pull-up On resistance I_LG= 20 mA

LG FET driver pull-down On resistance I_LG= 20 mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for which the device is

intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics.

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Typical Performance Characteristics

T_ONvs Temperature (LM1770S)

Quiescent Current vs Temperature

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T_OFFvs Temperature

Feedback Voltage vs Temperature

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Deadtime vs Temperature

Short Circuit Threshold vs Temperature

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Typical Performance Characteristics (Continued)

UVLO Threshold vs Temperature

T_ONvs V_IN(LM1770S)

T_ONvs V_IN(LM1770T)

T_ONvs V_IN(LM1770U)

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T_ONvs Temperature (LM1770T)

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T_ONvs Temperature (LM1770U)

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Typical Performance Characteristics (Continued)

Efficiency vs I_OUT

(V_IN= 5V, V_OUT= 3.3V)

(V_IN= 5V, V_OUT= 2.5V)

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Efficiency vs I_OUT

(V_IN= 5V, V_OUT= 1V)

(V_IN= 3.3V, V_OUT= 0.8V)

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Block Diagram

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Application Information

THEORY OF APPLICATION

The LM1770 synchronous buck switcher has a control

scheme that is referred to as constant on-time control. This

topology relies on a fixed switch on-time to regulate the

output voltage. This on-time is internally set by EEPROM

and is available with three different set-points to allow for

different frequency options. The LM1770 automatically ad-

justs the on-time during operation inversely with the input

voltage (V_IN) to maintain a constant frequency. Therefore the

switching frequency during continuous conduction mode is

independent of the inductor and capacitor size unlike hyster-

etic switchers.

where,

α = V_INx T_ON

To maintain a set frequency in an application, α is always

held constant by varying T_ONinversely with V_IN. The three

versions of the LM1770 are identified by the on times at a

V_INof 3.3V for consistency. For clarification see the table

below:

@

Product ID

LM1770S

LM1770T

LM1770U

T_ON3.3V

α (V µs)

1.65

3.3

0.5µs

1.0µs

2.0µs

At the beginning of the cycle the LM1770 turns on the high

side PFET for a fixed duration. This on-time is predetermined

(internally set by EEPROM and adjusted by V_IN) and the

switch will not turn off until the timer has completed its

period. The PFET will then turn off for a minimum pre-

determined time period. This minimum T_OFFof 150ns is

internally set and cannot be adjusted. This is to prevent false

triggering from occurring on the comparator due to noise

from the SW node transition. After the minimum T_OFFperiod

has expired, the PFET will remain off until the comparator

trip-point has been reached. Upon passing this trip-point (set

at 0.8V at the feedback pin), the PFET will turn back on and

the process will repeat, thus regulating the output.

6.6

The variation of T_ONversus V_INcan also be expressed

graphically. These graphs can be found in the typical curves

section of the datasheet.

With α being a constant regardless of the version of the

LM1770 used, equation [6] shows that the only dependent

variable remaining is V_OUT. Since V_OUTwill be a constant in

any application, the frequency will also remain constant. The

switching frequency at which the application runs depends

upon the V_OUTdesired and the LM1770 version chosen. For

any V_OUT, three frequency options (LM1770 versions) can

be selected. This can be seen in the table below. The rec-

ommended frequency range of operation is 100kHz to

1000kHz.

The NFET control is complementary to the PFET control with

the exception of a short dead-time to prevent shoot through

from occurring.

DEVICE OPERATION

Timing Opinion

Timing Options

VOUT

0.8

1

500ns

485

1000ns

242

2000ns

121

Three versions of the LM1770 are available each with a

predetermined T_ONset internally by EEPROM. This T_ON

setting will determine the switching frequency for the appli-

cation. Derivation and calculation of the switching frequen-

cy’s dependence on V_INand T_ONcan be seen in the follow-

ing section.

606

303

152

1.2

1.5

1.8

2.5

3.3

727

364

182

909

455

227

1091

1515

2000

545

273

In a PWM buck switcher the following equations can be

manipulated to obtain the switching frequency. The first

equation shows the standard duty-cycle equation given by

the volts-seconds balance on the inductor with the following

equations defining standard relationships:

758

379

1000

500

Switching Frequency (kHz) of LM1770 based on output voltage and timing

option.

SHORT-CIRCUIT PROTECTION

The LM1770 has an internal short circuit comparator that

constantly monitors the feedback node (except during soft-

start). If the feedback voltage drops below 0.55V (equivalent

to the output voltage dropping below 68% of nominal), the

comparator will trip causing the part to latch off. The LM1770

will not resume switching until the input voltage is taken

below the UVLO threshold and then brought back into its

normal operating range. The purpose of this function is to

prevent a severe short circuit from causing damage to the

application. Due to the fast transient response of the

LM1770 a severe short on the output causing the feedback

to drop would only occur if the load applied had an effective

T_ON= D x T_P

Using this equations and solving for duty-cycle:

D = f_SWx T_ON

Frequency can now be expressed as:

resistance that approaches the PMOS R_DS(ON)

.

SOFT-START

To limit in-rush current and allow for a controlled startup the

LM1770 incorporates an internal soft-start scheme. Every

time the input voltage rises through the UVLO threshold the

LM1770 goes through an adaptive soft-start that limits the

Or simply written as:

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equation can be used to determine the slight load depen-

dency on switch frequency if needed. Otherwise the simpli-

fied equation works well for component calculation.

Application Information (Continued)

on-time and expands the minimum off-time. In addition the

part will only activate the PMOS allowing a discontinuous

mode of operation enabling a pre-biased startup. The time

spent in soft-start will depend on the load applied to the

output, but is usually close to a set time that is dependent on

the timing option. The approximate soft-start time can be

seen below for each timing option.

FREQUENCY SELECTION

Product ID

LM1770S

LM1770T

LM1770U

Timing

0.5µs

1.0µs

2.0µs

T_SS

1ms

The LM1770 is available with three preset timing options that

select the on-time and hence determine the switching fre-

quency of the application. Increasing the switching fre-

quency has the effect of reducing the inductor size needed

for the application while requiring a slight trade-off in effi-

ciency. The table below shows the same frequency table as

shown earlier, with the exception that the recommended

timing option for each V_OUTis highlighted. It is not recom-

mended to use a high switching frequency with V_OUTequal

to or greater than 2.5V due to the maximum duty-cycle

limitations of the device coupled with the internal startup.

1.2ms

1.8ms

It should be noted that as soon as soft-start terminates the

short-circuit protection is enabled. This means that if the

output voltage does not reach at least 68% of its final value

the part will latch off. Therefore, if the input supply is ex-

tremely slow rising such that at the end of soft-start the input

voltage is still near the UVLO threshold, a timing option

should be chosen to ensure that maximum duty-cycle per-

mits the output to meet the minimum condition. As a general

recommendation it is advisable to use the 2000ns option

(LM1770U) in conditions where the output voltage is 2.5V or

greater to avoid false latch offs when there is concern re-

garding the input supply slew rate.

Timing Options

V_OUT

0.8

1

500ns

485

606

727

909

-

1000ns

242

303

364

455

545

-

2000ns

-

1.2

1.5

1.8

2.5

3.3

-

227

273

379

500

JITTER

The LM1770 utilizes a constant on-time control scheme that

relies on the output voltage ripple to provide a consistent

switching frequency. Under certain conditions, excessive

noise can couple onto the feedback pin causing the switch

node to appear to have a slight amount of jitter. This is not

indicative of an unstable design. The output voltage will still

regulate to the exact same value. Careful component selec-

tion and layout should minimize any external influence.

-

Recommended switching frequency (kHz) based on output voltage and

timing option.

INDUCTOR SELECTION

The inductor selection is an iterative process likely requiring

several passes before settling on a final value. The reason

for this is because it influences the amount of ripple seen at

the output, a critical component to ensure general stability of

an adaptive on-time circuit. For the first pass at inductor

selection the value can be obtained by targeting a maximum

peak-to-peak ripple current equal to 30% of the maximum

load current. The inductor current ripple (∆I_L) can be calcu-

lated by:

In addition to any external noise that can add to the jitter

seen on the switch node, the LM1770 will always have a

slight amount of switch jitter. This is because the LM1770

makes a small alteration in the reference voltage every 128

cycles to improve its accuracy and long term performance.

This has the effect of causing a change in the switching

frequency at that instant. When viewed on an oscilloscope

this can be seen as a jitter in the switch node. The change in

feedback voltage or output voltage, however, is almost indis-

tinguishable.

Design Guide

The following section walks the designer through the steps

necessary to select the external components to build a fully

functional power supply. As with any DC-DC converter nu-

merous trade-offs are possible to optimize the design for

efficiency, size or performance. These will be taken into

account and highlighted throughout this discussion.

Therefore, L can be initially set to the following by applying

the 30% rule:

The first equation to calculate for any buck converter is

duty-cycle. Ignoring conduction losses associated with the

FETs and parasitic resistances it can be approximated by:

The other features of the inductor that can be selected

besides inductance value are saturation current and core

material. Because the LM1770 does not have a current limit,

it is recommended to have a saturation current higher than

the maximum output current to handle any ripple or momen-

tary over-current events. The core material also influences

the saturation characteristics as ferrite materials have a hard

saturation curve and care should be taken such that they

never saturate during normal use. A shielded inductor or low

A more accurate calculation for duty-cycle can be used that

takes into account the voltage drops across the FETs. This

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If the output voltage is fairly high, causing significant attenu-

ation through the feedback resistors, a feed-forward capaci-

tor can be used. This is actually recommended for most

circuits as it improves performance. See the feed-forward

capacitor section for more details.

Design Guide (Continued)

profile unshielded inductor is recommended to reduce EMI.

This also helps prevent any spurious noise from picking up

on the feedback node resulting in unexpected tripping of the

feedback comparator.

The second criteria is to ensure that there is sufficient ripple

at the output that is in-phase with the switch. The problem

exists that there is actually ripple caused by the capacitor

charging and discharging, not only the ESR ripple. Since

these are effectively out of phase, problems can exist. To

avoid this issue it is recommended that the ratio of the two

ripples (β) is always greater than 5. To calculate the mini-

mum ESR value needed, the following equation can be

used.

OUTPUT CAPACITOR

One of the most important components to select with the

LM1770 is the output capacitor. This is because its size and

ESR have a direct effect on the stability of the loop. A

constant on-time control scheme works by sensing the out-

put voltage ripple and switching the FETs appropriately. The

output voltage ripple on a buck converter can be approxi-

mated by stating that the AC inductor ripple flows entirely

into the output capacitor and is created by the ESR of the

capacitor. This can be expressed in the following equation:

∆V_OUT= ∆I_Lx R_ESR

To ensure stability, two constraints need to be met. The first

is that there is sufficient ESR to create enough voltage ripple

at the feedback pin. The recommendation is to have at least

10mV of ripple seen at the feedback pin. This can be calcu-

lated by multiplying the output voltage ripple by the gain

seen through the feedback resistors. This gain, H, can be

calculated below:

In general the best capacitors to use are chemistries that

have a known and consistent ESR across the entire operat-

ing temperature range. Tantalum capacitors or similar chem-

istries such as Niobium Oxide perform well along with certain

families of Aluminum Electrolytics. Small value POSCAPs

and SP CAPs also work as they have sufficient ESR. When

used in conjunction with a low value inductor it is possible to

have an extremely stable design. The only capacitors that

require modification to the circuit are ceramic capacitors.

Ceramic capacitors cause problems meeting both criteria

because they have low ESR and low capacitance. There-

fore, if they are to be used, an external ESR resistor (RSNS)

should be added. This can be seen below in the following

circuit.

20166218

This circuit uses an additional resistor in series with the

inductor to add ripple at the output. It is placed in this location

and used in combination with the feed-forward capacitor

(C_FF) to provide ripple to the feedback pin, without adding

ripple or a DC offset to the output. The benefit of using a

ceramic capacitor is still obtained with this technique. Be-

cause the addition of the resistor results in power loss, this

circuit implementation is only recommended for low currents

(2A and below). The power loss and rating of the resistor

should be taken into account when selecting this compo-

nent.

This circuit implementation utilizing the feed-forward capaci-

tor begins to experience limitations when the output voltage

is small. Previously the circuit relied on the C_FFfor all the

ripple at the feedback node by assuming that the resistor

divider was negligible. As V_OUTdecreases this can not be

assumed. The resistor divider contributes a larger amount of

ripple which is problematic as it is also out of phase. There-

fore the resistor location should be changed to be in series

with the output capacitor. This can be viewed as adding an

effective ESR to the output capacitor.

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Design Guide (Continued)

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FEED-FORWARD CAPACITOR

The feed-forward capacitor is used across the top feedback

resistor to provide a lower impedance path for the high

frequency ripple without degrading the DC accuracy. Typi-

cally the value for this capacitor should be small enough to

prevent load transient errors because of the discharging

time, but large enough to prevent attenuation of the ripple

voltage. In general a small ceramic capacitor in the range of

1nF to 10nF is sufficient.

MOSFET Selection

The two FETs used in the LM1770 requires attention to

selection of parameters to ensure optimal performance of

the power supply. The high side FET should be a PFET and

the low side an NFET. These can be integrated in one

package or as two separate packages. The criteria that

matter in selection are listed below:

If C_FFis used then it can be assumed that the ripple voltage

seen at the feedback pin is the same as the ripple voltage at

the output. The attenuation factor H no longer needs to be

used. However, in these conditions, it is recommended to

have a minimum of 20mV ripple at the feedback pin. The use

of a C_FFcapacitor is recommended as it improves the regu-

lation and stability of the design. However, its benefit is

diminished as V_OUTstarts approaching V_REF, therefore it is

not needed in this situation.

VDS VOLTAGE RATING

The first selection criteria is to select FETs that have suffi-

cient V_DSvoltage ratings to handle the maximum voltage

seen at the input plus any transient spikes that can occur

from parasitic ringing. In general most FETs available for this

application will have ratings from 8V to 20V. If a larger

voltage rating is used then the performance will most likely

be degraded because of higher gate capacitance.

INPUT CAPACITOR

The dominating factor that usually sets an input capacitors’

size is the current handling ability. This is usually determined

by the package size and ESR of the capacitor. If these two

criteria are met then there usually should be enough capaci-

tance to prevent impedance interactions with the source. In

general it is recommended to use a ceramic capacitor for the

input as they provide a low impedance and small footprint.

One important note is to use a good dielectric for the ceramic

capacitor such as X5R or X7R. These provide better over

temperature performance and also minimize the DC voltage

derating that occurs on Y5V capacitors. To calculate the

input capacitor RMS current, the equation below can be

used:

RDSON

The R_DS(ON)specification is important as it determines sev-

eral attributes of the FET and the overall power supply. The

first is that it sets the maximum current of the FET for a given

package. A lower R_DS(ON)will permit a higher allowable

current and reduce conduction losses, however, it will in-

crease the gate capacitance and the switching losses.

GATE DRIVE

The next step is to ensure that the FETs are capable of

switching at the low Vin supplies used by the LM1770. The

FET should have the Rdson specified at either 1.8V or 2.5V

to ensure that it can switch effectively as soon as the

LM1770 starts up.

GATE CHARGE

Because the LM1770 utilizes a fixed dead-time scheme to

prevent cross conduction, the FET transitions must occur in

this time. The rise and fall time of the FETs gate can be

influenced by several factors including the gate capacitance.

which can be approximated by,

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If the above selection criteria have been met it is useful to

generate a figure of merit to allow comparison between the

FETs. One such method is to multiply the R_DS(ON)of the FET

by the total gate charge. This allows an easy comparison of

the different FETs available. Once again, the lower the prod-

uct, the better.

MOSFET Selection (Continued)

Therefore the total gate charge of both FETs should be

limited to less than 20nC at 4.5V V_GS. The lower the number

the faster the FETs should switch and the better the effi-

ciency.

RISE / FALL TIMES

FEEDBACK RESISTORS

A better indication of the actual switching times of the FETs

can be found in their electrical characteristics table. The rise

and fall time should be specified and selected to be at a

minimum. This helps improve efficiency and ensuring that

shoot through does not occur.

The feedback resistors are used to scale the output voltage

to the internal reference value such that the loop can be

regulated. The feedback resistors should not be made arbi-

trarily large as this creates a high impedance node at the

feedback pin that is more susceptible to noise. A combined

value of 50kΩ for the two resistors is adequate. To calculate

the resistor values use the equation below. Typically the low

side resistor is initially set to a pre-determined value such as

10 kΩ.

GATE CHARGE RATIO

Another consideration in selecting the FETs is to pay atten-

tion to the Qgd / Qgs ratio. The reason for this is that proper

selection can prevent spurious turn on. If we look at the

NFET for example, when the FET is turning off, the gate

signal will pull to ground. Conversely the PFET will be turn-

ing on, causing the SW node to rise towards V_IN. The gate to

drain capacitance of the NFET couples the SW node to the

gate and will cause it to rise. If this voltage is excessive, then

it could weakly turn on the low side FET causing an effi-

ciency loss. However, this coupling is mitigated by having a

large gate to source capacitance of the FET, which helps to

hold the gate voltage down. Ideally, a very low Qgd / Qgs

would be ideal, but in practice it is common to find the

number around 1. As a general rule, the lower the ratio, the

better.

V_FBis the internal reference voltage that can be found in the

electrical characteristics table or approximated by 0.8V.

The output voltage value can be set in a precise manner by

taking into account the fact that the reference voltage is

regulating the bottom of the output ripple as opposed to the

average value. This relationship is shown in the figure below.

20166223

It can be seen that the average output voltage (VOUT_AC-

TUAL) is higher than the output voltage (VOUT_SET) that

was calculated by the earlier equation by exactly half the

output voltage ripple. The output voltage that is targeted for

regulation may then be appended according to the voltage

ripple. This can be seen below:

QUIESCENT CURRENT

The quiescent current consumed by the LM1770 is one of

the major sources of loss within the controller. However, from

a system standpoint this is usually less than 0.5% of the

overall efficiency. Therefore, it could easily be omitted but is

shown for completeness:

1

V_{OUT_ACTUAL}= V_{OUT_SET}+ ⁄ ∆V_OUT= V_{OUT_SET}+ ⁄ ∆I_Lx

2

P_IQ= V_INx I_Q

R_ESR

CONDUCTION LOSS

Efficiency Calculations

There are three losses associated with the external FETs.

From the DC standpoint there is the I-squared R loss,

caused by the on resistance of the FET. This can be mod-

eled for the PMOS by:

One of the most important parameters to calculate during the

design stage is the expected efficiency of the system. This

can help determine optimal FET selection and can be used

to calculate expected temperature rise of the individual com-

ponents. The individual losses of each component are bro-

ken down and the equations are listed below:

2

P_{P_COND}= D x R_{DSON_PMOS}x I_OUT

and the NMOS by:

2

P_{N_COND}= (1 - D) x R_{DSON_NMOS}x I_OUT

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Efficiency Calculations (Continued)

SWITCHING LOSS

Thermals

By breaking down the individual power loss in each compo-

nent it makes it easy to determine the temperature rise of

each component. Generally the expected temperature rise

of the LM1770 is extremely low as it is not in the power path.

Therefore the only two items of concern are the PMOS and

the NMOS. The power loss in the PMOS is the sum of the

conduction loss and transitional loss, while the NMOS only

has conduction loss. It is assumed that any loss associated

with the body diode conduction during the dead-time is

negligible.

The next loss is the switching loss that is caused by the need

to charge and discharge the gate capacitance of the FETs

every cycle. This can be approximated by:

P_{P_SWITCH}= V_INx Q_{g_PMOS}x f_SW

for the PMOS, and the same approach can be adapted for

the NMOS:

P_{N_SWITCH}= V_INx Q_{g_NMOS}x f_SW

TRANSITIONAL LOSS

For completeness of design it is important to watch out for

the temperature rise of the inductor. Assuming the inductor is

kept out of saturation the predominant loss will be the DC

copper resistance. At higher frequencies, depending on the

core material, the core loss could approach or exceed the

DCR losses. Consult with the inductor manufacturer for ap-

propriate temp curves based on current.

The last FET power loss is the transitional loss. This is

caused by switching the PMOS while it is conducting current.

This approach only models the PMOS transition, the NMOS

loss is considered negligible because it has minimal drain to

source voltage when it switches due to the conduction of the

body diode. Therefore the transitional loss of the PMOS can

be modeled by:

Layout

P_{P_TRANSITIONAL}= 0.5 x V_INx I_OUTx f_SWx (t_r+ t_f)

t_rand t_fare the rise and fall times of the FET and can be

found in their corresponding datasheet. Typically these num-

bers are simulated using a 6Ω drive, which corresponds well

to the LM1770. Given this, no adjustment is needed.

The LM1770, like all switching regulators, requires careful

attention to layout to ensure optimal performance. The fol-

lowing steps should be taken to aid in the layout. For more

information refer to Application Note AN-1299.

1. Ensure that the ground connections of the input capaci-

tor, output capacitor and NMOS are as close as pos-

sible. Ideally these should all be grounded together in

close proximity on the component side of the board.

DCR LOSS

The last source of power loss in the system that needs to be

calculated is the loss associated with the inductor resistance

(DCR) which can be calculated by

2. Keep the switch node small to minimize EMI without

degrading thermal cooling of the FETs.

2

P_DCR= R_DCRx I_OUT

3. Locate the feedback resistors close to the IC and keep

the feedback trace as short as possible. Do not run any

feedback traces near the switch node.

EFFICIENCY

The efficiency, η, can then be calculated by summing all the

power losses and then using the equation below:

4. Keep the gate traces short and keep them away from the

switch node as much as possible.

5. If a small bypass capacitor is used on V_IN(0.1µF) place

it as close to the pin, with the ground connection as

close to the chip ground as possible.

13

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Physical Dimensions inches (millimeters) unless otherwise noted

SOT23-5 Package

NS Package Number MF05A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

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expected to cause the failure of the life support device or

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型号：	LM1770UMFX
厂家：	National Semiconductor
描述：	SOT-23 Synchronous Buck Controller SOT- 23同步降压控制器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总14页 (文件大小：685K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM1770UMFX [NSC]

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