LM1771_技术文档

June 2006

LM1771

Low-Voltage Synchronous Buck Controller with

Precision Enable and No External Compensation

General Description

Features

n Input voltage range of 2.8V to 5.5V

n 0.8V reference voltage

The LM1771 is an efficient synchronous buck switching con-

troller with a precision enable requiring no external compen-

sation. The constant on-time control scheme provides a

simple design free of compensation components, allowing

minimal component count and board space. The precision

enable pin allows flexibility in sequencing multiple rails and

setting UVLO. The LM1771 also incorporates a unique input

feed-forward to maintain a constant frequency independent

of the input voltage. The LM1771 is optimized for a low

voltage input range of 2.8V to 5.5V and can provide an

adjustable output as low as 0.8V. Driving an external high

side PFET and low side NFET it can provide efficiencies as

high as 95%.

n Precision enable

n No compensation required

n Constant frequency across input range

n Low quiescent current of 400 µA

n Internal soft-start

n Short circuit protection

n Tiny LLP-6 package and MSOP-8 package

Applications

n Simple To Design, High Efficiency Step Down Switching

Three versions of the LM1771 are available depending on

the switching frequency desired for the application. Nominal

switching frequencies are in the range of 100kHz to

1000kHz.

Regulators

n FPGAs, DSPs, and ASIC Power Supplies

n Set-Top Boxes

n Cable Modems

n Printers

n Digital Video Recorders

n Servers

n Graphic Cards

Typical Application Circuit

20189001

DS201890

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Connection Diagrams

Top View

20189040

MSOP-8

NS Package Number MUA08A

20189002

6-Lead LLP (3mm x 3mm)

NS Package Number SDE06A

Ordering Information

NSC Package

Drawing

Order Number

LM1771SSD

LM1771SSDX

LM1771TSD

LM1771TSDX

LM1771USD

LM1771USDX

Timing Option

Package Type

Top Mark

1771S

1771T

Supplied As

1000 units Tape and Reel

4500 units Tape and Reel

1000 units Tape and Reel

4500 units Tape and Reel

1000 units Tape and Reel

4500 units Tape and Reel

500ns

1000ns

2000ns

6-Lead LLP

SDE06A

1771T

1771U

Order Number

LM1771SMM

LM1771SMMX

LM1771TMM

LM1771TMMX

LM1771UMM

LM1771UMMX

Timing Option

Package Type

NSC Package Drawing

Supplied As

500ns

1000ns

2000ns

MSOP-8

MUA08A

Available Soon

Pin Descriptions

Pin #

Name

FB

Function

1

2

Feedback Pin

Ground

GND

HG

LG

3

PFET Gate Drive

NFET Gate Drive

Input supply

4

5

VIN

EN

6

Enable Pin

DAP

-

Die Attach Pad is internally connected to GND, but it cannot be

used as the primary GND connection

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Junction Temperature

150˚C

260˚C

2kV

Lead Temperature (soldering, 10sec)

ESD Rating

V_IN

-0.3V to 6V

-0.3V to V_IN

Operating Ratings

V_INto GND

EN, FB, HG, LG

Storage Temperature Range

2.8V to 5.5V

−65˚C to 150˚C

Junction Temperature Range (T_J)

−40˚C to +125˚C

Electrical Characteristics Specifications with standard typeface are for T_J= 25˚C, and those in bold face

type apply over the full Junction Temperature Range (−40˚C to +125˚C). Minimum and Maximum limits are guaranteed

through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25˚C and are

provided for reference purposes only. Unless otherwise specified V_IN= 3.3V.

Symbol

V_FB

Parameter

Feedback pin voltage

Conditions

Min

Typ

0.8

400

0.5

1.0

2.0

150

135

120

70

Max

0.818

700

0.6

Unit

V

0.782

I_Q

Quiescent current

V_FB= 0.9V

µA

LM1771S - (500ns)

LM1771T - (1000ns)

LM1771U - (2000ns)

LM1771S - (500ns)

LM1771T - (1000ns)

LM1771U - (2000ns)

0.4

0.8

1.6

T_ON

Switch On-Time

1.2

µs

ns

2.4

250

225

220

T_{OFF_MIN}

Minimum Off-Time

T_D

V_{IH_EN}

V_{EN_HYS}

I_FB

Gate Drive Dead-Time

ns

V

EN Pin Rising Threshold

EN Pin Hysteresis

1.15

0.42

1.2

50

1.25

200

mV

nA

V

Feedback pin bias current

Under-voltage lock out

V_FB= 0.9V

50

V_UVLO

V_INRising Edge

2.65

50

2.8

V_{UVLO_HYS}

V_{SC_TH}

Under-voltage lock out hysteresis

Feedback pin Short Circuit Latch

Threshold

mV

V

0.55

0.65

R_{DS(ON) 1}

R_{DS(ON) 2}

R_{DS(ON) 3}

R_{DS(ON) 4}

HG FET driver pull-up On resistance

I_HG= 20 mA

4

6

4

6

Ω

HG FET driver pull-down On resistance I_HG= 20 mA

LG FET driver pull-up On resistance I_LG= 20 mA

LG FET driver pull-down On resistance I_LG= 20 mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for which the device is

intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics.

3

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Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical ap-

plication circuit shown in Application Information section of this datasheet. T_J= 25˚C, unless otherwise specified.

T_ONvs V_IN(LM1771S)

T_ONvs V_IN(LM1771T)

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20189011

20189010

20189009

20189008

20189012

T_ONvs V_IN(LM1771U)

T_ONvs Temperature (LM1771S)

T_ONvs Temperature (LM1771T)

T_ONvs Temperature (LM1771U)

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Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical

application circuit shown in Application Information section of this datasheet. T_J= 25˚C, unless otherwise

specified. (Continued)

T_OFFvs Temperature (LM1771S)

T_OFFvs Temperature (LM1771U)

V_ENThreshold vs Temperature

T_OFFvs Temperature (LM1771T)

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20189042

20189014

20189041

Feedback Voltage vs Temperature

20189017

Short Circuit Threshold vs Temperature

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Typical Performance Characteristics All curves taken at VIN = 3.3V with configuration in typical

application circuit shown in Application Information section of this datasheet. T_J= 25˚C, unless otherwise

specified. (Continued)

Quiescent Current vs Temperature

Deadtime vs Temperature

20189016

20189015

Efficiency vs I_OUT(LM1771T)

Efficiency vs I_OUT(LM1771U)

(V_IN= 5V, V_OUT= 1.8V, F_SW= 545kHz)

(V_IN= 5V, V_OUT= 2.5V, F_SW= 379kHz)

20189004

20189003

Efficiency vs I_OUT(LM1771U)

Efficiency vs I_OUT(LM1771S)

(V_IN= 5V, V_OUT= 3.3V, F_SW= 500kHz)

(V_IN= 5V, V_OUT= 1.2V, F_SW= 727kHz)

20189005

20189006

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Block Diagram

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Application Information

THEORY OF APPLICATION

The LM1771 synchronous buck controller has a control

scheme that is referred to as adaptive on-time control. This

topology relies on a fixed switch on-time to regulate the

output voltage. This on-time is internally set by EEPROM

and is available with three different set-points to allow for

different frequency options. The LM1771 automatically ad-

justs the on-time during operation inversely with the input

voltage (VIN) to maintain a constant frequency. Therefore

the switching frequency during continuous conduction mode

is independent of the inductor and capacitor size unlike

hysteretic switchers.

where,

α = V_INx T_ON

To maintain a set frequency in an application, α is always

held constant by varying T_ONinversely with V_IN. The three

versions of the LM1771 are identified by the on times at a

V_INof 3.3V for consistency. For clarification see the table

below:

@

Product ID

LM1771S

LM1771T

LM1771U

T_ON3.3V

α (V µs)

1.65

3.3

0.5µs

1.0µs

2.0µs

At the beginning of the cycle the LM1771 turns on the high

side PFET for a fixed duration. This on-time is predetermined

(internally set by EEPROM and adjusted by V_IN) and the

switch will not turn off until the timer has completed its

period. The PFET will then turn off for a minimum pre-

determined time period. This minimum T_OFFof 150ns is

internally set and cannot be adjusted. This is to prevent false

triggering from occurring on the comparator due to noise

from the SW node transition. After the minimum T_OFFperiod

has expired, the PFET will remain off until the comparator

trip-point has been reached. Upon passing this trip-point (set

at 0.8V at the feedback pin), the PFET will turn back on and

the process will repeat, thus regulating the output.

6.6

The variation of T_ONversus V_INcan also be expressed

graphically. These graphs can be found in the typical curves

section of the datasheet.

With α being a constant regardless of the version of the

LM1771 used, equation [6] shows that the only dependent

variable remaining is V_OUT. Since V_OUTwill be a constant in

any application, the frequency will also remain constant. The

switching frequency at which the application runs depends

upon the V_OUTdesired and the LM1771 version chosen. For

any V_OUT, three frequency options (LM1771 versions) can

be selected. This can be seen in the table below. The rec-

ommended frequency range of operation is 100kHz to

1000kHz.

The NFET control is complementary to the PFET control with

the exception of a short dead-time to prevent shoot through

from occurring.

DEVICE OPERATION

Timing Opinion

Timing Options

VOUT

0.8

1

500ns

485

1000ns

242

2000ns

121

Three versions of the LM1771 are available each with a

predetermined T_ONset internally by EEPROM. This T_ON

setting will determine the switching frequency for the appli-

cation. Derivation and calculation of the switching frequen-

cy’s dependence on V_INand T_ONcan be seen in the follow-

ing section.

606

303

152

1.2

1.5

1.8

2.5

3.3

727

364

182

909

455

227

1091

1515

2000

545

273

758

379

In a PWM buck switcher the following equations can be

manipulated to obtain the switching frequency. The first

equation shows the standard duty-cycle equation given by

the volts-seconds balance on the inductor with the following

equations defining standard relationships:

1000

500

Switching Frequency (kHz) of LM1771 based on output voltage and timing

option.

SHORT-CIRCUIT PROTECTION

The LM1771 has an internal short circuit comparator that

constantly monitors the feedback node (except during soft-

start). If the feedback voltage drops below 0.55V (equivalent

to the output voltage dropping below 68% of nominal), the

comparator will trip causing the part to latch off. The LM1771

will not resume switching until the input voltage is taken

below the UVLO threshold and then brought back into its

normal operating range, or the part is disabled then re-

enabled through the enable pin. The purpose of this function

is to prevent a severe short circuit from causing damage to

the application. Due to the fast transient response of the

LM1771 a severe short on the output causing the feedback

to drop would only occur if the load applied had an effective

T_ON= D x T_P

Using these equations and solving for duty-cycle:

D = f_SWx T_ON

Frequency can now be expressed as:

resistance that approaches the PMOS R_DS(ON)

.

PRECISION ENABLE

The LM1771 features a precision enable circuit. If the volt-

age on the EN pin is 1.2V or greater, the part is enabled and

switching will occur. If the enable voltage falls below 1.2V,

Or simply written as:

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frequency at that instant. When viewed on an oscilloscope

this can be seen as a jitter in the switch node. The change in

feedback voltage or output voltage, however, is almost indis-

tinguishable.

Application Information (Continued)

the part will be placed into a shutdown state and the drivers

will be tri-stated. This allows the LM1771 to be easily se-

quenced using a resistive divider from the output of another

regulator, or the working input voltage range of the LM1771

to be set using a resistive divider on V_IN. There is no internal

pull-up connected to the EN pin, so an external signal is

required to initiate switching. It should be noted that when

power is first applied to the LM1771, there is a slight delay

before the enable comparator is functional. During this delay,

typically on the order of 400 µs, the part will be disabled

regardless of the voltage on the EN pin. The falling enable

threshold features 50 mV of hysteresis

Design Guide

The following section walks the designer through the steps

necessary to select the external components to build a fully

functional power supply. As with any DC-DC converter nu-

merous trade-offs are possible to optimize the design for

efficiency, size or performance. These will be taken into

account and highlighted throughout this discussion.

The first equation to calculate for any buck converter is

duty-cycle. Ignoring conduction losses associated with the

FETs and parasitic resistances it can be approximated by:

SOFT-START

To limit in-rush current and allow for a controlled startup the

LM1771 incorporates an internal soft-start scheme. Every

time the enable voltage rises rises above 1.2V while V_INis

greater than the UVLO threshold, the LM1771 goes through

an adaptive soft-start that limits the on-time and expands the

minimum off-time. In addition the part will only activate the

PMOS allowing a discontinuous mode of operation enabling

a pre-biased startup. The time spent in soft-start will depend

on the load applied to the output, but is usually close to a set

time that is dependent on the timing option. The approximate

soft-start time can be seen below for each timing option.

A more accurate calculation for duty-cycle can be used that

takes into account the voltage drops across the FETs. This

equation can be used to determine the slight load depen-

dency on switch frequency if needed. Otherwise the simpli-

fied equation works well for component calculation.

Product ID

LM1771S

LM1771T

LM1771U

Timing

0.5 µs

1.0 µs

2.0 µs

T_SS

1 ms

1.2 ms

1.8 ms

FREQUENCY SELECTION

The LM1771 is available with three preset timing options that

select the on-time and hence determine the switching fre-

quency of the application. Increasing the switching fre-

quency has the effect of reducing the inductor size needed

for the application while requiring a slight trade-off in effi-

ciency. The table below shows the same frequency table as

shown earlier, with the exception that the recommended

timing option for each V_OUTis highlighted. It is not recom-

mended to use a high switching frequency with V_OUTequal

to or greater than 2.5V due to the maximum duty-cycle

limitations of the device coupled with the internal startup.

It should be noted that as soon as soft-start terminates the

short-circuit protection is enabled. This means that if the

output voltage does not reach at least 68% of its final value

the part will latch off. Therefore, if the input supply is ex-

tremely slow rising such that at the end of soft-start the input

voltage is still near the UVLO threshold, a timing option

should be chosen to ensure that maximum duty-cycle per-

mits the output to meet the minimum condition. As a general

recommendation it is advisable to use the 2000 ns option

(LM1771U) in conditions where the output voltage is 2.5V or

greater to avoid false latch offs when there is concern re-

garding the input supply slew rate.

Timing Options

V_OUT

0.8

1

500 ns

1000 ns

242

303

364

455

545

-

2000 ns

In some situations, the internal soft-start routine can create a

slight overshoot on the output voltage. If this must be

avoided, the use of a feed-forward capacitor as detailed in

the feed-forward capacitor section of this datasheet is rec-

ommended.

485

606

727

909

-

1.2

1.5

1.8

2.5

3.3

-

227

273

379

500

JITTER

The LM1771 utilizes an adaptive on-time control scheme

that relies on the output voltage ripple to provide a consistent

switching frequency. Under certain conditions, excessive

noise can couple onto the feedback pin causing the switch

node to appear to have a slight amount of jitter. This is not

indicative of an unstable design. The output voltage will still

regulate to the exact same value. Careful component selec-

tion and layout should minimize any external influence.

-

Recommended switching frequency (kHz) based on output voltage and

timing option.

INDUCTOR SELECTION

The inductor selection is an iterative process likely requiring

several passes before settling on a final value. The reason

for this is because it influences the amount of ripple seen at

the output, a critical component to ensure general stability of

an adaptive on-time circuit. For the first pass at inductor

selection the value can be obtained by targeting a maximum

In addition to any external noise that can add to the jitter

seen on the switch node, the LM1771 will always have a

slight amount of switch jitter. This is because the LM1771

makes a small alteration in the reference voltage every 128

cycles to improve its accuracy and long term performance.

This has the effect of causing a change in the switching

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If the output voltage is fairly high, causing significant attenu-

ation through the feedback resistors, a feed-forward capaci-

tor can be used. This is actually recommended for most

circuits as it improves performance. See the feed-forward

capacitor section for more details.

Design Guide (Continued)

peak-to-peak ripple current equal to 30% of the maximum

load current. The inductor current ripple (∆I_L) can be calcu-

lated by:

The second criteria is to ensure that there is sufficient ripple

at the output that is in-phase with the switch. The problem

exists that there is actually ripple caused by the capacitor

charging and discharging, not only the ESR ripple. Since

these are effectively out of phase, problems can exist. To

avoid this issue it is recommended that the ratio of the two

ripples (β) is always greater than 5. To calculate the mini-

mum ESR value needed, the following equation can be

used.

Therefore, L can be initially set to the following by applying

the 30% rule:

The other features of the inductor that can be selected

besides inductance value are saturation current and core

material. Because the LM1771 does not have a current limit,

it is recommended to have a saturation current higher than

the maximum output current to handle any ripple or momen-

tary over-current events. The core material also influences

the saturation characteristics as ferrite materials have a hard

saturation curve and care should be taken such that they

never saturate during normal use. A shielded inductor or low

profile unshielded inductor is recommended to reduce EMI.

This also helps prevent any spurious noise from picking up

on the feedback node resulting in unexpected tripping of the

feedback comparator.

In general the best capacitors to use are chemistries that

have a known and consistent ESR across the entire operat-

ing temperature range. Tantalum capacitors or similar chem-

istries such as Niobium Oxide perform well along with certain

families of Aluminum Electrolytics. Small value POSCAPs

and SP CAPs also work as they have sufficient ESR. When

used in conjunction with a low value inductor it is possible to

have an extremely stable design. The only capacitors that

require modification to the circuit are ceramic capacitors.

Ceramic capacitors cause problems meeting both criteria

because they have low ESR and low capacitance. There-

fore, if they are to be used, an external ESR resistor (R_SNS

should be added. This can be seen below in the following

circuit.

)

OUTPUT CAPACITOR

One of the most important components to select with the

LM1771 is the output capacitor. This is because its size and

ESR have a direct effect on the stability of the loop. A

constant on-time control scheme works by sensing the out-

put voltage ripple and switching the FETs appropriately. The

output voltage ripple on a buck converter can be approxi-

mated by stating that the AC inductor ripple flows entirely

into the output capacitor and is created by the ESR of the

capacitor. This can be expressed in the following equation:

∆V_OUT= ∆I_Lx R_ESR

To ensure stability, two constraints need to be met. The first

is that there is sufficient ESR to create enough voltage ripple

at the feedback pin. The recommendation is to have at least

10mV of ripple seen at the feedback pin. This can be calcu-

lated by multiplying the output voltage ripple by the gain

seen through the feedback resistors. This gain, H, can be

calculated below:

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Design Guide (Continued)

20189029

This circuit uses an additional resistor in series with the

inductor to add ripple at the output. It is placed in this location

and used in combination with the feed-forward capacitor

(C_FF) to provide ripple to the feedback pin, without adding

ripple or a DC offset to the output. The benefit of using a

ceramic capacitor is still obtained with this technique. Be-

cause the addition of the resistor results in power loss, this

circuit implementation is only recommended for low currents

(2A and below). The power loss and rating of the resistor

should be taken into account when selecting this compo-

nent.

This circuit implementation utilizing the feed-forward capaci-

tor begins to experience limitations when the output voltage

is small. Previously the circuit relied on the C_FFfor all the

ripple at the feedback node by assuming that the resistor

divider was negligible. As V_OUTdecreases this can not be

assumed. The resistor divider contributes a larger amount of

ripple which is problematic as it is also out of phase. There-

fore the resistor location should be changed to be in series

with the output capacitor. This can be viewed as adding an

effective ESR to the output capacitor.

20189030

FEED-FORWARD CAPACITOR

time, but large enough to prevent attenuation of the ripple

voltage. In general a small ceramic capacitor in the range of

1nF to 10nF is sufficient.

The feed-forward capacitor is used across the top feedback

resistor to provide a lower impedance path for the high

frequency ripple without degrading the DC accuracy. Typi-

cally the value for this capacitor should be small enough to

prevent load transient errors because of the discharging

If C_FFis used then it can be assumed that the ripple voltage

seen at the feedback pin is the same as the ripple voltage at

the output. The attenuation factor H no longer needs to be

used. However, in these conditions, it is recommended to

have a minimum of 20mV ripple at the feedback pin. The use

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GATE CHARGE

Design Guide (Continued)

Because the LM1771 utilizes a fixed dead-time scheme to

prevent cross conduction, the FET transitions must occur in

this time. The rise and fall time of the FETs gate can be

influenced by several factors including the gate capacitance.

Therefore the total gate charge of both FETs should be

limited to less than 20nC at 4.5V V_GS. The lower the number

the faster the FETs should switch and the better the effi-

ciency.

of a C_FFcapacitor is recommended as it improves the regu-

lation and stability of the design. However, its benefit is

diminished as V_OUTstarts approaching V_REF, therefore it is

not needed in this situation.

INPUT CAPACITOR

The dominating factor that usually sets an input capacitors’

size is the current handling ability. This is usually determined

by the package size and ESR of the capacitor. If these two

criteria are met then there usually should be enough capaci-

tance to prevent impedance interactions with the source. In

general it is recommended to use a ceramic capacitor for the

input as they provide a low impedance and small footprint.

One important note is to use a good dielectric for the ceramic

capacitor such as X5R or X7R. These provide better over

temperature performance and also minimize the DC voltage

derating that occurs on Y5V capacitors. To calculate the

input capacitor RMS current, the equation below can be

used:

RISE / FALL TIMES

A better indication of the actual switching times of the FETs

can be found in their electrical characteristics table. The rise

and fall time should be specified and selected to be at a

minimum. This helps improve efficiency and ensuring that

shoot through does not occur.

GATE CHARGE RATIO

Another consideration in selecting the FETs is to pay atten-

tion to the Qgd / Qgs ratio. The reason for this is that proper

selection can prevent spurious turn on. If we look at the

NFET for example, when the FET is turning off, the gate

signal will pull to ground. Conversely the PFET will be turn-

ing on, causing the SW node to rise towards V_IN. The gate to

drain capacitance of the NFET couples the SW node to the

gate and will cause it to rise. If this voltage is excessive, then

it could weakly turn on the low side FET causing an effi-

ciency loss. However, this coupling is mitigated by having a

large gate to source capacitance of the FET, which helps to

hold the gate voltage down. Ideally, a very low Qgd / Qgs

would be ideal, but in practice it is common to find the

number around 1. As a general rule, the lower the ratio, the

better.

which can be approximated by,

MOSFET Selection

If the above selection criteria have been met it is useful to

generate a figure of merit to allow comparison between the

FETs. One such method is to multiply the R_DS(ON)of the FET

by the total gate charge. This allows an easy comparison of

the different FETs available. Once again, the lower the prod-

uct, the better.

The two FETs used in the LM1771 requires attention to

selection of parameters to ensure optimal performance of

the power supply. The high side FET should be a PFET and

the low side an NFET. These can be integrated in one

package or as two separate packages. The criteria that

matter in selection are listed below:

FEEDBACK RESISTORS

VDS VOLTAGE RATING

The feedback resistors are used to scale the output voltage

to the internal reference value such that the loop can be

regulated. The feedback resistors should not be made arbi-

trarily large as this creates a high impedance node at the

feedback pin that is more susceptible to noise. A combined

value of 50kΩ for the two resistors is adequate. To calculate

the resistor values use the equation below. Typically the low

side resistor is initially set to a pre-determined value such as

10 kΩ.

The first selection criteria is to select FETs that have suffi-

cient V_DSvoltage ratings to handle the maximum voltage

seen at the input plus any transient spikes that can occur

from parasitic ringing. In general most FETs available for this

application will have ratings from 8V to 20V. If a larger

voltage rating is used then the performance will most likely

be degraded because of higher gate capacitance.

RDSON

The R_DS(ON)specification is important as it determines sev-

eral attributes of the FET and the overall power supply. The

first is that it sets the maximum current of the FET for a given

package. A lower R_DS(ON)will permit a higher allowable

current and reduce conduction losses, however, it will in-

crease the gate capacitance and the switching losses.

V_FBis the internal reference voltage that can be found in the

electrical characteristics table or approximated by 0.8V.

The output voltage value can be set in a precise manner by

taking into account the fact that the reference voltage is

regulating the bottom of the output ripple as opposed to the

average value. This relationship is shown in the figure below.

GATE DRIVE

The next step is to ensure that the FETs are capable of

switching at the low Vin supplies used by the LM1771. The

FET should have the Rdson specified at either 1.8V or 2.5V

to ensure that it can switch effectively as soon as the

LM1771 starts up.

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MOSFET Selection (Continued)

20189034

It can be seen that the average output voltage (V_{OUT_AC}

-

TRANSITIONAL LOSS

^TUAL) is higher than the output voltage (V_{OUT_SET}) that was

calculated by the earlier equation by exactly half the output

voltage ripple. The output voltage that is targeted for regu-

lation may then be appended according to the voltage ripple.

This can be seen below:

The last FET power loss is the transitional loss. This is

caused by switching the PMOS while it is conducting current.

This approach only models the PMOS transition, the NMOS

loss is considered negligible because it has minimal drain to

source voltage when it switches due to the conduction of the

body diode. Therefore the transitional loss of the PMOS can

be modeled by:

1

V_{OUT_ACTUAL}= V_{OUT_SET}+ ⁄ ∆V_OUT= V_{OUT_SET}+ ⁄ ∆I_Lx

2

R_ESR

P_{P_TRANSITIONAL}= 0.5 x V_INx I_OUTx f_SWx (t_r+ t_f)

Efficiency Calculations

t_rand t_fare the rise and fall times of the FET and can be

found in their corresponding datasheet. Typically these num-

bers are simulated using a 6Ω drive, which corresponds well

to the LM1771. Given this, no adjustment is needed.

One of the most important parameters to calculate during the

design stage is the expected efficiency of the system. This

can help determine optimal FET selection and can be used

to calculate expected temperature rise of the individual com-

ponents. The individual losses of each component are bro-

ken down and the equations are listed below:

DCR LOSS

The last source of power loss in the system that needs to be

calculated is the loss associated with the inductor resistance

(DCR) which can be calculated by:

QUIESCENT CURRENT

2

The quiescent current consumed by the LM1771 is one of

the major sources of loss within the controller. However, from

a system standpoint this is usually less than 0.5% of the

overall efficiency. Therefore, it could easily be omitted but is

shown for completeness:

P_DCR= R_DCRx I_OUT

EFFICIENCY

The efficiency, η, can then be calculated by summing all the

power losses and then using the equation below:

P_IQ= V_INx I_Q

CONDUCTION LOSS

There are three losses associated with the external FETs.

From the DC standpoint there is the I-squared R loss,

caused by the on resistance of the FET. This can be mod-

eled for the PMOS by:

Thermals

2

By breaking down the individual power loss in each compo-

nent it makes it easy to determine the temperature rise of

each component. Generally the expected temperature rise

of the LM1771 is extremely low as it is not in the power path.

Therefore the only two items of concern are the PMOS and

the NMOS. The power loss in the PMOS is the sum of the

conduction loss and transitional loss, while the NMOS only

has conduction loss. It is assumed that any loss associated

with the body diode conduction during the dead-time is

negligible.

P_{P_COND}= D x R_{DSON_PMOS}x I_OUT

and the NMOS by:

2

P_{N_COND}= (1 - D) x R_{DSON_NMOS}x I_OUT

SWITCHING LOSS

The next loss is the switching loss that is caused by the need

to charge and discharge the gate capacitance of the FETs

every cycle. This can be approximated by:

P_{P_SWITCH}= V_INx Q_{g_PMOS}x f_SW

for the PMOS, and the same approach can be adapted for

the NMOS:

For completeness of design it is important to watch out for

the temperature rise of the inductor. Assuming the inductor is

kept out of saturation the predominant loss will be the DC

copper resistance. At higher frequencies, depending on the

core material, the core loss could approach or exceed the

DCR losses. Consult with the inductor manufacturer for ap-

propriate temp curves based on current.

P_{N_SWITCH}= V_INx Q_{g_NMOS}x f_SW

13

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3. Locate the feedback resistors close to the IC and keep

the feedback trace as short as possible. Do not run any

feedback traces near the switch node.

Layout

The LM1771, like all switching regulators, requires careful

attention to layout to ensure optimal performance. The fol-

lowing steps should be taken to aid in the layout. For more

information refer to Application Note AN-1299.

4. Keep the gate traces short and keep them away from the

switch node as much as possible.

5. If a small bypass capacitor is used on V_IN(0.1µF) place

it as close to the pin, with the ground connection as

close to the chip ground as possible.

1. Ensure that the ground connections of the input capaci-

tor, output capacitor and NMOS are as close as pos-

sible. Ideally these should all be grounded together in

close proximity on the component side of the board.

2. Keep the switch node small to minimize EMI without

degrading thermal cooling of the FETs.

www.national.com

14

Typical Application Circuit

20189043

Example Circuit Schematic

Bill of Materials (5V to 1.8V Conversion, f_SW= 1090kHz, I_OUT= 2A)

Designator

U₁

Description

LM1771, 500ns

Part Number

Quantity

Vendor

National Semiconductor

Siliconix

LM1771S

Si3867DV

Si3460DV

1

Q₁

PMOS

Q₂

NMOS

Siliconix

C_IN

22µF Capacitor, 0805

100µF Capacitor, 6.3V, 100mΩ

12.4kΩ Resistor, 0603

10kΩ Resistor, 0603

1nF Capacitor, 0603

3.3µH Inductor

GRM21BR60J226ME39

TPSY107M006R0100

CRCW06031242F

CRCW06031002F

VJ0603102KXXA

Murata

C_OUT

R_FB1

R_FB2

C_FF

AVX

Vishay

L

MSS7341-332NLB

Coilcraft

Bill of Materials (5V to 3.3V Conversion, f_SW= 500kHz, I_OUT= 5A)

Designator

U₁

Description

LM1771, 200ns

Part Number

Quantity

Vendor

National Semiconductor

Siliconix

LM1771U

1

Q₁

PMOS

Si9433BDY

Q₂

NMOS

Si4894DY

Siliconix

C_IN

100µF Capacitor, 1812

150µF Capacitor, 6.3V, 70mΩ

29.4kΩ Resistor, 0805

10kΩ Resistor, 0805

1nF Capacitor, 0805

2.2µH Inductor

GRM43SR60J107ME20B

NOSD157M006R0070

CRCW08052942F

CRCW08051002F

VJ0805102KXXA

DO3316P-222

Murata

C_OUT

R_FB1

R_FB2

C_FF

AVX

Vishay

L

Coilcraft

15

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release ("Engineering Samples") by National Semiconductor

Corporation, including its wholly-owned subsidiaries ("Na-

tional"), user agrees to accept such Engineering Samples

“AS IS” IN PRE-PRODUCTION FORM WITHOUT WAR-

RANTY OF ANY KIND for the sole purpose of engineering

evaluation and testing.

National reserves the right, at any time and without notice, to

modify the circuitry and/or specifications of such Engineering

Samples prior to National’s full qualification and PRODUC-

TION of such Engineering Samples. National makes no

representation that National will continue production of such

Engineering Samples in the pre-production form subsequent

to full qualification and production release of such Engineer-

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NOT ASSUME OR AUTHORIZE ANY OTHER PERSON TO

ASSUME FOR IT ANY OTHER LIABILITY IN CONNEC-

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16

Physical Dimensions inches (millimeters) unless otherwise noted

LLP-6 Package

NS Package Number SDE06A

MSOP-8 Package

NS Package Number MUA08A

17

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Notes

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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型号：	LM1771
厂家：	National Semiconductor
描述：	Low-Voltage Synchronous Buck Controller with Precision Enable and No External Compensation 低电压同步降压控制器具有精密启用和无需外部补偿控制器
文件：	总18页 (文件大小：964K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM1771 [NSC]

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