DM74LS221 [NSC]
Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs; 双非可重触发单稳态具有清零和互补输出
| 型号： | DM74LS221 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs |
| 文件： | 总6页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1992
DM74LS221 Dual Non-Retriggerable One-Shot
with Clear and Complementary Outputs
Y
Pin-out identical to ’LS123 (Note 1)
General Description
Y
Output pulse width range from 30 ns to 70 seconds
The DM74LS221 is a dual monostable multivibrator with
Schmitt-trigger input. Each device has three inputs permit-
ting the choice of either leading-edge or trailing-edge trig-
gering. Pin (A) is an active-low trigger transition input and
pin (B) is an active-high transition Schmitt-trigger input that
allows jitter free triggering for inputs with transition rates as
slow as 1 volt/second. This provides the input with excellent
noise immunity. Additionally an internal latching circuit at the
Y
Hysteresis provided at (B) input for added noise
immunity
Y
Y
Y
Y
Direct reset terminates output pulse
Triggerable from CLEAR input
DTL, TTL compatible
Input clamp diodes
Note 1: The pin-out is identical to ’LS123 but, functionally it is not; refer to
Ý
Operating Rules 10 in this datasheet.
input stage also provides a high immunity to V noise. The
CC
clear (CLR) input can terminate the output pulse at a prede-
termined time independent of the timing components. This
(CLR) input also serves as a trigger input when it is pulsed
with a low level pulse transition (ß). To obtain the best
and trouble free operation from this device please read op-
erating rules as well as the NSC one-shot application notes
carefully and observe recommendations.
Functional Description
The basic output pulse width is determined by selection of
an external resistor (R ) and capacitor (C ). Once triggered,
X
X
the basic pulse width is independent of further input tran-
sitions and is a function of the timing components, or it may
be reduced or terminated by use of the active low CLEAR
input. Stable output pulse width ranging from 30 ns to 70
seconds is readily obtainable.
Features
Y
A dual, highly stable one-shot
Y
Compensated for V
and temperature variations
CC
Connection Diagram
Function Table
Dual-In-Line Package
Inputs
A
Outputs
CLEAR
B
Q
Q
L
X
X
H
H
X
H
X
X
X
L
L
L
H
H
L
H
L
É
É
É
ß
ß
ß
u
H
H
v
L
*
u
High Logic Level
e
e
e
H
L
Low Logic Level
X
Can Be Either Low or High
e
Positive Going Transition
Negative Going Transition
u
e
v
e
É
A Positive Pulse
A Negative Pulse
e
ß
*This mode of triggering requires first the B input be set from a low to high
level while the CLEAR input is maintained at logic low level. Then with the B
input at logic high level, the CLEAR input whose positive transition from low
to high will trigger an output pulse.
TL/F/6409–1
Order Number DM74LS221M or DM74LS221N
See NS Package Number M16A or N16A
TL/F/6409–2
C
1995 National Semiconductor Corporation
TL/F/6409
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
DM74LS
a
0 C to 70 C
§
§
b
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM74LS221
Units
Symbol
Parameter
Min
Nom
Max
V
V
Supply Voltage
Positive-Going Input Threshold Voltage
4.75
5
5.25
V
V
CC
a
b
a
b
T
T
T
T
1
1
2
2
e
at the A Input (V
Min)
CC
V
V
V
Negative-Going Input Threshold Voltage
e
0.8
0.8
V
V
V
at the A Input (V
Min)
CC
Positive-Going Input Threshold Voltage
e
1
at the B Input (V
Min)
CC
Negative-Going Input Threshold Voltage
e
0.9
at the B Input (V
CC
Min)
b
I
I
High Level Output Current
Low Level Output Current
0.4
mA
mA
OH
OL
8
t
Pulse Width
(Note 1)
Data
40
40
15
W
ns
Clear
t
Clear Release Time (Note 1)
ns
REL
dV
dt
V
s
Rate of Rise or Fall of
1
1
Schmitt Input (B) (Note 1)
dV
dt
V
Rate of Rise or Fall of
Logic Input (A) (Note 1)
ms
R
External Timing Resistor (Note 1)
1.4
0
100
1000
50
kX
mF
EXT
EXT
C
External Timing Capacitance (Note 1)
e
e
DC
Duty Cycle
(Note 1)
R
R
2 kX
T
%
R
(Max)
60
T
EXT
T
A
Free Air Operating Temperature
0
70
C
§
e
e
5V.
Note 1:
T
25 C and V
§
A
CC
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
OH
CC
OH
2.7
3.4
e
e
Max, V
IL
IH
e
e
e
V
OL
Low Level Output
Voltage
V
V
Min, I
Max
Min
CC
OL
0.35
0.5
e
Max, V
V
IL
IH
e
e
e
V
Min, I
4 mA
7V
0.4
0.1
CC
CC
OL
@
Input Current Max
e
Max, V
I
I
I
V
mA
Input Voltage
2
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e
I
I
I
High Level Input Current
V
Max, V
2.7V
A1, A2
B
20
mA
IH
IL
CC
b
b
b
Low Level Input
Current
V
V
Max
0.4
0.8
0.8
CC
e
0.4V
I
mA
Clear
e
(Note 2)
I
I
Short Circuit
V
Max
OS
CC
CC
b
b
100
20
mA
mA
Output Current
e
Supply Current
V
CC
Max
Quiescent
Triggered
4.7
19
11
27
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
CC
A
Switching Characteristics
25 C
e
e
A
at V
5V and T
§
CC
From (Input)
To (Output)
Symbol
Parameter
Conditions
Min
Max
Units
ns
e
e
t
t
t
t
t
t
t
Propagation Delay Time
Low to High Level Output
A1, A2
to Q
C
80 pF
PLH
PLH
PHL
PHL
PLH
PHL
W(out)
EXT
70
55
80
65
65
55
R
2 kX
EXT
e
C
L
15 pF
Propagation Delay Time
Low to High Level Output
B
ns
e
R
L
2 kX
to Q
Propagation Delay Time
High to Low Level Output
A1, A2
to Q
ns
Propagation Delay Time
High to Low Level Output
B
ns
to Q
Propagation Delay Time
Low to High Level Output
Clear to
Q
ns
Propagation Delay Time
High to Low Level Output
Clear
to Q
ns
e
0
Output Pulse
A1, A2
to Q, Q
C
EXT
e
2 kX
Width Using Zero
Timing Capacitance
R
EXT
20
600
6
70
750
7.5
ns
ns
ms
ns
e
R
L
2 kX
e
C
L
15 pF
e
EXT
t
Output Pulse
A1, A2
to Q, Q
C
100 pF
W(out)
e
e
Width Using External
Timing Resistor
R
10 kX
2 kX
EXT
R
L
e
C
L
15 pF
e
C
EXT
1 mF
10 kX
2 kX
e
e
R
EXT
R
L
e
C
L
15 pF
e
C
EXT
80 pF
e
R
2 kX
EXT
70
150
e
R
L
2 kX
e
C
L
15 pF
3
Operating Rules
1. An external resistor (R ) and an external capacitor (C )
k
5. For C
1000 pF see Figure 3 for T vs C family
X
X
W
X
X
curves with R as a parameter:
X
are required for proper operation. The value of C may
X
vary from 0 to approximately 1000 mF. For small time
constants high-grade mica, glass, polypropylene, polycar-
bonate, or polystyrene material capacitor may be used.
For large time constants use tantalum or special alumi-
num capacitors. If timing capacitor has leakages ap-
proaching 100 nA or if stray capacitance from either ter-
minal to ground is greater than 50 pF the timing equations
may not represent the pulse width the device generates.
2. When an electrolytic capacitor is used for C a switching
X
diode is often required for standard TTL one-shots to pre-
vent high inverse leakage current. This switching diode is
not needed for the ’LS221 one-shot and should not be
used.
TL/F/6409–4
Furthermore, if a polarized timing capacitor is used on the
’LS221, the positive side of the capacitor should be con-
FIGURE 3
6. To obtain variable pulse widths by remote trimming, the
following circuit is recommended:
nected to the ‘‘C
’’ pin (Figure 1).
EXT
TL/F/6409–5
Note: ‘‘R
’’ should be as close to the one-shot as possible.
remote
FIGURE 4
TL/F/6409–8
7. Output pulse width versus V and temperatures: Figure
5 depicts the relationship between pulse width variation
CC
FIGURE 1
ll
fined as follows:
3. For C
1000 pF, the output pulse width (T ) is de-
W
X
versus V . Figure 6 depicts pulse width variation versus
CC
temperatures.
e
T
KR C
X X
W
[
]
R is in kX
X
where
[
[
]
C
is in pF
X
]
T
is in ns
W
&
e
0.70
K
Ln2
4. The multiplicative factor K is plotted as a function of C
below for design considerations:
X
TL/F/6409–6
FIGURE 5
TL/F/6409–3
FIGURE 2
TL/F/6409–7
FIGURE 6
4
Operating Rules (Continued)
c
8. Duty cycle is defined as T /T
100 in percentage, if it
10. Although the ’LS221’s pin-out is identical to the ’LS123
it should be remembered that they are not functionally
identical. The ’LS123 is a retriggerable device such that
the output is dependent upon the input transitions when
its output ‘‘Q’’ is at the ‘‘High’’ state. Furthermore, it is
recommended for the ’LS123 to externally ground the
W
goes above 50% the output pulse width will become
shorter. If the duty cycle varies between low and high
values, this causes output pulse width to vary, or jitter (a
function of the R
EXT
only). To reduce jitter , R should
EXT
be as large as possible, for example, with R
EXT
e
100k
jitter is not appreciable until the duty cycle approaches
90%.
C
pin for improved system performance. However,
EXT
this pin on the ’LS221 is not an internal connection to
the device ground. Hence, if substitution of an ’LS221
9. Under any operating condition C and R must be kept
X
X
onto an ’LS123 design layout where the C
EXT
wired to the ground, the device will not function.
pin is
as close to the one-shot device pins as possible to mini-
mize stray capacitance, to reduce noise pick-up, and to
reduce I-R and Ldi/dt voltage developed along their con-
11. V and ground wiring should conform to good high-
CC
frequency standards and practices so that switching
transients on the V and ground return leads do not
necting paths. If the lead length from C to pins (6) and
X
(7) or pins (14) and (15) is greater than 3 cm, for exam-
ple, the output pulse width might be quite different from
values predicted from the appropriate equations. A non-
inductive and low capacitive path is necessary to ensure
CC
cause interaction between one-shots. A 0.01 mF to 0.10
mF bypass capacitor (disk ceramic or monolithic type)
from V
to ground is necessary on each device. Fur-
CC
thermore, the bypass capacitor should be located as
complete discharge of C in each cycle of its operation
X
so that the output pulse width will be accurate.
close to the V -pin as space permits.
CC
For further detailed device characteristics and output performance,
please refer to the NSC one-shot application note AN-372.
Physical Dimensions inches (millimeters)
16-Lead Small Outline Molded Package (M)
Order Number DM74LS221M
NS Package Number M16A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS221N
NS Package Number N16E
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