DM74LS221SJX [FAIRCHILD]
Monostable Multivibrator ; 单稳态多谐振荡器\n
| 型号： | DM74LS221SJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Monostable Multivibrator
|
| 文件： | 总8页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1986
Revised April 2000
DM74LS221 Dual Non-Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
Features
The DM74LS221 is a dual monostable multivibrator with
Schmitt-trigger input. Each device has three inputs permit-
ting the choice of either leading-edge or trailing-edge trig-
gering. Pin (A) is an active-LOW trigger transition input and
pin (B) is an active-HIGH transition Schmitt-trigger input
that allows jitter free triggering for inputs with transition
rates as slow as 1 volt/second. This provides the input with
excellent noise immunity. Additionally an internal latching
circuit at the input stage also provides a high immunity to
■ A dual, highly stable one-shot
■ Compensated for VCC and temperature variations
■ Pin-out identical to DM74LS123 (Note 1)
■ Output pulse width range from 30 ns to 70 seconds
■ Hysteresis provided at (B) input for added noise
immunity
■ Direct reset terminates output pulse
■ Triggerable from CLEAR input
■ DTL, TTL compatible
VCC noise. The clear (CLR) input can terminate the output
pulse at a predetermined time independent of the timing
components. This (CLR) input also serves as a trigger
input when it is pulsed with a low level pulse transition
■ Input clamp diodes
(
). To obtain the best and trouble free operation from
this device please read operating rules as well as the Fair-
child Semiconductor one-shot application notes carefully
and observe recommendations.
Note 1: The pin-out is identical to DM74LS123 but, functionally it is not;
refer to Operating Rules #10 in this datasheet.
Ordering Code:
Order Number Package Number
Package Description
DM74LS221M
DM74LS221SJ
DM74LS221N
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
CLEAR
A
X
H
X
L
B
X
X
L
Q
L
L
L
Q
H
H
H
L
X
X
H
H
↑
↓
H
H
↑ (Note 2)
L
H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH
↑ = Positive Going Transition
↓ = Negative Going Transition
= A Positive Pulse
= A Negative Pulse
Note 2: This mode of triggering requires first the B input be set from a
LOW-to-HIGH level while the CLEAR input is maintained at logic LOW
level. Then with the B input at logic HIGH level, the CLEAR input whose
positive transition from LOW-to-HIGH will trigger an output pulse.
© 2000 Fairchild Semiconductor Corporation
DS006409
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Functional Description
The basic output pulse width is determined by selection of
may be reduced or terminated by use of the active low
CLEAR input. Stable output pulse width ranging from 30 ns
to 70 seconds is readily obtainable.
an external resistor (RX) and capacitor (CX). Once trig-
gered, the basic pulse width is independent of further input
transitions and is a function of the timing components, or it
8. Duty cycle is defined as tW/T × 100 in percentage, if it
Operating Rules
1. An external resistor (RX) and an external capacitor
goes above 50% the output pulse width will become
shorter. If the duty cycle varies between LOW and
HIGH values, this causes output pulse width to vary, or
jitter (a function of the REXT only). To reduce jitter, REXT
(CX) are required for proper operation. The value of CX
may vary from 0 to approximately 1000 µF. For small
time constants high-grade mica, glass, polypropylene,
polycarbonate, or polystyrene material capacitor may
be used. For large time constants use tantalum or spe-
cial aluminum capacitors. If timing capacitor has leak-
ages approaching 100 nA or if stray capacitance from
either terminal to ground is greater than 50 pF the tim-
ing equations may not represent the pulse width the
device generates.
should be as large as possible, for example, with
R
EXT = 100k jitter is not appreciable until the duty cycle
approaches 90%.
9. Under any operating condition CX and RX must be kept
as close to the one-shot device pins as possible to min-
imize stray capacitance, to reduce noise pick-up, and
to reduce I-R and Ldi/dt voltage developed along their
connecting paths. If the lead length from CX to pins (6)
2. When an electrolytic capacitor is used for CX a switch-
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations.
A non-inductive and low capacitive path is necessary to
ensure complete discharge of CX in each cycle of its
ing diode is often required for standard TTL one-shots
to prevent high inverse leakage current. This switching
diode is not needed for the DM74LS221 one-shot and
should not be used.
Furthermore, if a polarized timing capacitor is used on
the DM74LS221, the positive side of the capacitor
should be connected to the “CEXT” pin (Figure 1).
operation so that the output pulse width will be accu-
rate.
10. Although the DM74LS221's pin-out is identical to the
DM74LS123 it should be remembered that they are not
functionally identical. The DM74LS123 is a retrigger-
able device such that the output is dependent upon the
input transitions when its output “Q” is at the “High”
state. Furthermore, it is recommended for the
DM74LS123 to externally ground the CEXT pin for
3. For CX >> 1000 pF, the output pulse width (tW) is
defined as follows:
t
W = KRX CX
where [RX is in kΩ]
[CX is in pF]
improved system performance. However, this pin on
the DM74LS221 is not an internal connection to the
device ground. Hence, if substitution of an DM74LS221
onto an DM74LS123 design layout where the CEXT pin
[tW is in ns]
K ≈ Ln2 = 0.70
4. The multiplicative factor K is plotted as a function of CX
for design considerations: (See Figure 4).
5. For CX < 1000 pF see Figure 3 for tW vs. CX family
curves with RX as a parameter.
is wired to the ground, the device will not function.
11. VCC and ground wiring should conform to good high-
frequency standards and practices so that switching
transients on the VCC and ground return leads do not
6. To obtain variable pulse widths by remote trimming,
the following circuit is recommended: (See Figure 2).
cause interaction between one-shots. A 0.01 µF to 0.10
µF bypass capacitor (disk ceramic or monolithic type)
from VCC to ground is necessary on each device. Fur-
7. Output pulse width versus VCC and temperatures: Fig-
ure 5 depicts the relationship between pulse width vari-
ation versus VCC. Figure 6 depicts pulse width variation
thermore, the bypass capacitor should be located as
close to the VCC-pin as space permits.
versus temperatures.
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2
Operating Rules (Continued)
Note: “Rremote” should be as close to the one-shot as possible.
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
Note: For further detailed device characteristics and output performance, please refer to the Fairchild Semiconductor one-shot application note AN-372.
3
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Absolute Maximum Ratings(Note 3)
Note 3: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
Storage Temperature Range
0°C to +70°C
−65°C to +150°C
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
Nom
Max
Units
Supply Voltage
4.75
5
5.25
V
VT+
Positive-Going Input Threshold Voltage
at the A Input (VCC = Min)
Negative-Going Input Threshold Voltage
at the A Input (VCC = Min)
Positive-Going Input Threshold Voltage
at the B Input (VCC = Min)
Negative-Going Input Threshold Voltage
at the B Input (VCC = Min)
HIGH Level Output Current
LOW Level Output Current
Pulse Width
1
1
2
V
V
V
V
VT−
VT+
VT−
0.8
0.8
1
2
0.9
IOH
IOL
tW
−0.4
mA
mA
8
Data
40
40
15
ns
ns
(Note 4)
Clear
tREL
Clear Release Time (Note 4)
Rate of Rise or Fall of
1
1
Schmitt Input (B) (Note 4)
Rate of Rise or Fall of
Logic Input (A) (Note 4)
REXT
CEXT
DC
External Timing Resistor (Note 4)
External Timing Capacitance (Note 4)
Duty Cycle
1.4
0
100
1000
50
kΩ
µF
R
R
T = 2 kΩ
T = REXT (Max)
%
(Note 4)
60
TA
Free Air Operating Temperature
TA = 25°C and VCC = 5V.
0
70
°C
Note 4:
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4
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 5)
VI
VOH
Input Clamp Voltage
V
V
V
V
V
V
V
V
V
CC = Min, II = −18 mA
CC = Min, IOH = Max
IL = Max, VIH = Min
CC = Min, IOL = Max
IL = Max, VIH = Min
CC = Min, IOL = 4 mA
CC = Max, VI = 7V
−1.5
V
V
HIGH Level
2.7
3.4
Output Voltage
LOW Level
VOL
0.35
0.5
Output Voltage
V
0.4
0.1
II
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level
mA
IIH
IIL
CC = Max, VI = 2.7V
20
µA
CC = Max
A1, A2
−0.4
−0.8
−0.8
Input Current
VI = 0.4V
B
mA
Clear
IOS
Short Circuit
V
CC = Max
(Note 6)
CC = Max
−20
−100
mA
mA
Output Current
Supply Current
ICC
V
Quiescent
Triggered
4.7
19
11
27
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
at VCC = 5V and TA = 25°C
From (Input)
Symbol
tPLH
Parameter
Conditions
Min
Max
70
Units
ns
To (Output)
A1, A2
to Q
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Output Pulse
C
EXT = 80 pF
EXT = 2 kΩ
L = 15 pF
L = 2 kΩ
R
tPLH
tPHL
tPHL
tPLH
tPHL
tW(out)
B
C
55
ns
to Q
R
A1, A2
to Q
80
ns
B
65
ns
to Q
Clear to
Q
65
ns
Clear
to Q
55
ns
A1, A2
to Q, Q
CEXT = 0
Width Using Zero
REXT = 2 kΩ
20
600
6
70
750
7.5
ns
ns
ms
ns
Timing Capacitance
R
L = 2 kΩ
L = 15 pF
EXT = 100 pF
EXT = 10 kΩ
L = 2 kΩ
L = 15 pF
EXT = 1 µF
EXT = 10 kΩ
L = 2 kΩ
L = 15 pF
EXT = 80 pF
EXT = 2 kΩ
L = 2 kΩ
L = 15 pF
C
tW(out)
Output Pulse
A1, A2
to Q, Q
C
Width Using External
Timing Resistor
R
R
C
C
R
R
C
C
R
70
150
R
C
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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