DAC104S085EVAL [NSC]
10-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output; 10位微功耗四数位类比转换器具有轨到轨输出
| 型号： | DAC104S085EVAL |
| 厂家： | 
National Semiconductor |
| 描述： | 10-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output |
| 文件： | 总20页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2007
DAC104S085
10-Bit Micro Power QUAD Digital-to-Analog Converter with
Rail-to-Rail Output
General Description
Features
The DAC104S085 is a full-featured, general purpose QUAD
10-bit voltage-output digital-to-analog converter (DAC) that
can operate from a single +2.7V to 5.5V supply and consumes
1.1 mW at 3V and 2.5 mW at 5V. The DAC104S085 is pack-
aged in 10-lead LLP and MSOP packages. The 10-lead LLP
package makes the DAC104S085 the smallest QUAD DAC
in its class. The on-chip output amplifier allows rail-to-rail out-
put swing and the three wire serial interface operates at clock
rates up to 40 MHz over the entire supply voltage range.
Competitive devices are limited to 25 MHz clock rates at sup-
ply voltages in the 2.7V to 3.6V range. The serial interface is
compatible with standard SPI™, QSPI, MICROWIRE and
DSP interfaces.
Guaranteed Monotonicity
■
■
■
■
■
■
■
■
Low Power Operation
Rail-to-Rail Voltage Output
Power-on Reset to 0V
Simultaneous Output Updating
Wide power supply range (+2.7V to +5.5V)
Industry's Smallest Package
Power Down Modes
Key Specifications
Resolution
INL
DNL
Settling Time
Zero Code Error
Full-Scale Error
Supply Power
10 bits
±2 LSB (max)
+0.35 / −0.25 LSB (max)
6 µs (max)
■
The reference for the DAC104S085 serves all four channels
and can vary in voltage between 1V and VA, providing the
widest possible output dynamic range. The DAC104S085 has
a 16-bit input shift register that controls the outputs to be up-
dated, the mode of operation, the powerdown condition, and
the binary input data. All four outputs can be updated simul-
taneously or individually depending on the setting of the two
mode of operation bits.
■
■
■
■
■
■
■
+15 mV (max)
−0.75 %FS (max)
Normal
Power Down
1.1 mW (3V) / 2.5 mW (5V) typ
0.3 µW (3V) / 0.8 µW (5V) typ
—
—
A power-on reset circuit ensures that the DAC output powers
up to zero volts and remains there until there is a valid write
to the device. A power-down feature reduces power con-
sumption to less than a microWatt with three different termi-
nation options.
Applications
Battery-Powered Instruments
■
■
■
■
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Programmable Attenuators
The low power consumption and small packages of the
DAC104S085 make it an excellent choice for use in battery
operated equipment.
The DAC104S085 is one of a family of pin compatible DACs,
including the 8-bit DAC084S085 and the 12-bit DAC124S085.
The DAC104S085 operates over the extended industrial tem-
perature range of −40°C to +105°C.
Pin Configuration
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20195302
SPI™ is a trademark of Motorola, Inc.
© 2007 National Semiconductor Corporation
201953
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Ordering Information
Order Numbers
DAC104S085CISD
DAC104S085CISDX
DAC104S085CIMM
DAC104S085CIMMX
DAC104S085EVAL
Temperature Range
−40°C ≤ TA ≤ +105°C
−40°C ≤ TA ≤ +105°C
−40°C ≤ TA ≤ +105°C
−40°C ≤ TA ≤ +105°C
Package
LLP
Top Mark
X69C
LLP Tape-and-Reel
MSOP
X69C
X68C
MSOP Tape-and-Reel
Evaluation Board (MSOP)
X68C
Block Diagram
20195303
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2
Pin Descriptions
LLP
MSOP
Symbol
Type
Description
Pin No.
VA
1
2
3
4
5
6
Supply
Power supply input. Must be decoupled to GND.
Channel A Analog Output Voltage.
Channel B Analog Output Voltage.
Channel C Analog Output Voltage.
Channel D Analog Output Voltage.
Ground reference for all on-chip circuitry.
VOUTA
VOUTB
VOUTC
VOUTD
GND
Analog Output
Analog Output
Analog Output
Analog Output
Ground
Unbuffered reference voltage shared by all channels. Must be decoupled
to GND.
VREFIN
DIN
7
8
Analog Input
Digital Input
Serial Data Input. Data is clocked into the 16-bit shift register on the falling
edges of SCLK after the fall of SYNC.
Frame synchronization input for the data input. When this pin goes low,
it enables the input shift register and data is transferred on the falling
edges of SCLK. The DAC is updated on the 16th clock cycle unless
SYNC is brought high before the 16th clock, in which case the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the
DAC.
9
SYNC
SCLK
Digital Input
Serial Clock Input. Data is clocked into the input shift register on the
falling edges of this pin.
10
11
Digital Input
Ground
Exposed die attach pad can be connected to ground or left floating.
Soldering the pad to the PCB offers optimal thermal performance and
enhances package self-alignment during reflow.
PAD
(LLP only)
3
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Absolute Maximum Ratings (Notes 1, 2)
Operating Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature Range
−40°C ≤ TA ≤ +105°C
Supply Voltage, VA
Reference Voltage, VREFIN
Digital Input Voltage (Note 7)
Output Load
+2.7V to 5.5V
+1.0V to VA
Supply Voltage, VA
6.5V
−0.3V to 6.5V
10 mA
0.0V to 5.5V
0 to 1500 pF
Up to 40 MHz
Voltage on any Input Pin
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Consumption at TA = 25°C
SCLK Frequency
20 mA
See (Note 4)
Package Thermal Resistances
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
Package
θJA
2500V
250V
10-Lead MSOP
10-Lead LLP
240°C/W
250°C/W
Junction Temperature
Storage Temperature
+150°C
−65°C to +150°C
Soldering
process
must
comply
with
National
Semiconductor's Reflow Temperature Profile specifications.
Refer to www.national.com/packaging. (Note 6)
Electrical Characteristics
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range
12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
STATIC PERFORMANCE
Resolution
10
10
Bits (min)
Bits (min)
LSB (max)
LSB (max)
LSB (min)
mV (max)
%FSR (max)
%FSR
Monotonicity
INL
Integral Non-Linearity
±0.7
+0.08
−0.03
+5
±2
+0.35
−0.25
+15
VA = 2.7V to 5.5V
DNL
Differential Non-Linearity
IOUT = 0
ZE
FSE
GE
Zero Code Error
Full-Scale Error
Gain Error
IOUT = 0
−0.1
−0.2
−20
−0.75
−1.0
All ones Loaded to DAC register
ZCED
Zero Code Error Drift
µV/°C
VA = 3V
VA = 5V
−0.7
−1.0
ppm/°C
TC GE
Gain Error Tempco
ppm/°C
OUTPUT CHARACTERISTICS
0
V (min)
V (max)
Output Voltage Range
(Note 10)
VREFIN
High-Impedance Output
IOZ
±1
µA (max)
Leakage Current (Note 10)
VA = 3V, IOUT = 200 µA
VA = 3V, IOUT = 1 mA
VA = 5V, IOUT = 200 µA
VA = 5V, IOUT = 1 mA
VA = 3V, IOUT = 200 µA
VA = 3V, IOUT = 1 mA
VA = 5V, IOUT = 200 µA
VA = 5V, IOUT = 1 mA
1.3
6.0
mV
mV
mV
mV
V
ZCO
Zero Code Output
Full Scale Output
7.0
10.0
2.984
2.934
4.989
4.958
V
FSO
V
V
VA = 3V, VOUT = 0V,
Input Code = 3FFh
VA = 5V, VOUT = 0V,
Input Code = 3FFh
-56
-69
mA
mA
Output Short Circuit Current
(source)
IOS
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Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Symbol
IOS
Parameter
Conditions
VA = 3V, VOUT = 3V,
52
75
mA
mA
Input Code = 000h
VA = 5V, VOUT = 5V,
Input Code = 000h
Output Short Circuit Current (sink)
Continuous Output
Current (Note 10)
IO
Available on each DAC output
11
mA (max)
1500
1500
7.5
pF
pF
Ω
RL = ∞
RL = 2kΩ
CL
Maximum Load Capacitance
ZOUT
DC Output Impedance
REFERENCE INPUT CHARACTERISTICS
Input Range Minimum
0.2
30
1.0
VA
V (min)
V (max)
kΩ
Input Range Maximum
Input Impedance
VREFIN
LOGIC INPUT CHARACTERISTICS
IIN
Input Current (Note 10)
±1
0.6
0.8
2.1
2.4
3
µA (max)
V (max)
V (max)
V (min)
VA = 3V
VA = 5V
VA = 3V
VA = 5V
0.9
1.5
1.4
2.1
VIL
Input Low Voltage (Note 10)
VIH
CIN
Input High Voltage (Note 10)
Input Capacitance (Note 10)
V (min)
pF (max)
POWER REQUIREMENTS
Supply Voltage Minimum
2.7
5.5
V (min)
V (max)
VA
Supply Voltage Maximum
VA = 2.7V
350
500
330
460
0.10
0.15
1.1
485
650
µA (max)
µA (max)
µA
to 3.6V
fSCLK = 30 MHz
VA = 4.5V
to 5.5V
Normal Supply Current (output
unloaded)
IN
VA = 2.7V
to 3.6V
fSCLK = 0
VA = 4.5V
to 5.5V
µA
VA = 2.7V
to 3.6V
1.0
1.0
1.7
3.6
µA (max)
µA (max)
mW (max)
mW (max)
mW
Power Down Supply Current (output
unloaded, SYNC = DIN = 0V after
PD mode loaded)
All PD Modes,
(Note 10)
IPD
VA = 4.5V
to 5.5V
VA = 2.7V
to 3.6V
fSCLK = 30 MHz
VA = 4.5V
to 5.5V
2.5
Normal Supply Power (output
unloaded)
PN
VA = 2.7V
to 3.6V
1.0
fSCLK = 0
VA = 4.5V
to 5.5V
2.3
mW
VA = 2.7V
to 3.6V
0.3
3.6
5.5
µW (max)
µW (max)
Power Down Supply Power (output
unloaded, SYNC = DIN = 0V after
PD mode loaded)
All PD Modes,
(Note 10)
PPD
VA = 4.5V
to 5.5V
0.8
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A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range
12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified.
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
SCLK Frequency
Conductions
fSCLK
40
30
MHz (max)
100h to 300h code change
Output Voltage Settling Time
(Note 10)
ts
4.5
6
µs (max)
RL = 2 kΩ, CL = 200 pF
SR
Output Slew Rate
Glitch Impulse
1
12
0.5
1
V/µs
nV-sec
nV-sec
nV-sec
nV-sec
kHz
Code change from 200h to 1FFh
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
3
VREFIN = 2.5V ± 0.1Vpp
160
VREFIN = 2.5V ± 0.1Vpp
input frequency = 10kHz
VA = 3V
Total Harmonic Distortion
Wake-Up Time
70
dB
0.8
0.5
25
7
µsec
tWU
VA = 5V
µsec
1/fSCLK
tCH
SCLK Cycle Time
SCLK High time
SCLK Low Time
33
10
10
ns (min)
ns (min)
ns (min)
tCL
7
SYNC Set-up Time prior to SCLK
Falling Edge
tSS
tDS
tDH
4
10
3.5
3.5
ns (min)
ns (min)
ns (min)
Data Set-Up Time prior to SCLK
Falling Edge
1.5
1.5
Data Hold Time after SCLK Falling
Edge
tCFSR
tSYNC
SCLK fall prior to rise of SYNC
SYNC High Time
0
6
3
ns (min)
ns (min)
10
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package
input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond
the operating ratings, or the power supply polarity is reversed).
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: Reflow temperature profiles are different for lead-free packages.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For
example, if VA is 3V, the digital input pins can be driven with a 5V logic device.
20195304
Note 8: To guarantee accuracy, it is required that VA and VREFIN be well bypassed.
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Note 9: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
LSB = VREF / 2n
Specification Definitions
where VREF is the supply voltage for this product, and "n" is
the DAC resolution in bits, which is 10 for the DAC104S085.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB,
MAXIMUM LOAD CAPACITANCE is the maximum capaci-
which is VREF / 1024 = VA / 1024.
tance that can be driven by the DAC with output stability
DAC-to-DAC CROSSTALK is the glitch impulse transferred
maintained.
to a DAC output in response to a full-scale change in the out-
MONOTONICITY is the condition of being monotonic, where
put of another DAC.
the DAC has an output that never decreases when the input
DIGITAL CROSSTALK is the glitch impulse transferred to a
code increases.
DAC output at mid-scale in response to a full-scale change in
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest
value or weight of all bits in a word. Its value is 1/2 of VA.
the input register of another DAC.
DIGITAL FEEDTHROUGH is a measure of the energy inject-
ed into the analog output of the DAC from the digital inputs
MULTIPLYING BANDWIDTH is the frequency at which the
output amplitude falls 3dB below the input sine wave on
when the DAC outputs are not updated. It is measured with a
VREFIN with a full-scale code loaded into the DAC.
full-scale code change on the data bus.
POWER EFFICIENCY is the ratio of the output current to the
FULL-SCALE ERROR is the difference between the actual
total supply current. The output current comes from the power
output voltage with a full scale code (3FFh) loaded into the
supply. The difference between the supply and output cur-
DAC and the value of VA x 1023 / 1024.
rents is the power consumed by the device without a load.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Zero and Full-
SETTLING TIME is the time for the output to settle to within
1/2 LSB of the final value after the input code is updated.
Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE
TOTAL HARMONIC DISTORTION (THD) is the measure of
the harmonics present at the output of the DACs with an ideal
sine wave applied to VREFIN. THD is measured in dB.
is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog out-
put when the input code to the DAC register changes. It is
specified as the area of the glitch in nanovolt-seconds.
WAKE-UP TIME is the time for the output to exit power-down
mode. This is the time from the falling edge of the 16th SCLK
pulse to when the output voltage deviates from the power-
down voltage of 0V.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The end point method is used. INL for this product
is specified over a limited range, per the Electrical Tables.
ZERO CODE ERROR is the output error, or voltage, present
at the DAC output after a code of 000h has been entered.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the small-
est value or weight of all bits in a word. This value is
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Transfer Characteristic
20195305
FIGURE 1. Input / Output Transfer Characteristic
Timing Diagrams
20195306
FIGURE 2. Serial Timing Diagram
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Typical Performance Characteristics VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to
1011, unless otherwise stated
INL at VA = 3.0V
INL at VA = 5.0V
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DNL at VA = 3.0V
DNL at VA = 5.0V
INL/DNL vs VREFIN at VA = 3.0V
INL/DNL vs VREFIN at VA = 5.0V
9
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INL/DNL vs fSCLK at VA = 2.7V
INL/DNL vs VA
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20195322
INL/DNL vs Clock Duty Cycle at VA = 3.0V
INL/DNL vs Clock Duty Cycle at VA = 5.0V
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INL/DNL vs Temperature at VA = 3.0V
INL/DNL vs Temperature at VA = 5.0V
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Zero Code Error vs. VA
Zero Code Error vs. VREFIN
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Zero Code Error vs. fSCLK
Zero Code Error vs. Clock Duty Cycle
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Zero Code Error vs. Temperature
Full-Scale Error vs. VA
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Full-Scale Error vs. VREFIN
Full-Scale Error vs. fSCLK
Full-Scale Error vs. Temperature
Supply Current vs. Temperature
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Full-Scale Error vs. Clock Duty Cycle
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Supply Current vs. VA
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5V Glitch Response
Power-On Reset
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output impedance. The reference voltage range is 1.0V to
VA, providing the widest possible output dynamic range.
1.0 Functional Description
1.1 DAC SECTION
1.4 SERIAL INTERFACE
The DAC104S085 is fabricated on a CMOS process with an
architecture that consists of switches and resistor strings that
are followed by an output buffer. The reference voltage is ex-
ternally applied at VREFIN and is shared by all four DACs.
The three-wire interface is compatible with SPI, QSPI and
MICROWIRE, as well as most DSPs and operates at clock
rates up to 40 MHz. See the Timing Diagram for information
on a write sequence.
For simplicity, a single resistor string is shown in Figure 3.
This string consists of 1024 equal valued resistors with a
switch at each junction of two resistors, plus a switch to
ground. The code loaded into the DAC register determines
which switch is closed, connecting the proper node to the
amplifier. The input coding is straight binary with an ideal out-
put voltage of:
A write sequence begins by bringing the SYNC line low. Once
SYNC is low, the data on the DIN line is clocked into the 16-
bit serial input register on the falling edges of SCLK. To avoid
misclocking data into the shift register, it is critical that
SYNC not be brought low simultaneously with a falling edge
of SCLK (see Serial Timing Diagram, Figure 2). On the 16th
falling clock edge, the last data bit is clocked in and the pro-
grammed function (a change in the DAC channel address,
mode of operation and/or register contents) is executed. At
this point the SYNC line may be kept low or brought high. Any
data and clock pusles after the 16th falling clock edge will be
ignored. In either case, SYNC must be brought high for the
minimum specified time before the next write sequence is ini-
tiated with a falling edge of SYNC.
VOUTA,B,C,D = VREFIN x (D / 1024)
where D is the decimal equivalent of the binary code that is
loaded into the DAC register. D can take on any value be-
tween 0 and 1023. This configuration guarantees that the
DAC is monotonic.
Since the SYNC and DIN buffers draw more current when they
are high, they should be idled low between write sequences
to minimize power consumption.
1.5 INPUT SHIFT REGISTER
The input shift register, Figure 4, has sixteen bits. The first
two bits are address bits. They determine whether the register
data is for DAC A, DAC B, DAC C, or DAC D. The address
bits are followed by two bits that determine the mode of op-
eration (writing to a DAC register without updating the outputs
of all four DACs, writing to a DAC register and updating the
outputs of all four DACs, writing to the register of all four DACs
and updating their outputs, or powering down all four outputs).
The final twelve bits of the shift register are the data bits. The
data format is straight binary (MSB first, LSB last), with all 0's
corresponding to an output of 0V and all 1's corresponding to
a full-scale output of VREFIN - 1 LSB. The contents of the serial
input register are transferred to the DAC register on the six-
teenth falling edge of SCLK. See Timing Diagram, Figure 2.
20195307
FIGURE 3. DAC Resistor String
1.2 OUTPUT AMPLIFIERS
The output amplifiers are rail-to-rail, providing an output volt-
age range of 0V to VA when the reference is VA. All amplifiers,
even rail-to-rail types, exhibit a loss of linearity as the output
approaches the supply rails (0V and VA, in this case). For this
reason, linearity is specified over less than the full output
range of the DAC. However, if the reference is less than VA,
there is only a loss in linearity in the lowest codes. The output
capabilities of the amplifier are described in the Electrical Ta-
bles.
20195308
FIGURE 4. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling
edges of SCLK and the DAC is updated on the 16th SCLK
falling edge. However, if SYNC is brought high before the 16th
falling edge, the data transfer to the shift register is aborted
and the write sequence is invalid. Under this condition, the
DAC register is not updated and there is no change in the
mode of operation or in the DAC output voltages.
The output amplifiers are capable of driving a load of 2 kΩ in
parallel with 1500 pF to ground or to VA. The zero-code and
full-scale outputs for given load currents are available in the
Electrical Characterisics Table.
1.3 RERENCE VOLTAGE
1.6 POWER-ON RESET
The DAC104S085 uses a single external reference that is
shared by all four channels. The reference pin, VREFIN, is not
buffered and has an input impedance of 30 kΩ. It is recom-
mended that VREFIN be driven by a voltage source with low
The power-on reset circuit controls the output voltages of the
four DACs during power-up. Upon application of power, the
DAC registers are filled with zeros and the output voltages are
0V. The outputs remain at 0V until a valid write sequence is
made to the DAC.
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1.7 POWER-DOWN MODES
The DAC104S085 has four power-down modes, two of which
are identical. In power-down mode, the supply current drops
to 20 µA at 3V and 30 µA at 5V. The DAC104S085 is set in
power-down mode by setting OP1 and OP0 to 11. Since this
mode powers down all four DACs, the address bits, A1 and
A0, are used to select different output terminations for the
DAC outputs. Setting A1 and A0 to 00 or 11 causes the out-
puts to be tri-stated (a high impedance state). While setting
A1 and A0 to 01 or 10 causes the outputs to be terminated by
2.5 kΩ or 100 kΩ to ground respectively (see Table 1).
20195313
TABLE 1. Power-Down Modes
FIGURE 5. The LM4130 as a power supply
2.1.2 LM4050
A1
0
A0
0
OP1
OP0
ꢀOperating Mode
High-Z outputs
2.5 kΩ to GND
100 kΩ to GND
High-Z outputs
1
1
1
1
1
1
1
1
0
1
Available with accuracy of 0.44%, the LM4050 shunt refer-
ence is also a good choice as a reference for the
DAC104S085. It is available in 4.096V and 5V versions and
comes in a space-saving 3-pin SOT23.
1
0
1
1
The bias generator, output amplifiers, resistor strings, and
other linear circuitry are all shut down in any of the power-
down modes. However, the contents of the DAC registers are
unaffected when in power-down. Each DAC register main-
tains its value prior to the DAC104S085 being powered down
unless it is changed during the write sequence which instruct-
ed it to recover from power down. Minimum power consump-
tion is achieved in the power-down mode with SYNC and
DIN idled low and SCLK disabled. The time to exit power-down
(Wake-Up Time) is typically 0.8 µsec at 3V and 0.5 µsec at
5V.
2.0 Applications Information
2.1 USING REFERENCES AS POWER SUPPLIES
While the simplicity of the DAC104S085 implies ease of use,
it is important to recognize that the path from the reference
input (VREFIN) to the VOUTs will have essentially zero Power
Supply Rejection Ratio (PSRR). Therefore, it is necessary to
provide a noise-free supply voltage to VREFIN. In order to uti-
lize the full dynamic range of the DAC104S085, the supply
pin (VA) and VREFIN can be connected together and share the
same supply voltage. Since the DAC104S085 consumes very
little power, a reference source may be used as the reference
input and/or the supply voltage. The advantages of using a
reference source over a voltage regulator are accuracy and
stability. Some low noise regulators can also be used. Listed
below are a few reference and power supply options for the
DAC104S085.
20195314
FIGURE 6. The LM4050 as a power supply
The minimum resistor value in the circuit of Figure 6 must be
chosen such that the maximum current through the LM4050
does not exceed its 15 mA rating. The conditions for maxi-
mum current include the input voltage at its maximum, the
LM4050 voltage at its minimum, and the DAC104S085 draw-
ing zero current. The maximum resistor value must allow the
LM4050 to draw more than its minimum current for regulation
plus the maximum DAC104S085 current in full operation. The
conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor
value at its maximum due to tolerance, and the DAC104S085
draws its maximum current. These conditions can be sum-
marized as
2.1.1 LM4130
The LM4130, with its 0.05% accuracy over temperature, is a
good choice as a reference source for the DAC104S085. The
4.096V version is useful if a 0 to 4.095V output range is de-
sirable or acceptable. Bypassing the LM4130 VIN pin with a
0.1µF capacitor and the VOUT pin with a 2.2µF capacitor will
improve stability and reduce output noise. The LM4130
comes in a space-saving 5-pin SOT23.
R(min) = ( VIN(max) − VZ(min) ) /IZ(max)
and
R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )
where VZ(min) and VZ(max) are the nominal LM4050 output
voltages ± the LM4050 output tolerance over temperature, IZ
(max) is the maximum allowable current through the LM4050,
IZ(min) is the minimum current required by the LM4050 for
proper regulation, and IDAC(max) is the maximum
DAC104S085 supply current.
15
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2.1.3 LP3985
2.2 BIPOLAR OPERATION
The LP3985 is a low noise, ultra low dropout voltage regulator
with a 3% accuracy over temperature. It is a good choice for
applications that do not require a precision reference for the
DAC104S085. It comes in 3.0V, 3.3V and 5V versions, among
others, and sports a low 30 µV noise specification at low fre-
quencies. Since low frequency noise is relatively difficult to
filter, this specification could be important for some applica-
tions. The LP3985 comes in a space-saving 5-pin SOT23 and
5-bump micro SMD packages.
The DAC104S085 is designed for single supply operation and
thus has a unipolar output. However, a bipolar output may be
obtained with the circuit in Figure 9. This circuit will provide
an output voltage range of ±5 Volts. A rail-to-rail amplifier
should be used if the amplifier supplies are limited to ±5V.
20195317
FIGURE 9. Bipolar Operation
20195315
The output voltage of this circuit for any code is found to be
VO = (VA x (D / 1024) x ((R1 + R2) / R1) - VA x R2 / R1)
FIGURE 7. Using the LP3985 regulator
where D is the input code in decimal form. With VA = 5V and
R1 = R2,
An input capacitance of 1.0µF without any ESR requirement
is required at the LP3985 input, while a 1.0µF ceramic ca-
pacitor with an ESR requirement of 5mΩ to 500mΩ is required
at the output. Careful interpretation and understanding of the
capacitor specification is required to ensure correct device
operation.
VO = (10 x D / 1024) - 5V
A list of rail-to-rail amplifiers suitable for this application are
indicated in Table 2.
TABLE 2. Some Rail-to-Rail Amplifiers
2.1.4 LP2980
Typ ISUPPLY
AMP
PKGS
ꢀTyp VOS
The LP2980 is an ultra low dropout regulator with a 0.5% or
1.0% accuracy over temperature, depending upon grade. It is
available in 3.0V, 3.3V and 5V versions, among others.
DIP-8
SOT23-5
LMC7111
0.9 mV
25 µA
SO-8
SOT23-5
LM7301
LM8261
0.03 mV
0.7 mV
620 µA
1 mA
SOT23-5
20195316
FIGURE 8. Using the LP2980 regulator
Like any low dropout regulator, the LP2980 requires an output
capacitor for loop stability. This output capacitor must be at
least 1.0µF over temperature, but values of 2.2µF or more will
provide even better performance. The ESR of this capacitor
should be within the range specified in the LP2980 data sheet.
Surface-mount solid tantalum capacitors offer a good combi-
nation of small size and ESR. Ceramic capacitors are attrac-
tive due to their small size but generally have ESR values that
are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large
size and have ESR values that may be too high at low tem-
peratures.
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16
2.3 DSP/MICROPROCESSOR INTERFACING
mits data in 8-bit bytes with eight falling clock edges. Data is
transmitted with the MSB first. PC7 must remain low after the
first eight bits are transferred. A second write cycle is initiated
to transmit the second byte of data to the DAC, after which
PC7 should be raised to end the write sequence.
Interfacing the DAC104S085 to microprocessors and DSPs
is quite simple. The following guidelines are offered to hasten
the design process.
2.3.1 ADSP-2101/ADSP2103 Interfacing
Figure 10 shows a serial interface between the DAC104S085
and the ADSP-2101/ADSP2103. The DSP should be set to
operate in the SPORT Transmit Alternate Framing Mode. It is
programmed through the SPORT control register and should
be configured for Internal Clock Operation, Active Low Fram-
ing and 16-bit Word Length. Transmission is started by writing
a word to the Tx register after the SPORT mode has been
enabled.
20195311
FIGURE 12. 68HC11 Interface
2.3.4 Microwire Interface
Figure 13 shows an interface between a Microwire compatible
device and the DAC104S085. Data is clocked out on the rising
edges of the SK signal. As a result, the SK of the Microwire
device needs to be inverted before driving the SCLK of the
DAC104S085.
20195309
FIGURE 10. ADSP-2101/2103 Interface
2.3.2 80C51/80L51 Interface
A serial interface between the DAC104S085 and the
80C51/80L51 microcontroller is shown in Figure 11. The
SYNC signal comes from a bit-programmable pin on the mi-
crocontroller. The example shown here uses port line P3.3.
This line is taken low when data is transmitted to the
DAC104S085. Since the 80C51/80L51 transmits 8-bit bytes,
only eight falling clock edges occur in the transmit cycle. To
load data into the DAC, the P3.3 line must be left low after the
first eight bits are transmitted. A second write cycle is initiated
to transmit the second byte of data, after which port line P3.3
is brought high. The 80C51/80L51 transmit routine must rec-
ognize that the 80C51/80L51 transmits data with the LSB first
while the DAC104S085 requires data with the MSB first.
20195312
FIGURE 13. Microwire Interface
2.4 LAYOUT, GROUNDING, AND BYPASSING
For best accuracy and minimum noise, the printed circuit
board containing the DAC104S085 should have separate
analog and digital areas. The areas are defined by the loca-
tions of the analog and digital power planes. Both of these
planes should be located in the same board layer. There
should be a single ground plane. A single ground plane is
preferred if digital return current does not flow through the
analog ground area. Frequently a single ground plane design
will utilize a "fencing" technique to prevent the mixing of ana-
log and digital ground current. Separate ground planes should
only be utilized when the fencing technique is inadequate.
The separate ground planes must be connected in one place,
preferably near the DAC104S085. Special care is required to
guarantee that digital signals with fast edge rates do not pass
over split ground planes. They must always have a continu-
ous return path below their traces.
20195310
FIGURE 11. 80C51/80L51 Interface
The DAC104S085 power supply should be bypassed with a
10µF and a 0.1µF capacitor as close as possible to the device
with the 0.1µF right at the device supply pin. The 10µF ca-
pacitor should be a tantalum type and the 0.1µF capacitor
should be a low ESL, low ESR type. The power supply for the
DAC104S085 should only be used for analog circuits.
2.3.3 68HC11 Interface
A serial interface between the DAC104S085 and the 68HC11
microcontroller is shown in Figure 12. The SYNC line of the
DAC104S085 is driven from a port line (PC7 in the figure),
similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero
and its CPHA bit as a one. This configuration causes data on
the MOSI output to be valid on the falling edge of SCLK. PC7
is taken low to transmit data to the DAC. The 68HC11 trans-
Avoid crossover of analog and digital signals and keep the
clock and data lines on the component side of the board. The
clock and data lines should have controlled impedances.
17
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Physical Dimensions inches (millimeters) unless otherwise noted
10-Lead MSOP
Order Numbers DAC104S085CIMM
NS Package Number MUB10A
10-Lead LLP
Order Numbers DAC104S085CISD
NS Package Number SDA10A
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18
Notes
19
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