DAC1054CMJ [NSC]
Quad 10-Bit Voltage-Output Serial D/A Converter with Readback; 四通道10位电压输出串行D / A转换器，具有回读
| 型号： | DAC1054CMJ |
| 厂家： | 
National Semiconductor |
| 描述： | Quad 10-Bit Voltage-Output Serial D/A Converter with Readback |
| 文件： | 总14页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1995
DAC1054 Quad 10-Bit Voltage-Output
Serial D/A Converter with Readback
General Description
Features
Y
a
Single 5V supply operation
The DAC1054 is a complete quad 10-bit voltage-output digi-
tal-to-analog converter that can operate on a single 5V sup-
ply. It includes on-chip output amplifiers, internal voltage ref-
erence, and serial microprocessor interface. By combining
in one package the reference, amplifiers, and conversion
circuitry for four D/A converters, the DAC1054 minimizes
wiring and parts count and is hence ideally suited for appli-
cations where cost and board space are of prime concern.
Y
MICROWIRE serial interface allows easy interface to
many popular microcontrollers including the COPSTM
and HPCTM families of microcontrollers
Data readback capability
Y
Y
Output data can be formatted to read back MSB or
LSB first
Y
Versatile logic allows selective or global update of the
DACs
The DAC1054 also has a data readback function, which can
be used by the microprocessor to verify that the desired
input word has been properly latched into the DAC1054’s
data registers. The data readback function simplifies the de-
sign and reduces the cost of systems which need to verify
data integrity.
Y
Y
Y
Power fail flag
Output amplifiers can drive 2 kX load
Synchronous/asynchronous update of the DAC outputs
Key Specifications
Y
The logic comprises a MICROWIRETM-compatible serial in-
terface and control circuitry. The interface allows the user to
write to any one of the input registers or to all four at once.
The latching registers are double-buffered, consisting of 4
separate input registers and 4 DAC registers. Each DAC
register may be written to individually. Double buffering al-
lows all 4 DAC outputs to be updated simultaneously or
individually.
Guaranteed monotonic over temperature
Y
g
Integral linearity error
*/4 LSB max
3.7 ms max
Y
Output settling time
Y
Analog output voltage range
0.3V to 2.8V
4.5V to 5.5V
10 MHz max
5 MHz max
Y
Supply voltage range
Y
Clock frequency for write
Y
Clock frequency for read back
Y
The four reference inputs allow the user to configure the
system to have a separate output voltage range for each
DAC. The output voltage of each DAC can range between
e
10 MHz)
Power dissipation (f
On-board reference
100 mW max
CLK
Y
g
2.65V 2% max
0.3V and 2.8V and is a function of V , V , and the
BIAS REF
input word.
Applications
Y
Automatic test equipment
Y
Y
Y
Industrial process controls
Automotive controls and diagnostics
Instrumentation
Connection Diagram
Ordering Information
k
k
b
Industrial ( 40 C
a
85 C)
T
Package
§
§
A
DAC1054CIN
N24A Molded DIP
M24B Small Outline
DAC1054CIWM
k
k
b
Military ( 55 C
a
T
125 C)
§
§
A
DAC1054CMJ/883 or
5962-9466201MJA
J24A Ceramic DIP
TL/H/11437–1
Top View
COPSTM, HPCTM and MICROWIRETM are trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/H/11437
RRD-B30M75/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Soldering Information
N Package (10 sec.)
SO Package
260 C
§
Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)
215 C
§
Supply Voltage (AV , DV
)
7V
CC CC
220 C
§
g
Supply Voltage Difference (AV –DV
CC
)
CC
5.5V
b
a
65 C to 150 C
Storage Temperature
§
§
b
GND 0.3V to
Voltage at Any Pin (Note 3)
a
AV /DV
CC
0.3V
CC
Operating Ratings (Notes 1 & 2)
Supply Voltage
Input Current at Any Pin (Note 3)
Package Input Current (Note 4)
Power Dissipation (Note 5)
5 mA
4.5V to 5.5V
30 mA
b
g
1V
Supply Voltage Difference (AV
DV
)
CC
CC
950 mW
k
k
k
T
Temperature Range
DAC1054CIN, DAC1054CIWM
DAC1054CMJ/883
T
T
T
MIN
A
MAX
85 C
§
ESD Susceptibility (Note 6)
Human Body Model
Machine Model
k
b
40 C
§
55 C
A
2000V
200V
k
k
b
T
A
125 C
§
§
Converter Electrical Characteristics
e
e
e
e
10 MHz unless otherwise specified. Boldface limits apply for T
e
1.4V, R 2 kX (R is the load resistor on
The following specifications apply for AV
DV
CC
5V, V
2.65V, V
CC
REF
BIAS
L
L
e
the analog outputs – pins 2, 13, 17, and 23) and f
CLK
A
e
e
25 C.
T
from T
to T
. All other limits apply for T
MAX A
§
J
MIN
Typical
(Note 8)
Limit
Units
Symbol
Parameter
Conditions
(Note 9)
(Limits)
STATIC CHARACTERISTICS
Resolution
n
10
10
10
10
bits
bits
Monotonicity
(Note 10)
(Note 11)
Integral Linearity Error
g
DAC1054CIN, DAC1054CIWM
0.75
LSB (max)
LSB (max)
mV
g
Differential Linearity Error
Fullscale Error
1.0
g
(Note 12)
(Note 13)
(Note 14)
(Note 13)
(Note 15)
30
25
34
b
b
Fullscale Error Tempco
Zero Error
38
38
ppm/ C
§
g
mV
Zero Error Tempco
Power Supply Sensitivity
ppm/ C
§
b
dB (max)
DYNAMIC CHARACTERISTICS
t
Positive Voltage Output
Settling Time
(Note 16)
e
a
s
1.8
3.2
3.7
ms
ms
C
L
200 pF
t
s
Negative Voltage Output
Settling Time
(Note 16)
e
b
2.3
C
L
200 pF
Digital Crosstalk
(Note 17)
(Note 18)
(Note 19)
15
15
20
mV
mV
mV
p-p
p-p
p-p
Digital Feedthrough
Clock Feedthrough
b
Channel-to-Channel Isolation
Glitch Energy
(Note 20)
(Note 21)
71
dB
b
nV s
7
Peak Value of Largest Glitch
Power Supply Rejection Ratio
38
mV
dB
b
49
PSRR
(Note 22)
2
Converter Electrical Characteristics (Continued)
e
the analog outputs – pins 2, 13, 17, and 23) and f
e
e
e
10 MHz unless otherwise specified. Boldface limits apply for T
e
1.4V, R 2 kX (R is the load resistor on
The following specifications apply for AV
DV
5V, V
2.65V, V
CC
CC
REF
BIAS
L
L
e
CLK
. All other limits apply for T
A
e
e
25 C.
T
from T
to T
§
J
MIN
MAX
A
Typical
(Note 3)
Limit
Units
Symbol
Parameter
Conditions
(Note 4)
(Limits)
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
e
e
e
e
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Digital Input Leakage Current
Input Capacitance
AV
AV
DV
DV
5.5V
4.5V
2.0
0.8
1
V (min)
V (max)
mA (max)
pF
IN(1)
CC
CC
IN(0)
CC
CC
I
IL
C
C
4
5
IN
Output Capacitance
pF
OUT
OUT(1)
OUT(0)
INT
e
V
V
V
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Interrupt Pin Output Voltage
Supply Current
I
I
0.8 mA
2.4
0.4
0.4
20
V (min)
V (max)
V (max)
mA
SOURCE
e
3.2 mA
SINK
10 kX Pullup
I
Outputs Unloaded
14
S
REFERENCE INPUT CHARACTERISTICS
V
Input Voltage Range
Input Resistance
0–2.75
7
V
REF
R
4
9
kX (min)
kX (max)
REF
C
REF
Input Capacitance
Full-Scale Data Input
25
pF
V
BIAS
INPUT CHARACTERISTICS
V
BIAS
V
BIAS
Input Voltage Range
0.3–1.4
V
Input Leakage
1
9
mA
pF
C
BIAS
Input Capacitance
e
BANDGAP REFERENCE CHARACTERISTICS (C
220mF)
L
g
2.65 2%
V
OUT
Output Voltage
Tempco
V
REF
DV
/DT
REF
(Note 23)
29
ppm/ C
§
k
k
5.5V, I
e
Line Regulation
Load Regulation
4.5V
V
4 mA
5
mV
CC
L
k
k
4 mA
DV
/DI
REF
0
I
10
mV
mV
L
L
k
k
0 mA
b
1
I
2.5
12
L
e
I
Short Circuit Current
V
OUT
REF
0V
mA
SC
AC ELECTRICAL CHARACTERISTICS
t
t
t
t
f
f
t
t
Data Setup Time
15
0
ns (min)
ns (min)
DS
Data Hold Time
DH
Control Setup Time
15
0
ns (min)
CS
Control Hold Time
ns (min)
CH
Clock Frequency Write
Clock Frequency Readback
Minimum Clock High Time
Minimum Clock Low Time
10
5
MHz (max)
MHz (max)
ns (min)
WMAX
RMAX
H
20
20
ns (min)
L
3
Converter Electrical Characteristics (Continued)
e
e
e
e
10 MHz unless otherwise specified. Boldface limits apply for T
e
1.4V, R 2 kX (R is the load resistor on
The following specifications apply for AV
DV
CC
5V, V
2.65V, V
CC
REF
BIAS
L
L
e
the analog outputs – pins 2, 13, 17, and 23) and f
CLK
A
e
e
25 C.
T
from T
to T
. All other limits apply for T
MAX A
§
J
MIN
Typical
(Note 3)
Limit
Units
Symbol
Parameter
Conditions
(Note 4)
(Limits)
AC ELECTRICAL CHARACTERISTICS (Continued)
e
e
t
t
t
t
Output Hi-Z to Valid 1
Output Hi-Z to Valid 0
CS to Output Hi-Z
f
f
5 MHz
5 MHz
70
70
ns (max)
ns (max)
ns (max)
ns (max)
CZ1
CZ0
1H
CLK
CLK
e
e
10 kX with 60 pF, f
5 MHz
5 MHz
150
130
CLK
CLK
CS to Output Hi-Z
10 kX with 60 pF, f
0H
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Converter Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not
operated under the listed test conditions.
Note 2: All voltages are measured with respect to ground, unless otherwise specified.
a) the absolute value of current at that pin should be limited
k
l
V
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
to 5 mA or less.
GND or V
IN
IN
Note 4: The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 30 mA.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by
(package junction to ambient thermal resistance), and (ambient temperature). The maximum allowable power dissipation at any temperature is
T
(maximum junction temperature), H
JA
Jmax
T
A
e
packages and versions of the DAC1054.
b
T
P
Dmax
(T
)/H or the number given in the Absolute Maximum Ratings, whichever is lower. The table below details T and H for the various
JA Jmax JA
Jmax
A
Part Number
T
( C)
§
H
( C/W)
§
Jmax
JA
DAC1054CIN
125
125
42
57
DAC1054CIWM
Note 6: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Production Reliability’’ of the section titled ‘‘Surface Mount’’ found in any current Linear
Databook for other methods of soldering surface mount devices.
e
Note 8: Typicals are at T
25 C and represent most likely parametric norm.
§
Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
J
Note 10: A monotonicity of 10 bits for the DAC1054 means that the output voltage changes in the same direction (or remains constant) for each increase in the
input code.
Note 11: Integral linearity error is the maximum deviation of the output from the line drawn between zero and full-scale (excluding the effects of zero error and full-
scale error).
e
e
Note 12: Full-scale error is measured as the deviation from the ideal 2.800V full-scale output when V
Note 13: Full-scale error tempco and zero error tempco are defined by the following equation:
2.650V and V
1.400V.
REF
BIAS
6
10
b
Error (T
)
Error (T
)
MIN
MAX
e
Error tempco
b
V
T
T
Ð
( Ð
(
Note 16: Positive or negative settling time is defined as the time taken for the output of the DAC to settle to its final full-scale or zero output to within 0.5 LSB.
SPAN
MAX
MIN
where Error (T
MAX
) is the zero error or full-scale error at T
(in volts), and Error (T
) is the zero error or full-scale error at T
(in volts); V
is the output
MAX
and V
MIN
MIN
SPAN
voltage span of the DAC1054, which depends on V
BIAS
.
REF
e
e
BIAS
Note 14: Zero error is measured as the deviation from the ideal 0.302V output when V
2.650V, V
1.400V, and the digital input word is all zeros.
REF
Note 15: Power Supply Sensitivity is the maximum change in the offset error or the full-scale error when the power supply differs from its optimum 5V by up to
e
0.50V (10%). The load resistor R
2 kX.
L
g
This time shall be referenced to the 50% point of the positive edge of CS, which initiates the update of the analog outputs.
Note 17: Digital crosstalk is the glitch measured on the output of one DAC while applying an all 0s to all 1s transition at the input of the other DACs.
Note 18: All DACs have full-scale outputs latched and DI is clocked with no update of the DAC outputs. The glitch is then measured on the DAC outputs.
Note 19: Clock feedthrough is measured for each DAC with its output at full-scale. The serial clock is then applied to the DAC at a frequency of 10 MHz and the
glitch on each DAC full-scale output is measured.
Note 20: Channel-to-channel isolation is a measure of the effect of a change in one DAC’s output on the output of another DAC. The V
of the first DAC is varied
REF
between 1.4V and 2.65V at a frequency of 15 kHz while the change in full-scale output of the second DAC is measured. The first DAC is loaded with all 0s.
Note 21: Glitch energy is the difference between the positive and negative glitch areas at the output of the DAC when a 1 LSB digital input code change is applied
to the input. The glitch energy will have its largest value at one of the three major transitions. The peak value of the maximum glitch is separately specified.
e
of this signal imposed on a full-scale output of the DAC under consideration.
Note 22: Power Supply Rejection Ratio is measured by varying AV
CC
DV between 4.50V and 5.50V with a frequency of 10 kHz and measuring the proportion
CC
Note 23: The bandgap reference tempco is defined by the largest value from the following equations:
6
6
10
b
b
V
V
(T
REF MAX
)
V
(T
REF ROOM
)
10
V
(T
REF MIN
)
(T
REF ROOM
)
e
e
)
MIN
Tempco (T
MAX
)
or Tempco (T
b
b
T
V
(T
REF ROOM
)
T
T
V
(T
REF ROOM
)
T
Ð
( Ð
(
Ð
( Ð
(
MAX
ROOM
ROOM
MIN
e
where T
25 C, V
(T
REF MAX
) is the reference output at T
, and similarly for V
(T
REF MIN
) and V
(T ).
REF ROOM
§
Note 24: A Military RETS specification is available upon request.
ROOM
MAX
4
Typical Converter Performance Characteristics
Zero Error vs
Temperature
Full-Scale Error
vs Temperature
Supply Current
vs Temperature
TL/H/11437–2
Typical Reference Performance Characteristics
Bandgap Voltage
vs Temperature
Line Regulation
vs Temperature
TL/H/11437–3
TL/H/11437–4
5
TRI-STATE Test Circuits and Waveforms
TL/H/11437–6
TL/H/11437–5
TL/H/11437–8
TL/H/11437–7
Timing Waveforms
Data Input Timing
Data Output Timing
TL/H/11437–10
TL/H/11437–9
Timing Diagrams
TL/H/11437–11
e
FIGURE 1. Write to One DAC with Update of Output (AU
1), 10 MHz Maximum CLK Rate
6
Timing Diagrams (Continued)
TL/H/11437–12
* DACs are written to MSB first.
DAC1 is written to first, then DACs 2, 3, and 4.
e
FIGURE 2. Write to All DACs with Update of Outputs (AU
1), 10 MHz Maximum CLK Rate
TL/H/11437–13
e
FIGURE 3. Read One DAC, DO LSB First, DO Changes on Falling Edge of CLK (AU
1), 5 MHz Maximum CLK Rate
TL/H/11437–14
*DAC1 is read first, then DACs 2, 3, and 4.
e
FIGURE 4. Read All DACs, DO LSB First, DO Changes on Falling Edge of CLK (AU
1), 5 MHz Maximum CLK Rate
7
Block Diagram
TL/H/11437–15
Pin Description
V
OUT1
V
OUT2
V
OUT3
V
OUT4
(2),
The voltage output connections of the
four DACS. These provide output
voltages in the range 0.3V–2.8V.
AU(11)
When this pin is taken low, all DAC outputs
will be asynchronously updated. CS must
be held high during the update. AU must be
held high during Read back.
(23),
(17),
(13)
V
OUT(21) The internal voltage reference output.
The output of the reference is 2.65V
REF
V
V
V
V
(1),
The voltage reference inputs for the four
REF1
REF2
REF3
REF4
(22), DACs. The allowed range is 0V–2.75V.
g
2%.
(18),
(14)
V
BIAS1
V
BIAS2
V
BIAS3
V
BIAS4
(3),
The non-inverting inputs of the 4 output
amplifiers. These pins set the virtual
ground voltage for the respective DACs.
The allowed range is 0.3V–1.4V.
(24),
(16),
(15)
CS(9)
The Chip Select control input. This input is
active low.
CLK(8)
DI(10)
The external clock input pin.
AGND(20),
DGND(5)
The analog and digital ground pins.
The serial data input. The data is clocked in
MSB first. Preceding the data byte are 4 or
6 bits of instructions. The read back
DV (4, 6),
CC
The digital and analog power supply
pins. The power supply range of the
DAC1054 is 4.5V–5.5V. To guarantee
AV (19)
CC
command requires 7 bits of instructions.
DO(7)
The serial data output. The data can be
clocked out either MSB or LSB first, and on
either the positive or negative edge of the
clock.
accuracy, it is required that the AV
CC
and DV pins be bypassed separately
CC
with bypass capacitors of 10 mF
tantalum in parallel with 0.1 mF ceramic.
INT(12)
The power interrupt output. On an
interruption of the digital power supply, this
pin goes low. Since this pin has an open
drain output, a 10 kX pull-up resistor must
be connected to the supply.
8
Applications Information
FUNCTIONAL DESCRIPTION
The current output I , summed with the correction cur-
OUT2
rent I , is applied to the internal output amplifier and
EEPROM
converted to a voltage. The output voltage of each DAC is a
The DAC1054 is a monolithic quad 10-bit digital-to-analog
converter that is designed to operate on a single 5V supply.
Each of the four units is comprised of an input register, a
DAC register, a shift register, a current output DAC, and an
output amplifier. In addition, the DAC1054 has an onboard
bandgap reference and a logic unit which controls the inter-
nal operation of the DAC1054 and interfaces it to micro-
processors.
function of V
given by
, V
BIAS
, and the digital input word, and is
REF
DATA 2047
1023
512
e
b
a
b
V
BIAS
V
OUT
2 (V
REF
V
BIAS
)
V
REF
1024
512
The output voltage range for each DAC is 0.3V–2.8V. This
range can be achieved by using the internal 2.65V reference
Each of the four internal 10-bit DACs uses a modified R-2R
ladder to effect the digital-to-analog conversion (Figure 5).
The resistances corresponding to the 2 most significant bits
are segmented to reduce glitch energy and to improve
matching. The bottom of the ladder has been modified so
that the voltage across the LSB resistor is much larger than
the input offset voltage of the buffer amplifier. The input
digital code determines the state of the switches in the lad-
der network. An internal EEPROM, which is programmed at
the factory, is used to correct for linearity errors in the resis-
tor ladder of each of the four internal DACs. The codes
stored in the EEPROM’s memory locations are converted to
and a voltage divider network which provides a V
1.40V (Figure 6). In this case the DAC transfer function is
of
BIAS
(DATA)
e
a
0.30244
V
2.5
OUT
1024
The output impedance of any external reference that is
used will affect the accuracy of the conversion. In order that
this error be less than (/2 LSB, the output impedance of the
external reference must be less than 2X.
a current, I
rents I
, with a small trim DAC. The sum of cur-
is fixed and is given by
OUT2
EEPROM
and I
OUT1
b
V
REF
V
BIAS
1023
1024
a
e
I
I
OUT2
OUT1
R
#
J
TL/H/11437–16
FIGURE 5. Equivalent Circuit of R-2R Ladder and Output Amplifier
TL/H/11437–17
e
FIGURE 6. Generating a V
BIAS
1.40V from the Internal Reference, Typical Application
9
Digital Interface
The DAC1054 has two interface modes: a WRITE mode
and a READ mode. The WRITE mode is used to convert a
10-bit digital input word into a voltage. The READ mode is
used to read back the digital data that was sent to one or all
of the DACs. The WRITE mode maximum clock rate is
10 MHz. READ mode is limited to a 5 MHz maximum clock
rate. These modes are selected by the appropriate setting
of the RD/WR bit, which is part of the instruction byte. The
instruction byte precedes the data byte at the DI pin. In both
modes, a high level on the Start Bit (SB) alerts the DAC to
respond to the remainder of the input stream.
high; DAC 1 is written to first, then DACs 2, 3 and 4 (in that
order). For a global write bits A0 and A1 of the instruction
byte are not required (see Figure 2 timing diagram). If the
update bit (U) is high, then the DAC output(s) will be updat-
ed on the rising edge of CS; otherwise, the new data byte
will be placed only in the input register. Chip Select (CS)
must remain low for at least one clock cycle after the last
data bit has been entered. (See Figures 1 and 2 )
When the U bit is set low an asynchronous update of all the
DAC outputs can be achieved by taking AU low. The con-
tents of the input registers are loaded into the DAC regis-
ters, with the update occurring on the falling edge of AU. CS
must be held high during an asynchronous update.
Table I lists the instruction set for the WRITE mode when
writing to only a single DAC, and Table II lists the instruction
set for a global write. Bits A0 and A1 select the DAC to be
written to. The DACs are always written to MSB first. All
DACs will be written to sequentially if the global bit (G) is
All DAC registers will have their contents reset to all zeros
on power up.
TABLE I. WRITE Mode Instruction Set (Writing to a Single DAC)
SB
RD/WR
G
U
A1
A0
Description
Ý
Ý
Ý
Ý
Ý
Ý
Bit 6
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Write DAC 1, no update of DAC outputs
Write DAC 2, no update of DAC outputs
Write DAC 3, no update of DAC outputs
Write DAC 4, no update of DAC outputs
Write DAC 1, update DAC 1 on CS rising edge
Write DAC 2, update DAC 2 on CS rising edge
Write DAC 3, update DAC 3 on CS rising edge
Write DAC 4, update DAC 4 on CS rising edge
0
0
0
0
0
0
0
TABLE II. WRITE Mode Instruction Set (Writing to all DACs)
SB
RD/WR
G
U
Description
Ý
Ý
Ý
Ý
Bit 4
Bit
1
Bit
2
Bit
3
1
0
1
1
0
1
Write all DACs, no update of outputs
1
0
Write all DACs, update all outputs on CS rising edge
10
Digital Interface (Continued)
Table III lists the instruction set for the READ mode. By the
appropriate setting of the global (G) and address (A1 and
A0) bits, one can select a specific DAC to be read, or one
can read all the DACs in succession, starting with DAC 1.
The R/F bit determines whether the data changes on the
rising or the falling edge of the system clock. With the R/F
bit high, DO goes out of TRI-STATE on the rising edge that
occurs 1(/2 clock cycles after the end of the instruction byte;
the data will continue to be sequentially clocked out by the
following rising clock edges. With the R/F bit low, DO goes
out of TRI-STATE on the falling edge that occurs 1 clock
cycle after the end of the instruction byte; the data will con-
tinue to be sequentially clocked by the next falling clock
edges. The rising edge of CS returns DO to TRI-STATE.
Read back with the R/F bit set high is not MICROWIRE
compatible. One can choose to read the data back MSB
first or LSB first by setting the M/L bit. (See Figures 3 and
4 )
TABLE III. READ MODE Instruction Set
M/L A1 A0
SB
RD/WR
G
R/F
Description
Ý
Ý
Ý
Ý
Ý
Ý
Ý
Bit 7
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
Read DAC 1, LSB first, data changes on the falling edge
Read DAC 2, LSB first, data changes on the falling edge
Read DAC 3, LSB first, data changes on the falling edge
Read DAC 4, LSB first, data changes on the falling edge
Read DAC 1, MSB first, data changes on the falling edge
Read DAC 2, MSB first, data changes on the falling edge
Read DAC 3, MSB first, data changes on the falling edge
Read DAC 4, MSB first, data changes on the falling edge
Read DAC 1, LSB first, data changes on the rising edge
Read DAC 2, LSB first, data changes on the rising edge
Read DAC 3, LSB first, data changes on the rising edge
Read DAC 4, LSB first, data changes on the rising edge
Read DAC 1, MSB first, data changes on the rising edge
Read DAC 2, MSB first, data changes on the rising edge
Read DAC 3, MSB first, data changes on the rising edge
Read DAC 4, MSB first, data changes on the rising edge
Read all DACs, LSB first, data changes on the falling edge
Read all DACs, MSB first, data changes on the falling edge
Read all DACs, LSB first, data changes on the rising edge
Read all DACs, MSB first, data changes on the rising edge
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
Power Fail Function
Power Supplies
a
The DAC1054 is designed to operate from a 5V (nominal)
supply. There are two supply lines, AV and DV . These
The DAC1054 powers up with the INT pin in a Low state. To
force this output high and reset this flag, the CS pin will have
to be brought low. When this is done the INT output will be
pulled high again via an external 10 kX pull-up resistor. Any-
CC CC
pins allow separate external bypass capacitors for the ana-
log and digital portions of the circuit. To guarantee accurate
conversions, the two supply lines should each be bypassed
with a 0.1 mF ceramic capacitor in parallel with a 10 mF
tantalum capacitor.
time a power failure occurs on the DV line, the INT will be
CC
set low when power is reapplied. This feature may be used
by the microprocessor to discard data whose integrity is in
question.
11
Typical Applications
TL/H/11437–18
FIGURE 7. Trimming the Offset of a 5V Op Amp Whose Output is Biased at 2.5V
TL/H/11437–19
FIGURE 8. Trimming the Offset of a Dual Supply Op Amp (V is Ground Referenced)
IN
TL/H/11437–20
FIGURE 9. Bringing the Output Range Down to Ground
12
Physical Dimensions inches (millimeters)
Order Number DAC1054CMJ/883 or 5962-9466201MJA
NS Package Number J24A
Order Number DAC1054CIWM
NS Package Number M24B
13
Ý
Lit. 02236
Physical Dimensions inches (millimeters) (Continued)
Order Number DAC1054CIN
NS Package Number N24A
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