COP87L88_技术文档

September 1999

COP87L88EB/RB Family

8-Bit CMOS OTP Microcontrollers with 16k or 32k

Memory, CAN Interface, 8-Bit A/D, and USART

Features include an 8-bit memory mapped architecture, 10

MHz CKI (-XE = crystal oscillator) with 1µs instruction cycle,

two multi-function 16-bit timer/counters, WATCHDOG and

clock monitor, idle timer, CAN 2.0B (passive) interface,

General Description

The COP87L88EB/RB Family OTP (One Time program-

™

mable) microcontrollers are highly integrated COP8 Fea-

ture core devices with 16k or 32k memory and advanced

features including a CAN 2.0B (passive) interface, A/D and

USART. These multi-chip CMOS devices are suited for appli-

cations requiring a full featured controller with a CAN inter-

face, low EMI, and versatile communications interfaces, and

as pre-production devices for ROM designs. Pin and soft-

ware compatible 8k ROM versions (COP888EB) are avail-

able as well as a range of COP8 software and hardware de-

velopment tools.

™

MICROWIRE/PLUS serial I/O, SPI master/slave interface,

fully buffered USART, 8 bit A/D with 8 channels, two power

saving HALT/IDLE modes, MIWU, software selectable I/O

options, low EMI 4.5V to 5.5V operation, program code se-

curity, and 44/68 pin packages.

Note: A companion device with CAN interface, less I/O and

memory, A/D, and PWM timer is the COP87L84BC.

Devices included in this datasheet are:

Device

Memory (bytes)

16k OTP EPROM

32k OTP EPROM

RAM (bytes)

I/O Pins

35

Packages

44 PLCC

68 PLCC

44 PLCC

68 PLCC

Temperature

-40 to +85˚C

COP87L88EB

COP87L89EB

COP87L88RB

COP87L89RB

192

58

35

58

Key Features

CPU/Instruction Set Features

n CAN 2.0B (passive) bus interface, with Software Power

save mode

n 1 µs instruction cycle time

n Fourteen multi-sourced vectored interrupts servicing

— External interrupt

— Idle Timer T0

n 8-bit A/D Converter with 8 channels

n Fully buffered USART

— Timers (T1 and T2) (4 Interrupts)

— MICROWIRE/PLUS and SPI

— Multi-input Wake up

— Software Trap

— CAN interface (3 interrupts)

— USART (2 Inputs)

n Multi-input wake up (MIWU) on both Port L and M

n SPI Compatible Master/Slave Interface

n 16 or 32 kbytes of on-board OTP EPROM with security

feature

Note: Mask ROMed device with equivalent on-chip features and program

memory size of 8k is available.

n Versatile easy to use instruction set

n 8-bit stacker pointer (SP) (Stack in RAM)

n Two 8-bit RegisterR Indirect Memory Pointers (B, X)

n 192 bytes of on-board RAM

Additional Peripheral Features

n Idle timer (programmable)

n Two 16-bit timer, with two 16-bit registers supporting

— Processor independent PWM mode

— External Event counter mode

— Input capture mode

Fully Static CMOS

n Two power saving modes: HALT, IDLE

n Single supply operation: 4.5V to 5.5V

n Temperature range: −40˚C to +85˚C

™

n WATCHDOG and Clock Monitor

n MICROWIRE/PLUS serial I/O

Development Support

n Emulation device for COP888EB

I/O Features

n Real time emulation and full program debug offered by

MetaLink Development System

n Software selectable I/O options (TRI-STATE^®outputs,

Push pull outputs, Weak pull up input, High impedance

input)

n Schmitt trigger inputs on Port G, L and M

n Packages: 44 PLCC with 35 I/O pins;

68 PLCC with 58 I/O pins

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

™

COP8 , MICROWIRE/PLUS , WATCHDOG and MICROWIRE are trademarks of National Semiconductor Corporation.

iceMASTER^®is a registered trademark of MetaLink Corporation.

DS100044

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— CAN Interface Wake-up (MSB)

— Timer 2 Input or Output (Depending on mode

selected)

n Port N—8-bit bidirectional I/O

— SPI Slave Select Expander

Basic Functional Description

n CAN I/F—CAN serial bus interface block as described

in the CAN specification part 2.0B (Passive)

— Interface rates up to 250k bit/s are supported utilizing

standard message identifiers

n Two 16-bit multi-function Timer counters (T1 and T2)

plus supporting registers

— (I/P Capture, PWM and Event Counting)

n Idle timer—Provides a basic time-base counter, (with

interrupt) and automatic wake up from IDLE mode

programmable

n MICROWIRE/PLUS—MICROWIRE serial peripheral

interface, supporting both Master and Slave operation

n HALT and IDLE—Software programmable low current

modes

— HALT—Processor stopped, Minimum current

— IDLE—Processor semi-active more than 60% power

saving

n Programmable double buffered USART

n A/D—8-bit, 8 channel, 1-LSB Resolution, with improved

Source Impedance and improved channel to channel

cross talk immunity

n Multi-Input-Wake-Up (MIWU)—edge selectable wake-up

and interrupt capability via input port and CAN interface

(Port L, Port M and CAN I/F); supports Wake-Up

capability on SPI, USART, and T2

n Port C—8-bit bi-directional I/O port

n Port D—8-bit Output port with high current drive

capability (10 mA)

n Port F—8-bit bidirectional I/O

n Port G—8-bit bidirectional I/O port, including alternate

functions for:

n 16 or 32 kbytes OTP EPROM and 192 bytes of on

board static RAM

n SPI Master/Slave interface includes 12 bytes Transmit

and 12 bytes Receive FIFO Buffers. Operates up to 1M

Bit/S

™

— MICROWIRE Input and Output

— Timer 1 Input or Output (Depending on mode

selected)

— External Interrupt input

n On board programmable WATCHDOG and CLOCK

Monitor

— WATCHDOG Output

n Port I—8-bit input port combining either digital input, or

up to eight A/D input channels

n Port L—8-bit bidirectional I/O port, including alternate

functions for:

— USART Transmit/Receive I/O

— Multi-input-wake up (MIWU on all pins)

n Port M—8-bit I/O port, with the following alternate

function

Applications

n Automobile Body Control and Comfort System

n Integrated Driver Informaiton Systems

n Steering Wheel Control

n Car Radio Control Panel

n Sensor/Actuator Applications in Automotive and

Industrial Control

— SPI Interface

— MIWU

Block Diagram

DS100044-1

FIGURE 1. Block Diagram

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2

Connection Diagrams

Plastic Chip Carrier

DS100044-2

Top View

Order Number COP87L88EBV-XE or COP87L88RBV-XE

See NS Plastic Chip Package Number V44A

Plastic Leaded Chip Carrier

DS100044-3

Note:

-X Crystal Oscillator

-E Halt Mode Enabled

Top View

Order Number COP87L89EBV-XE or COP87L89RBV-XE

See NS Plastic Chip Package Number V68A

FIGURE 2. Connection Diagrams

3

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Connection Diagrams (Continued)

Port

Type

ALT

44-Pin

PLCC

68-Pin

PLCC

10

Function

Pinouts for 44-Pin and 68-Pin Packages

F0

I/O

I

Port

Type

ALT

44-Pin

68-Pin

PLCC

1

F1

11

Function

PLCC

44

1

F2

12

G0

I/O

I

INT

F3

13

G1

G2

G3

G4

G5

G6

G7

D0

D1

D2

D3

D4

D5

D6

D7

I0

WDOUT

T1B

T1A

SO

2

F4

14

2

3

C0

35

3

4

C1

36

4

5

C2

37

SK

5

6

RX0

RX1

TX0

TX1

CANV_REF

CKI

31

30

48

SI

6

7

I

47

I

CKO

7

8

O

29

46

O

17

18

19

20

27

28

29

30

31

32

33

34

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

38

39

40

41

42

43

44

18

19

20

21

22

23

24

25

O

28

45

O

32

49

O

8

9

O

RESET

DV_CC

GND

16

26

O

10, 33

9, 11, 34

16, 50

O

15, 17,

51

O

A/D

V_REF

35

52

I

ADCH0

ADCH1

ADCH2

ADCH3

ADCH4

ADCH5

ADCH6

ADCH7

MIWU

36

37

38

39

I1

I

I2

I

I3

I

I4

I

I5

I

I6

I

I7

I

L0

L1

L2

L3

L4

L5

L6

L7

M0

M1

M2

M3

M4

M5

M6

N0

N1

N2

N3

N4

N5

N6

N7

I/O

40

41

42

43

MIWU;CKX

MIWU;TDX

MIWU;RDX

MIWU

MIWU;MISO

MIWU;MOSI

MIWU;SCK

MIWU;SS

MIWU;T2A

MIWU;T2B

MIWU

21

22

23

24

25

26

27

12

13

14

15

ESS0

ESS1

ESS2

ESS3

ESS4

ESS5

ESS6

ESS7

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4

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Total Current into V_CCPins (Source)

Total Current out of GND Pins (Sink)

Storage Temperature Range

Note 1: Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

90 mA

100 mA

−65˚C to +150˚C

Supply Voltage (V_CC

Voltage at Any Pin

)

6V

−0.3V to V_CC+0.3V

DC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C

Parameter

Conditions

Min

Typ

Max

5.5

Units

V

Operating Voltage

4.5

Power Supply Ripple (Note 2)

Supply Current

Peak-to-Peak

0.1 V_CC

16

V

V_CC= 5.5V, t_c= 1 µs

mA

CKI = 10 MHz (Note 3)

HALT Current (Notes 4, 5)

IDLE Current (Note 5)

CKI = 10 MHz

<

V_CC= 5.5V, CKI = 0 MHz

V_CC= 5.5V, t_c= 1 µs

1

µA

5.5

mA

Input Levels (V_IH, V_IL)

Reset, CKI

Logic High

0.8V_CC

0.7V_CC

−40

V

Logic Low

0.2V_CC

All Other Inputs

Logic High

V

Logic Low

±

Hi-Z Input Leakage

Input Pull-Up Current

Port G, L and M Input Hysteresis

Output Current Levels

D Outputs

V_CC= 5.5V

2

µA

V

V_CC= 5.5V, V_IN= 0V

(Note 8)

−250

0.05V_CC

Source

V_CC= 4.5V, V_OH= 3.3V

V_CC= 4.5V, V_OL= 1.0V

−0.4

10

mA

Sink

CAN Transmitter Outputs

Source (Tx1)

V_CC= 4.5V, V_OH= V_CC−0.1V

V_CC= 4.5V, V_OH= V_CC− 0.6V

V_CC= 4.5V, V_OL= 0.1V

−1.5

−10

1.5

mA

+5.0

Sink (Tx0)

V_CC= 4.5V, V_OL= 0.6V

10

All Others

Source (Weak Pull-Up)

Source (Push-Pull)

V_CC= 4.5V, V_OH= 2.7V

V_CC= 4.5V, V_OH= 3.3V

V_CC= 4.5V, V_OL= 0.4V

V_CC= 5.5V

−10

−0.4

1.6

−110

µA

mA

µA

Sink (Push-Pull)

±

TRI-STATE Leakage

Allowable Sink/Source Current per Pin

D Outputs (sink)

2.0

15

30

3

mA

Tx0 (Sink) (Note 8)

Tx1 (Source) (Note 8)

All Other

±

Maximum Input Current

without Latchup (Notes 6, 8)

RAM Retention Voltage, V_r(Note 7)

Input Capacitance

Room Temp

200

500 ns Rise and Fall Time

(Note 8)

2.0

V

7

pF

Load Capacitance on D2

1000

<

Note 2: Maxiumum rate of voltage change must be 0.5V/ms

5

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DC Electrical Characteristics (Continued)

Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V

or GND, and outputs open.

CC

Note 4: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to V ; Port C, G, E, F, L, M and N I/Os con-

CC

figured as outputs and programmed low; D outputs programmed high. Parameter refers to HALT mode entered via setting bit 7 of the Port G data register. Part will

pull up CKI during HALT in crystal clock mode. Both CAN main comparator and the CAN Wakeup comparator need to be disabled.

Note 5: . HALT and IDLE current specifications assume CAN block comparators are disabled.

Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than V

and the pins will have sink current

CC

to V when biased at voltages greater than V (the pins do not have source current when biased at a voltage below V ). The effective resistance to V is 750Ω

CC

(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

Note 7: Condition and parameter valid only for part in HALT mode.

Note 8: Parameter characterized but not tested.

AC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C

Parameter

Instruction Cycle Time (t_c)

Crystal/Resonator

Inputs

Conditions

Min

Typ

Max

Units

V_CC≥ 4.5V

1.0

DC

µs

t_SETUP

V_CC≥ 4.5V

200

60

ns

t_HOLD

V_CC≥ 4.5V

Output Propagation Delay (t_PD1, t_PD0) (Note 9)

SK, SO

C_L= 100 pF, R_L= 2.2 kΩ

V_CC≥ 4.5V

0.7

1

µs

All others

V_CC≥ 4.5V

MICROWIRE

Setup Time (tUWS) (Note 10)

Hold Time (tUWH) (Note 10)

Output Pop Delay (tUPD)

Input Pulse Width

20

56

ns

220

Interrupt High Time

Interrupt Low Time

Timer 1, 2 High Time

Timer 1, 2 Low Time

Reset Pulse Width (Note 10)

1

t_c

1

t_c

1

t_c

1.0

µs

t

= Instruction Cycle Time

c

The maximum bus speed achievable with the CAN interface is a function of crystal frequency, message length and software overhead. The device can support a bus

speed of up to 1 Mbit/S with a 10 MHz oscillator and 2 byte messages. The 1M bus speed refers to the rate at which protocol and data bits are transferred on the

bus. Longer messages require slower bus speeds due to the time required for software intervention between data bytes. The device will support a maximum of 125k

bits/s with eight byte messages and a 10 MHz oscillator.

For device testing purpose of all AC parameters, V

will be tested at 0.5*V

.

CC

OH

Note 9: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 10: Parameter not tested.

On-Chip Voltage Reference

−40˚C ≤ T_A≤ +85˚C

Parameter

Reference Voltage

V_REF

Conditions

Min

Max

Units

<

I_OUT80 µA,

0.5V_CC−0.12

0.5V_CC+0.12

V

V_CC= 5V

Reference Supply

Current, I_DD

I_OUT= 0A, (No Load)

V_CC= 5V (Note 11)

120

µA

Note 11: Reference supply I

is supplied for information purposes only, it is not tested.

DD

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6

CAN Comparator DC and AC Characteristics

4.8V ≤ V_CC≤ 5.2V, −40˚C ≤ T_A≤ +85˚C

Parameter

Differential Input Voltage

Input Offset Voltage

Input Common Mode

Voltage Range

Conditions

Min

Typ

Max

Units

mV

V

±

25

10

<

1.5V V_INV_CC−1.5V

1.5

8

V_CC−1.5

Input Hysteresis

mV

A/D Converter Specifications

(4.5V ≤ V_CC≤ 5.5V) (V_SS− 0.050V) ≤ Any Input ≤ (V_CC+ 0.050V)

Parameter Conditions

Min

Typ

Max

Units

Resolution

8

Bits

LSB

±

Absolute Accuracy

Non-Linearity

V_REF= V_CC

2

1

±

Deviation from the Best Straight Line

Differential Non-Linearity

±

1

LSB

Common Mode Input Range (Note 14)

DC Common Mode Error

GND

0.1

V_CC

V

±

0.5

LSB

Off Channel Leakage Current

1

2.0

µA

On Channel Leakage Current

2.0

µA

A/D Clock Frequency (Note 13)

Conversion Time (Note 12)

1.67

MHz

A/D Clock Cycles

µs

17

Internal Reference Resistance Turn-On Time (Note 15)

1

Note 12: Conversion Time includes sample and hold time.

Note 13: See Prescaler description.

Note 14: For V (−) = V (+) the digital output code will be 0000 0000. Two on-chip doides are ties to each analog input. The diodes will forward conduct for analog

IN

input voltages below ground or above the V supply. Be careful, during testing at low V levels (4.5V), as high level analog inputs (5V) can cause this input diode

CC

to conduct — especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means

that as long as the analog V does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V to 5 V input

IN

DC

voltage range will therefore require a minimum supply voltage of 4.950 V

over temperature variations, initial tolerance and loading.

DC

Note 15: Time for internal reference resistance to turn on after coming out of Halt or Idle Mode.

DS100044-5

DS100044-4

FIGURE 4. SPI Timing Diagram

FIGURE 3. MICROWIRE/PLUS Timing Diagram

7

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Typical Performance Characteristics (−55˚C ≤ T_A= +125˚C)

DS100044-57

DS100044-58

DS100044-59

DS100044-60

DS100044-61

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8

Pin Description

V_CCand GND are the power supply pins.

Port G is an 8-bit port with 5 I/O pins (G0–G5), an input pin

(G6), and one dedicated output pin (G7). Pins G0–G6 all

have Schmitt Triggers on their inputs. G7 serves as the dedi-

cated output pin for the CKO clock output. There are two reg-

isters associated with the G Port, a data register and a con-

figuration register. Therefore, each of the 6 I/O bits (G0–G5)

can be individually configured under software control.

CKI is the clock input. The clock can come from a crystal os-

cillator (in conjunction with CKO). See Oscillator Description

section.

RESET is the master reset input. See Reset Description sec-

tion.

The device contains seven bidirectional 8-bit I/O ports (C, E,

F, G, L, M, N) where each individual bit may be indepen-

dently configured as an input (Schmitt trigger inputs on all

ports), output or TRI-STATE under program control. Three

data memory address locations are allocated for each of

these I/O ports. Each I/O port has two associated 8-bit

memory mapped registers, the CONFIGURATION register

and the output DATA register. A memory mapped address is

also reserved for the input pins of each I/O port. (See the

memory map for the various addresses associated with the

I/O ports.) Figure 5 shows the I/O port configurations for the

device. The DATA and CONFIGURATION registers allow for

each port bit to be individually configured under software

control as shown below:

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin the associated bits in the data and configu-

ration registers for G6 and G7 are used for special purpose

functions as outlined below. Reading the G6 and G7 data

bits will return zeroes.

Note that the chip will be placed in the HALT mode by wirting

a ’’1” to bit 7 of the Port G Data Register. Similarly the chip

will be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

phase of the SK clock

Config. Reg.

CLKDLY

Data Reg.

HALT

Configuration

Data

Register

0

Port Set-Up

G7

G6

Register

Alternate SK

IDLE

0

Hi-Z Input

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

0

1

0

1

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer I/O)

Port L and M are 8-bit I/O ports, they support Multi-Input

Wake-up (MIWU) on all eight pins. All L-pins and M-pins

have Schmitt triggers on the inputs.

G2 (Timer T1 Capture Input)

G1 Dedicated WATCHDOG output

G0 INTR (External Interrupt Input)

Port G has the following dedicated function:

G7 CKO Oscillator dedicated output

Port L and M only have one (1) interrupt vector.

Port M is a bidirectional I/O, it may be configured in software

as Hi-Z input, weak pull-up, or push-pull output. These pins

may be used as general purpose input/output pins or for se-

lected altlernate functions.

Port M pins have optional alternate functions. Each pin

(M0–M5) has been assigned an alternate data, configura-

tion, or wakeup source. If the respective alternate function is

selected the content of the associated bits in the configura-

tion and/or data register are ignored. If an alternate wakeup

source is selected the input level at the respective pin will be

ignored for the purpose of triggering a wakeup event, how-

ever it will still be possible to read that pin by accessing the

input register. The SPI (Serial Peripheral Interface) block, for

example, uses four of the Port M pins to automatically re-

configure its MISO (Master Input, Slave Output), MOSI

(Master Output, Slave Input), SCK (Serial Clock) and Slave-

Select pins as inputs or outputs, depending on whether the

interface has been configured as a Master or Slave. When

the SPI interface is disabled those pins are available as gen-

eral purpose I/O pins configurable by user software writing to

the associated data and configuration bits. The CAN inter-

face on the device makes use of one of the Port M’s alter-

nate wake-ups, to trigger a wakeup if such a condition has

been detected on the CAN’s dedicated receive pins.

DS100044-6

FIGURE 5. I/O Port Configurations

Port L has the following alternate features:

L7 MIWU

L6 MIWU

L5 MIWU

L4 MIWU

L3 MIWU or RDX

L2 MIWU or TDX

L1 MIWU or CKX

L0 MIWU

Port M has the following alternate pin functions:

M7 Multi-input Wakeup or CAN

M6 Multi-input Wakeup

M5 Multi-input Wakeup or T2B

9

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Port I is an 8-bit Hi-Z input port, and also provides the analog

inputs to the A/D converter. If unterminated, Port I pins will

draw power only when addressed.

Pin Description (Continued)

M4 Multi-input Wakeup or T2A

M3 Multi-input Wakeup or SS

M2 Multi-input Wakeup or SCK

M1 Multi-input Wakeup or MOSI

M0 Multi-input Wakeup or MISO

Functional Description

The architecture of the device utilizes a modified Harvard ar-

chitecture. With the Harvard architecture, the control store

program memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The ar-

chitecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

Ports C, E, F and N are general-purpose, bidirectional I/O

ports.

Any device package that has Port C, E, F, M, N but has fewer

than eight pins, contains unbonded, floating pads internally

on the chip. For these types of devices, the software should

write a 1 to the configuration register bits corresponding to

the non-existent port pins. This configures the port bits as

outputs, thereby reducing leakage current of the device.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t_c) cycle time.

Port N is an 8-bit wide port with alternate function capability

used for extending the slave select (SS) lines of the on SPI

interface. The SPI expander block provides mutually exclu-

sive slave select extension signals (ESS0 to ESS7) accord-

ing to the state of the SS line and specific contents of the SPI

shift register. These slave select extension lines can be

routed to the Port N I/O pins by enabling the alternate func-

tion of the port in the PORTNX register. If enabled, the inter-

nal signal on the ESSx line causes the ports state to change

exactly like a change to the PORTND register. It is the user’s

responsibility to switch the port to an output when enabling

the alternate function.

There are five CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). The SP is initialized to RAM ad-

dress 02F with reset.

Port N has the following alternate pin functions:

N7 ESS7

N6 ESS6

N5 ESS5

N4 ESS4

N3 ESS3

N2 ESS2

N1 ESS1

N0 ESS0

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

Program memory for the device consists of 8 or 32 kbytes of

OTP EPROM. These bytes may hold program instructions or

constant data (data tables for the LAID instruction, jump vec-

tors for the JID instruction and interrupt vectors for the VIS

instruction). The program memory is addressed by the 15-bit

program counter (PC). All interrupts in the device vector to

program memory location 0FF Hex.

CAN pins: For the on-chip CAN interface this device has five

dedicated pins with the following features:

V_REF

Rx0

RX1

Tx0

On-chip reference voltage with the value of V_CC/2

CAN receive data input pin.

The device can be configured to inhibit external reads of the

program memory. This is done by programming the Security

Byte.

CAN receive data input pin.

CAN transmit data output pin. This pin may be put in

the TRI-STATE mode with the TXEN0 bit in the CAN

Bus control register.

SECURITY FEATURE

The program memory array has an associate Security Byte

that is located outside of the program address range. This

byte can be addressed only from programming mode by a

programmer tool.

Tx1

CAN transmit data output pin. This pin may be put in

the TRI-STATE mode with the TXEN1 bit in the CAN

Bus control register.

Security is an optional feature and can only be asserted after

the memory array has been programmed and verified. A se-

cured part will read all 00(hex) by a programmer. The part

will fail Blank Check and will fail Verify operations. A Read

operation will fill the programmer’s memory with 00(hex).

The Security byte itself is always readable with value of

00(hex) if unsecure and FF(hex) if secure.

ALTERNATE PORT FUNCTIONS

Many general-purpose pins have alternate functions. The

software can program each pin to be used either for a

general-purpose or for a specific function. The chip hardware

determines which of the pins have alternate functions, and

what those functions are. This section lists the alternate

functions available on each of the pins.

DATA MEMORY

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more port D outputs (ex-

cept D2) together in order to get a higher drive.

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

register, and the various registers, and counters associated

Note: Care must be exercised with D2 pin operation. At RESET, the external

loads on this pin must ensure that the output voltages stay above 0.8

V

to prevent the chip from entering special modes. Also keep the ex-

CC

<

ternal loading on D2 to 1000 pF.

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10

“error-active” state and waits until the user’s software

sets either one or both of the TXEN0, TXEN1 bits to

“1”. After that, the device will not start transmission or

reception of a frame util eleven consecutive “reces-

sive” (undriven) bits have been received. This is done

to ensure that the output drivers are not enamble dur-

ing an active message on the bus.

Functional Description (Continued)

with the timers (with the exception of the IDLE timer). Data

memory is addressed directly by the instruction or indirectly

by the B, X and SP pointers.

The device has 192 bytes of RAM. Sixteen bytes of RAM are

mapped as “registers” at addresses 0F0 to 0FF Hex. These

registers can be loaded immediately, and also decremented

and tested with the DRSZ (decrement register and skip if

zero) instruction. The memory pointer registers X, SP, and B

are memory mapped into this space at address locations

0FC to 0FE Hex respectively, with the other registers (other

than reserved register 0FF) being available for general us-

age.

CSCAL, CTIM, TCNTL, TEC, REC: CLEARED

RTSTAT: CLEARED with the exception of the TBE bit which

is set to 1

RID, RIDL, TID, TDLC: RANDOM

WATCHDOG: The device comes out of reset with both the

WATCHDOG logic and the Clock Monitor

detector armed, with the WATCHDOG ser-

vice window bits set and the Clock Monitor

bit set. The WATCHDOG and Clock Monitor

circuits are inhibited during reset. The

WATCHDOG service window bits being ini-

tialized high default to the maximum

WATCHDOG service window of 64k t_cclock

cycles. The Clock Monitor bit being initial-

ized high will cause a Clock Monitor bit be-

ing initialized high will cause a Clock Moni-

tor error following reset if the clock has not

reached the minimum specified frequency

at the termination of reset. A Clock Monitor

error will cause an active low error output on

pin G1. This error output will continue until

16 t_c–32 t_cclock cycles following the clock

frequency reaching the minimum specified

value, at which time the G1 output will enter

the TRI-STATE mode.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore I/O bits and register bits can be

directly and individually set, reset and tested. The accumula-

tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

RESET

The RESET input when pulled low initializes the microcon-

troller. Initialization will occur whenever the RESET input is

pulled low. Upon initialization, the data and configuration

registers for Ports L and G, are cleared, resulting in these

Ports being initialized to the TRI-STATE mode. Port D is ini-

tialized high with RESET. The PC, CNTRL, and INCTRL

control registers are cleared. The Multi-Input Wakeup regis-

ters WKEN, WKEDG, and WKPND are cleared. The Stack

Pointer, SP, is initialized to 06F Hex.

The following initializations occur with RESET:

SPI:

The RESET signal goes directly to the

HALT latch to restart a halted chip.

SPICNTRL: Cleared

When using external reset, the external RC network shown

in Figure 6 should be used to ensure that the RESET pin is

held low until the power supply to the chip stabilizes. Under

no circumstances should the RESET pin be allowed to float.

SPISTAT: Cleared

STBE Bit: Set

T1CNTRL & T2CNTRL: Cleared

ITMR: Cleared and IDLE timer period is reset to 4k Instr.

CLK

ENAD: Cleared

ADDSLT: Random

SIOR: Unaffected after RESET with power already ap-

plied.

Random after RESET at power on.

Port L: TRI-STATE

Port G: TRI-STATE

DS100044-7

RC 5 x Power Supply Rise Time

Port D: HIGH

PC: CLEARED

FIGURE 6. Recommended Reset Circuit

PSW, CNTRL and ICNTRL registers: CLEARED

Accumulator and Timer 1:

RANDOM after RESET with power already applied

RANDOM after RESET at power-on

SP (Stack Pointer): Loaded with 6F Hex

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-up

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-up

CAN: The CAN Interface comes out of external reset in the

11

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PSW Register (Address X'00EF)

Oscillator Circuits

HC

C

T1PNDA T1ENA EXPND BUSY EXEN GIE

Bit 0

The chip can be driven by a clock input on the CKI input pin

which can be between DC and 10 MHz. The CKO output

clock is on pin G7. The CKI input frequency is divided by 10

to produce the instruction cycle clock (1/t_c).

Bit 7

The PSW register contains the following select bits:

HC

C

Half Carry Flag

Carry Flag

Figure 7 shows the Crystal diagram.

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload

RA in mode 1, T1 Underflow in Mode 2, T1A

capture edge in mode 3)

CRYSTAL OSCILLATOR

CKI and CKO can be connected to make a closed loop crys-

tal (or resonator) controlled oscillator.

T1ENA

Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

EXPND External interrupt pending

BUSY

EXEN

GIE

MICROWIRE/PLUS busy shifting flag

Enable external interrupt

Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that

affect the Carry flag. The SC (Set Carry) and R/C (Reset

Carry) instructions will respectively set or clear both the carry

flags. In addition to the SC and R/C instructions, ADC,

SUBC, RRC and RLC instructions affect the Carry and Half

Carry flags.

DS100044-8

FIGURE 7. Crystal Oscillator Diagram

ICNTRL Register (Address X'00E8)

Table 1 shows the component values required for various

standard crystal values.

Reserved

Bit 7

LPEN

T0PND

T0EN µWPND µWEN T1PNDB

T1ENB

Bit 0

The ICNTRL register contains the following bits:

Reserved This bit is reserved and should be zero

TABLE 1. Crystal Oscillator Configuration, T_A= 25˚C

LPEN

L Port Interrupt Enable (Multi-Input Wakeup/

Interrupt)

R1

R2

C1

C2

CKI Freq. Conditions

(MHz)

(kΩ) (MΩ) (pF)

(pF)

T0PND Timer T0 Interrupt pending

0

1

30

30–36

10

4

V_CC= 5V

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

µWPND MICROWIRE/PLUS interrupt pending

µWEN Enable MICROWIRE/PLUS interrupt

200 100–150

0.455

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture

edge

Control Registers

T1ENB Timer T1 Interrupt Enable for T1B Input capture

edge

CNTRL Register (Address X'00EE)

T1C3

Bit 7

T1C2

T1C1

T1C0 MSEL

IEDG

SL1

SL0

Bit 0

T2CNTRL Register (Address X'00C6)

The Timer1 (T1) and MICROWIRE/PLUS control register

contains the following bits:

T2C3

Bit 7

T2C2

T2C1

T2C0

T2PNDA

T2ENA

T2PNDB

T2ENB

Bit 0

T1C3

T1C2

T1C1

T1C0

Timer T1 mode control bit

Timer T1 Start/Stop control in timer

The T2CNTRL control register contains the following bits:

T2C3

T2C2

T2C1

T2C0

Timer T2 mode control bit

modes 1 and 2, T1 Underflow Interrupt

Pending Flag in timer mode 3

Timer T2 Start/Stop control in timer

modes 1 and 2, T2 Underflow Interrupt Pend-

ing Flag in timer mode 3

MSEL

IEDG

Selects G5 and G4 as MICROWIRE/PLUS

signals SK and SO respectively

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload

RA in mode 1, T2 Underflow in mode 2, T2A

capture edge in mode 3)

External interrupt edge polarity select

(0 = Rising edge, 1 = Falling edge)

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

by (00 = 2, 01 = 4, 1x = 8)

T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

T2ENB

Timer T2 Interrupt Enable for Timer Underflow

or T2B Input capture edge

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12

Figure 8 is a functional block diagram showing the structure

of the IDLE Timer and its associated interrupt logic.

Timers

The device contains a very versatile set of timers (T0, T1 and

T2). All timers and associated autoreload/capture registers

power up containing random data.

Bits 11 through 15 of the ITMR register can be selected for

triggering the IDLE Timer interrupt. Each time the selected

bit underflows (every 4k, 8k, 16k, 32k or 64k instruction

cycles), the IDLE Timer interrupt pending bit T0PND is set,

thus generating an interrupt (if enabled), and bit 6 of the Port

G data register is reset, thus causing an exit from the IDLE

mode if the device is in that mode.

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE timer T0, which is a

16-bit timer. The Timer T0 runs continuously at the fixed rate

of the instruction cycle clock, t_c. The user cannot read or

write to the IDLE Timer T0, which is a count down timer.

In order for an interrupt to be generated, the IDLE Timer in-

terrupt enable bit T0EN must be set, and the GIE (Global In-

terrupt Enable) bit must also be set. The T0PND flag and

T0EN bit are bits 5 and 4 of the ICNTRL register, respec-

tively. The interrupt can be used for any purpose. Typically, it

is used to perform a task upon exit from the IDLE mode. For

more information on the IDLE mode, refer to the Power Save

Modes section.

The Timer T0 supports the following functions:

•

Exit out of the Idle Mode (See Idle Mode description)

WATCHDOG logic (See WATCHDOG description)

Start up delay out of the HALT mode

DS100044-9

FIGURE 8. Functional Block Diagram for Idle Timer T0

The Idle Timer period is selected by bits 0–2 of the ITMR

register Bits 3–7 of the ITMR Register are reserved and

should not be used as software flags.

TIMER T1 and TIMER T2

The device has a set of three powerful timer/counter blocks,

T1 and T2. The associated features and functioning of a

timer block are described by referring to the timer block Tx.

Since the three timer blocks, T1 and T2 are identical, all

comments are equally applicable to either of the three timer

blocks.

ITMR Register (Address X’0xCF)

Reserved

ITSEL2 ITSEL1 ITSLE0

Bit 0

Bit 7

Each timer block consists of a 16-bit timer, Tx, and two sup-

porting 16-bit autoreload/capture registers, RxA and RxB.

Each timer block has two pins associated with it, TxA and

TxB. The pin TxA supports I/O required by the timer block,

while the pin TxB is an input to the timer block. The powerful

and flexible timer block allows the device to easily perform all

timer functions with minimal software overhead. The timer

block has three operating modes: Processor Independent

PWM mode, External Event Counter mode, and Input Cap-

ture mode.

TABLE 2. Idle Timer Window Length

ITSEL2

ITSEL1

ITSEL0

Idle Timer Period

(Instruction Cycles)

4,096

0

1

0

1

X

0

1

0

1

X

8,192

16,384

32,768

The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

65,536

Mode 1. Processor Independent PWM Mode

The ITMR register is cleared on Reset and the Idle Timer pe-

riod is reset to 4,096 instruction cycles.

As the name suggests, this mode allows the device to gen-

erate a PWM signal with very minimal user intervention.

Any time the IDLE Timer period is changed there is the pos-

sibility of generating a spurious IDLE Timer interrupt by set-

ting the T0PND bit. The user is advised to disable IDLE

Timer interrupts prior to changing the value of the ITSEL bits

of the ITMR Register and then clear the T0PND bit before at-

tempting to synchronize operation to the IDLE Timer.

The user only has to define the parameters of the PWM sig-

nal (ON time and OFF time). Once begun, the timer block will

continuously generate the PWM signal completely indepen-

13

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TxA pin. Underflows from the timer are latched into the TxP-

NDA pending flag. Setting the TxENA control flag will cause

an interrupt when the timer underflows.

Timers (Continued)

dent of the microcontroller. The user software services the

timer block only when the PWM parameters require updat-

ing.

In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB con-

trol flag is set. The occurrence of the positive edge on the

TxB input pin is latched to the TxPNDB flag.

In this mode the timer Tx counts down at a fixed rate of t_c.

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, RxA and RxB. The very

first underflow of the timer causes the timer to reload from

the register RxA. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

register RxB.

Figure 10 shows a block diagram of the timer in External

Event Counter mode.

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the

timer for PWM mode operation.

Figure 9 shows a block diagram of the timer in PWM mode.

DS100044-11

Note: The PWM output is not available in this mode since the TxA pin is

being used as the counter input clock.

FIGURE 10. Timer in External Event Counter Mode

Mode 3. Input Capture Mode

The device can precisely measure external frequencies or

time external events by placing the timer block, Tx, in the in-

put capture mode.

DS100044-10

FIGURE 9. Timer in PWM Mode

In this mode, the timer Tx is constantly running at the fixed t_c

rate. The two registers, RxA and RxB, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

RxA acts in conjunction with the TxA pin and the register RxB

acts in conjunction with the TxB pin.

The underflows can be programmed to toggle the TxA output

pin. The underflows can also be programmed to generate in-

terrupts.

Underflows from the timer are alternately latched into two

pending flags, TxPNDA and TxPNDB. The user must reset

these pending flags under software control. Two control en-

able flags, TxENA and TxENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag TxENA will cause an interrupt when a timer un-

derflow causes the RxA register to be reloaded into the timer.

Setting the timer enable flag TxENB will cause an interrupt

when a timer underflow causes the RxB register to be re-

loaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

TxC3, TxC2 and TxC1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger con-

dition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively latched into the

pending flags, TxPNDA and TxPNDB. The control flag

TxENA allows the interrupt on TxA to be either enabled or

disabled. Setting the TxENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

TxA pin. Similarly, the flag TxENB controls the interrupts

from the TxB pin.

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the TxC0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the TxENA control flag. When a TxA interrupt

occurs in the Input Capture mode, the user must check both

whether a TxA input capture or a timer underflow (or both)

caused the interrupt.

Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin. The

Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to

be clocked either on a positive or negative edge from the

Figure 11 shows a block diagram of the timer in Input Cap-

ture mode.

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14

Timers (Continued)

DS100044-12

FIGURE 11. Timer in Input Capture Mode

TxPNDA Timer Interrupt Pending Flag

TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

TxC3

TxC2

TxC1

TxC0

Timer mode control

TxPNDB Timer Interrupt Pending Flag

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

TxENB

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

Timer Underflow Interrupt Pending Flag in

Mode 3 (Input Capture)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

Interrupt A

Source

Interrupt B

Source

Timer

Mode

TxC3

TxC2

TxC1

Description

Counts On

1

0

1

0

PWM: TxA Toggle

Autoreload RA

Autoreload RB

t_C

1

PWM: No TxA

Toggle

t_C

0

1

0

1

0

External Event

Counter

Timer

Underflow

Pos. TxB Edge

Pos. TxA

Edge

2

External Event

Counter

Timer

Underflow

Pos. TxA

Edge

Captures:

Pos. TxA Edge

or Timer

t_C

TxA Pos. Edge

TxB Pos. Edge

Captures:

Underflow

1

0

1

0

1

Pos. TxA

Neg. TxB

Edge

TxA Pos. Edge

TxB Neg. Edge

Captures:

Edge or Timer

Underflow

3

Neg. TxA

Neg. TxB

Edge

TxA Neg. Edge

TxB Neg. Edge

Captures:

Edge or Timer

Underflow

Neg. TxA

Neg. TxB

Edge

TxA Neg. Edge

TxB Neg. Edge

Edge or Timer

Underflow

15

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In order to reduce the device overall current consumption

in HALT/IDLE mode a two step power save mechanism is

implemented on the device:

Power Save Modes

The device offer the user two power save modes of opera-

tion: HALT and IDLE. In the HALT mode, all microcontrol-

ler activities are stopped. In the IDLE mode, the on-board

oscillator circuitry and timer T0 are active but all other mi-

crocontroller activities are stopped. In either mode, all on-

board RAM, registers, I/O states, and timers (with the ex-

ception of T0) are unaltered.

Step 1: Disable main receive comparator. This is done

by resetting both the TxEN0 and TxEN1 bits in

the CBUS register. Note: These bits should al-

ways be reset before entering HALT/IDLE mode

to allow proper resynchronization to the CAN

bus after exiting HALT/IDLE mode.

Step 2: Disable the CAN wake-up comparators, this is

done by resetting bit 7 in the port-m wakeup en-

able register (MWKEN) a transition on the CAN

bus will then not wake the device up.

HALT MODE

The device is placed in the HALT mode by writing a ’’1” to

the HALT flag (G7 data bit). All microcontroller activities,

including the clock, and timers, are stopped. In the HALT

mode, the power requirements of the device are minimal

and the applied voltage (V_CC) may be decreased to Vr

(Vr = 2.0V) without altering the state of the machine.

Note: If both the main receive comparator and the wake-up comparator

are disabled the on chip CAN voltage reference is also disabled.

The CAN-V

output is then High-Z

REF

CAN HALT/IDLE mode:

The following table shows the two CAN power save modes and the active CAN transceiver blocks:

Step 1

Step 2

Main-Comp

Wake-Up-Comp

CAN-V_REF

V_REFPin

0

1

0

1

0

1

on

off

on

off

on

off

on

off

V

_CC/2

High-Z

The device supports two different ways of exiting the HALT

mode. The first method of exiting the HALT mode is with the

Multi-Input Wakeup feature on the L & M port. The second

method of exiting the HALT mode is by pulling the RESET

pin low.

As with the HALT mode, the device can be returned to nor-

mal operation with a reset, or with a Multi-Input Wakeup from

the Port L or CAN Interface. Alternately, the microcontroller

resumes normal operation from the IDLE mode when the

thirteenth bit (representing 4.096 ms at internal clock fre-

quency of 1 MHz, t_c= 1 µs) of the IDLE Timer toggles.

Since a crystal or ceramic resonator may be selected as the

oscillator, the Wakeup signal is not allowed to start the chip

running immediately since crystal oscillators and ceramic

resonators have a delayed start up time to reach full ampli-

tude and frequency stability. The IDLE timer is used to gen-

erate a fixed delay to ensure that the oscillator has indeed

stabilized before allowing instruction execution. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry is enabled. The IDLE timer is loaded with a value of

256 and is clocked with the t_cinstruction cycle clock. The t_c

clock is derived by dividing the oscillator clock down by a fac-

tor of 10. The Schmitt trigger following the CKI inverter on

the chip ensures that the IDLE timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specifications. This Schmitt trigger is not part

of the oscillator closed loop. The start-up time-out from the

IDLE timer enables the clock signals to be routed to the rest

of the chip.

This toggle condition of the thirteenth bit of the IDLE Timer

T0 is latched into the T0PND pending flag.

The user has the option of being interrupted with a transition

on the thirteenth bit of the IDLE Timer T0. The interrupt can

be enabled or disabled via the T0EN control bit. Setting the

T0EN flag enables the interrupt and vice versa.

The user can enter the IDLE mode with the Timer T0 inter-

rupt enabled. In this case, when the T0PND bit gets set, the

device will first execute the Timer T0 interrupt service routine

and then return to the instruciton following the “Enter Idle

Mode” instruction.

Alternatively, the user can enter the IDLE mode with the

IDLE Timer T0 interrupt disabled. In this case, the device will

resume normal operation with the instruction immediately

following the “Enter IDLE Mode” instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions

are necessary to allow clock resynchronization following the HALT or

IDLE modes.

The device has two mask options associated with the HALT

mode. The first mask option enables the HALT mode feature,

while the second mask option disables the HALT mode. With

the HALT mode enable mask option, the device will enter

and exit the HALT mode as described above. With the HALT

disable mask option, the device cannot be placed in the

HALT mode (writing a “1” to the HALT flag will have to effect).

Multi-Input Wakeup

The Multi-Input Wakeup feature is used to return (wakeup)

the device from either the HALT or IDLE modes. Alternately,

the Multi-Input Wakeup/Interrupt feature may also be used to

generate up to 7 edge selectable external interrupts.

IDLE MODE

Note: The following description is for both the Port L and the M port. When

the document refers to the registers WKEGD, WKEN or WKPND, the

user will have to put either M (for M port) or L (for port) in front of the

register, i.e., LWKEN (Port L WKEN), MWKEN (Port M WKEN).

The device is placed in the IDLE mode by writing a “1” to the

IDLE flag (G6 data bit). In this mode, all activity, except the

associated on-board oscillator circuitry, ad the IDLE Timer

T0, is stopped. The power supply requirements of the micro-

controller in this mode of operation are typically around 30%

of normal power requirement of the microcontroller.

Figures 12, 13 shows the Multi-Input Wakeup logic for the

microcontroller. The Multi-Input Wakeup feature utilizes the L

Port. The user selects which particular Port L bit (or combi-

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16

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for Port L bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

Multi-Input Wakeup (Continued)

nation of Port L bits) will cause the device to exit the HALT or

IDLE modes. The selection is done through the Reg: WKEN.

The Reg: WKEN is an 8-bit read/write register, which con-

tains a control bit for every Port L bit. Setting a particular

WKEN bit enables a Wakeup from the associated Port L pin.

RBIT 5, WKEN

;Disable MIWU

SBIT 5, WKEDG ;Change edge polarity

RBIT 5, WKPND ;Reset pending flag

The user can select whether the trigger condition on the se-

lected Port L pin is going to be either a positive edge (low to

high transition) or a negative edge (high to low transition).

This selection is made via the Reg: WKEDG, which is an

8-bit control register with a bit assigned to each Port L pin.

Setting the control bit will select the trigger condition to be a

negative edge on that particular Port L pin. Resetting the bit

selects the trigger condition to be a positive edge. Changing

an edge select entails several steps in order to avoid a

pseudo Wakeup condition as a result of the edge change.

First, the associated WKEN bit should be reset, followed by

the edge select change in WKEDG. Next, the associated

WKPND bit should be cleared, followed by the associated

WKEN bit being re-enabled.

SBIT 5, WKEN

;Enable MIWU

If the Port L bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid inherited pseudo

wakeup conditions. After the selected Port L bits have been

changed from output to input but before the associated

WKEN bits are enabled, the associated edge select bits in

WKEDG should be set or reset for the desired edge selects,

followed by the assoicated WKPND bits being cleared.

DS100044-13

FIGURE 12. Port M Multi-Input Wake-up Logic

This same procedure should be used following reset, since

the Port L inputs are left floating as a result of reset. The oc-

currence of the selected trigger condition for Multi-Input

Wakeup is latched to a pending register called WKPND. The

respective bits of the WKPND register will be set on the oc-

currence of the selected trigger edge on the corresponding

Port L and Port M pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

register for the occurrence of selected wakeup conditions,

the device will not enter the HALT mode if any wakeup bit is

both enabled and pending. Consequently, the user has the

responsibility of clearing the pending flags before attempting

to enter the HALT mode.

The WKEN, WKPND and WKEDG are all read/write regis-

ters, and are cleared at reset.

PORT L INTERRUPTS

Port L provides the user with additional eight fully selectable,

edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

17

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nite start up time. The IDLE Timer (T0) generates a fixed de-

lay to ensure that the oscillator has indeed stabilized before

allowing the device to execute instructions. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is

Multi-Input Wakeup (Continued)

The GIE (global interrupt enable) bit enables the interrupt

function. A control flag, LPEN, functions as a global interrupt

enable for Port L interrupts. Setting the LPEN flag will enable

interrupts and vice versa. A separate global pending flag is

not needed since the register WKPND is adequate.

loaded with a value of 256 and is clocked from the t

_cinstruc-

tion cycle clock. The t_cclock is derived by dividing down the

oscillator clock by a factor of 10. A Schmitt trigger following

the CKI on-chip inverter ensures that the IDLE timer is

clocked only when the oscillator has a sufficiently large am-

plitude to meet the Schmitt trigger specifications. This

Schmitt trigger is not part of the oscillator closed loop. The

start-up time-out from the IDLE timer enables the clock sig-

nals to be routed to the rest of the chip.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

The Wakeup signal will not start the chip running immedi-

ately since crystal oscillators or ceramic resonators have a fi-

DS100044-14

FIGURE 13. Port L Multi-Input Wake-Up Logic

PORT M INTERRUPTS

struction cycle of the instruction following the enter HALT or

IDLE mode instruction). In the other case, the device finishes

the instruction which was being executed when the part was

stopped (the NOP(Note *NO TARGET FOR FNXref

NS9529*) instruction following the enter HALT or IDLE mode

instruction), and then branches to the interrupt service rou-

tine. The device then reverts to normal operation.

Port M provides the user with seven fully selectable, edge

sensitive interrupts which are all vectored into the same ser-

vice subroutine.

The interrupt from Port M shares logic with the wake up cir-

cuitry. The MWKEN register allows interrupts from Port M to

be individually enabled or disabled. The MWKEDG register

specifies the trigger condition to be either a positive or a

negative edge. The MWKPND register latches in the pend-

ing trigger conditions.

Note 16: The user must place two NOPs after an enter HALT or IDLE mode

instruction.

To prevent erroneous clearing of the SPI receive FIFO when

entering HALT/IDLE mode, the user needs to enable the

MIWU on port M3. (SS) by setting bit 3 in the MWKEN reg-

ister.

The LPEN control flag in the ICNTRL register functions as a

global interrupt enable for Port M interrupts. Setting the

LPEN flag enables interrupts. Note that the GIE bit in the

PSW register must also be set to enable these Port L inter-

rupts. A global pending flag is not needed since each pin has

a corresponding pending flag in the MWKPND register.

CAN RECEIVE WAKEUP

The CAN Receive Wakeup source can be enabled or dis-

abled. There is no specific enable bit for the CAN Wakeup

feature. Although the wakeup feature on pins L0..17 and

M0..M7 can be programmed to generate an interrupt (Port L

or Port M interrupt), no interrupt is generated upon a CAN re-

Since Port M is also used for exiting the device from the

HALT or IDLE mode, the user can elect to exit the HALT or

IDLE mode either with or without the interrupt enabled. If the

user elects to disable the interrupt, then the device restarts

execution from the point at which it was stopped (first in-

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18

Multi-Input Wakeup (Continued)

CAN Interface Block

This device supports applications which require a low speed

CAN interface. It is designed to be programmed with two

transmit and two receive registers. The user’s program may

check the status bytes in order to get information of the bus

state and the received or transmitted messages. The device

has the capability to generate an interrupt as soon as one

byte has been transmitted or received. Care must be taken if

more than two bytes in a message frame are to be

transmitted/received. In this case the user’s program must

poll the transmit buffer empty (TBE)/receive buffer full (RBF)

bits or enable their respective interrupts and perform a data

exchange between the user data and the Tx/Rx registers.

ceive wakeup condition. The CAN block has it’s own, dedi-

cated receiver interrupt upon receive buffer full (see CAN

Section).

CAN Wake-Up:

The CAN interface can be programmed to wake the device

from HALT/IDLE mode. This is done by setting bit 7 in the

Port M wake-up enable register (MWKEN). A transition on

the bus will cause the bit 7 of the Port M wake-up pending

(MWKPND) to be set and thereby waking up the device. The

frame on the CAN bus will be lost. The MWEDG (m port

wake-up edge) register bit 7 can be programmed high or low

(high will wake-up on the first falling edge on Rx0).

Fully automatic transmission on error is supported for mes-

sages not longer than two bytes. Messages which are longer

than two bytes have to be processed by software.

Resetting bit 7 in the MWKEN will disable the CAN wake-up.

The following sequence should be executed before entering

HALT/IDLE mode:

The interface is compatible with CAN Specification 2.0 part

B, without the capability to receive/transmit extended

frames. Extended frames on the bus are checked and ac-

knowledged according to the CAN specification.

RBIT 7, MWKPND ;clear CAN wake-up pending

LD

AND A, #0CF

A, CBUS

;resetTxEN0 and TxEN1

;disable main receive

;comparator

The maximum bus speed achievable with the CAN interface

is a function of crystal frequency, message length and soft-

ware overhead. The device can support a bus speed of up to

1 Mbit/s with a 10 MHz oscillator and 2 byte messages. The

1 Mbit/s bus speed refers to the rate at which protocol and

data bits are transferred on the bus. Longer messages re-

quire slower bus speeds due to the time required for soft-

ware intervention between data bytes. The device will sup-

port a maximum of 125k bit/s with eight byte messages and

a 10 MHz oscillator.

X

After the device woke-up the CBUS bits TxEN0 and/or

TxEN1 need be set to allow synchronization on the bus and

to enable transmission/reception of CAN frames.

CAN Block Description *

This device contains a CAN serial bus interface as described

in the CAN Specification Rev. 2.0 part B.

*Patents Pending.

19

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CAN Interface Block (Continued)

DS100044-16

FIGURE 14. CAN Interface Block Diagram

Transceive Logic (TCL)

Functional Block Description of

the CAN Interface

The TCL is a state machine which incorporates the bit stuff

logic and controls the output drivers, CRC logic and the

Rx/Tx shift registers. It also controls the synchronization to

the bus with the CAN clock signal generated by the BTL.

Interface Management Logic (IML)

The IML executes the CPU’s transmission and reception

commands and controls the data transfer between CPU,

Rx/Tx and CAN registers. It provides the CAN Interface with

Rx/Tx data from the memory mapped Register Block. It also

sets and resets the CAN status information and generates

interrupts to the CPU.

Error Management Logic (EML)

The EML is responsible for the fault confinement of the CAN

protocol. It is also responsible for changing the error

counters, setting the appropriate error flag bits and interrupts

and changing the error status (passive, active and bus off).

Bit Stream Processor (BSP)

Cyclic Redundancy Check (CRC)

Generator and Register

The BSP is a sequencer controlling the data stream between

The Interface Management Logic (parallel data) and the bus

line (serial data). It controls the transceive logic with regard

to reception and arbitration, and creates error signals ac-

cording to the bus specification.

The CRC Generator consists of a 15-bit shift register and the

logic required to generate the checksum of the destuffed bit-

stream. It informs the EML about the result of a receiver

checksum.

The checksum is generated by the polynomial:

χ¹⁵+ χ¹⁴+ χ¹⁰+ χ⁸+ χ⁷+ χ⁴+ χ³− 1

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20

It is the user’s responsibility to ensure that the time between

setting TBE and a reload of TxD2 is longer than the length of

phase segment 2 as indicated in the following equation:

Functional Block Description of

the CAN Interface ^(Continued)

Receive/Transmit (Rx/Tx) Registers

The Rx/Tx registers are 8-bit shift registers controlled by the

TCL and the BSP. They are loaded or read by the Interface

Management Logic, which holds the data to be transmitted

or the data that was received.

Table 3 shows examples of the minimum required t_LOADfor

different CSCAL settings based on a clock frequency of

10 MHz. Lower clock speeds require recalculation of the

CAN bit rate and the mimimum t_LOAD

.

Bit Time Logic (BTL)

The bit time logic divider divides the CKI input clock by the

value defined in the CAN prescaler (CSCAL) and bus timing

register (CTIM). The resultig bit time (tcan) can be computed

by the formula:

TABLE 3. CAN Timing (CKI = 10 MHz, t_c= 1 µs)

Minimum

PS CSCAL

CAN Bit Rate (kbit/s)

t_LOAD(µs)

2.0

4

3

9

250

100

62

40

25

10

5

5.0

Where divider is the value of the clock prescaler, PS is the

programmable value of phase segment 1 and 2 (1..8) and

PPS the programmed value of the propagation segment

(1..8) (located in CTIM).

15

24

39

99

199

8.0

12.5

20

50

Bus Timing Considerations

100

The internal architecture of the CAN interface has been op-

timized to allow fast software response times within mes-

sages of more than two data bytes. The TBE (Transmit

Buffer Empty) bit is set on the last bit of odd data bytes when

CAN internal sample points are high.

DS100044-17

FIGURE 15. Bit Rate Generation

Figure 16 illustrates the minimum time required for t_LOAD

.

DS100044-18

FIGURE 16. TBE Timing

In the case of an interrupt driven CAN interface, the calcula-

tion of the actual t_LOADtime would be done as follows:

•

;registers with subsequent data

;bytes.

LD

•

TXD2,DATA

INT:

PUSH A

LD

PUSH A

VIS

CANTX:

•

;Interrupt latency = 7tc = 7 µs

; 3tc = 3 µs

A,B ; 2tc = 2 µs

•

; 3tc = 3 µs

; 5tc = 5 µs

;20tc = µs to this point

;additional time for instructions

;which check

Interrupt driven programs use more time than programs

which poll the TBE flag, however programs which operate at

lower baud rates (which are more likely to be sensitive to this

issue) have more time for interrupt response.

•

;status prior to reloading the

;transmit data

21

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RECEIVER DATA REGISTER 1 (RXD1) (Address

X’00A4)

Functional Block Description of

the CAN Interface ^(Continued)

The Receive Data Register 1 (RXD1) contains the first data

byte received in a frame and then successive odd byte num-

bers (i.e., bytes 1, 3,..7). This register is read-only.

Output Drivers/Input Comparators

The output drivers/input comparators are the physical inter-

face to the bus. Control bits are provided to TRI-STATE the

output drivers.

RECEIVE DATA REGISTER 2 (RXD2) (Address X’00A5)

The Receive Data Register 2 (RXD2) contains the second

data byte received in a frame and then successive even byte

numbers (i.e., bytes 2,4,..,8). This register is read-only.

A dominant bit on the bus is represented as a “0” in the data

registers and a recessive bit on the bus is represented as a

“1” in the data registers.

REGISTER DATA LENGTH CODE AND IDENTIFIERLOW

REGISTER (RIDL) (Address X’00A6)

TABLE 4. Bus Level Definition

RID3 RID2 RID1 RID0 RDLC3 RDLC2 RDLC1 RDLC0

Bus Level

Pin Tx0

drive low

(GND)

Pin Tx1

Data

Bit 7

Bit 0

“dominant”

dirve high

0

This register is read only.

(V_CC

)

RID3..RID0 Receive Identifier bits (lower four bits)

“recessive”

TRI-STATE

1

The RID3..RID0 bits are the lower four bits of the eleven bit

long Receive Identifier. Any received message that matches

the upper 7 bits of the Receive Identifier (RID10..RID4) is ac-

cepted if the Receive Identifier Acceptance Filter (RIAF) bit is

set to zero.

Register Block

The register block consists of fifteen 8-bit registers which are

described in more detail in the following paragraphs.

Note: The contents of the receiver related registers RxD1, RxD2, RDLC,

RIDH and RTSTAT are only changed if a received frame passes the

acceptance filter or the Receive Identifier Acceptance Filter bit (RIAF)

is set to accept all received messages.

RDLC3..RDLC0 Receive Data Length Code bits

The RDLC3..RDLC0 bits determine the number of data

bytes within a received frame.

TRANSMIT DATA REGISTER 1 (TXD1) (Address

X’00A0)

RECEIVE IDENTIFIER HIGH (RID) (Address X’00A7)

The Transmit Data Register 1 contains the first data byte to

be transmitted within a frame and then the successive odd

byte numbers (i.e., bytes number 1,3,..,7).

Reserved RID10 RID9 RID8 RID7 RID6 RID5 RID4

Bit 7

Bit 0

This register is read/write.

Bit 7 is reserved and should be zero.

RID10..RID4 Receive Identifier bits (upper bits)

TRANSMIT DATA REGISTER 2 (TXD2)(Address X’00A1)

The Transit Data Register 2 contains the second data byte to

be transmitted within a frame and then the successive even

byte numbers (i.e., bytes number 2,4,..,8).

The RID10...RID4 bits are the upper 7 bits of the eleven bit

long Receive Identifier. If the Receive Identifier Acceptance

Filter (RIAF) bit (see CBUS register) is set to zero, bits 4 to

10 of the received identifier are compared with the mask bits

of RID4..RID10. If the corresponding bits match, the mes-

sage is accepted. If the RIAF bit is set to a one, the filter

function is disabled and all messages, independent of iden-

tifier, will be accepted.

TRANSMIT DATA LENGTH CODE AND IDENTIFIER

LOW REGISTER (TDLC) (Address X’00A2)

TID3 TID2 TID1 TID0 TDLC3 TDLC2 TDLC1 TDLC0

Bit 7

Bit 0

This register is read/write.

CAN PRESCALER REGISTER (CSCAL) (Address

X’00A8)

TID3..TIDO Transmit Identifier Bits 3..0 (lower 4 bits)

The transmit identifier is composed of eleven bits in total, bits

3 to 0 of the TID are stored in bits 7 to 4 of this register.

CKS7

Bit 7

CKS6

CKS5

CKS4

CKS3

CKS2

CKS1

CKS0

Bit 0

TDLC3..TDLC0 Transmit Data Length Code

This register is read/write.

CKS7..0 Prescaler divider select.

These bits determine the number of data bytes to be trans-

mitted within a frame. The CAN specification allows a maxi-

mum of eight data bytes in any message.

The resulting clock value is the CAN Prescaler clock.

TRANSMIT IDENTIFIER HIGH (TID) (Address X’00A3)

CAN BUS TIMING REGISTER (CTIM) (00A9)

TRTR

Bit 7

TID10

TID9

TID8

TID7

TID6

TID5

TID4

Bit 0

PPS2

Bit 7

PPS1

PPS0

PS2

PS1

PS0

Reserved

Bit 0

This register is read/write.

TRTR Transmit Remote Frame Request

This register is read/write.

PPS2..PPS0 Propagation Segment, bits 2..0

This bit is set if the frame to be transmitted is a remote frame

request.

The PPS2..PPS0 bits determine the length of the propaga-

tion delay in Prescaler clock cycles (PSC) per bit time. (For

a more detailed discussion of propagation delay and phase

segments, see SYNCHRONIZATION.)

TID10..TID4 Transmit Identifier Bits 10 .. 4 (higher 7 bits)

Bits TID10..TID4 are the upper 7 bits of the 11 bit transmit

identifier.

PS2..PS0 Phase Segment 1, bits 2..0

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22

Functional Block Description of

the CAN Interface ^(Continued)

The PS2..PS0 bits fix the number of Prescaler clock cycles

per bit time for phase segment 1 and phase segment 2. The

PS2..PS0 bits also set the synchronization Jump Width to a

value equal to the lesser of: 4 PSC, or the length of PS1/2

(Min: 4 l length of PS1/2).

TxEN1

TxEN0

Output

1

Tx0 and Tx1 enabled

Bus synchronization of the device is done in the following

way:

If the output was disabled (TxEN1, TxEN0 = “0”) and either

TxEN1 or TxEN0, or both are set to 1, the device will not start

transmission or reception of a frame until eleven consecutive

“recessive” bits have been received. Resetting the TxEN1

and TxEN0 bits will disable the output drivers and the CAN

input comparator. All other CAN related registers and flags

will be unaffected. It is recommended that the user reset the

TxEN1 and TxEN0 bits before switching the device into the

HALT mode (the CAN receive wakeup will still work) in order

to reduce current consumption and to assure a proper resy-

chronization to the bus after exiting the HALT mode.

Bits 1 and 0 are reserved and should be zero.

TABLE 5. Synchronization Jump Width

Length of

Phase

Synchronization

Jump Width

PS2

PS1

PS0

1

Segment ⁄

2

Note: A “bus off” condition will also cause Tx0 and Tx1 to be at TRI-STATE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 t_can

2 t_can

3 t_can

4 t_can

5 t_can

6 t_can

7 t_can

8 t_can

1 t_can

2 t_can

3 t_can

4 t_can

(independent of the values of the TxEN1 and TxEN0 bits).

RXREF1 Reference voltage applied to Rx1 if bit is set

RXREF0 Reference voltage applied to Rx0 if bit is set

FMOD

Fault Confinement Mode select

Setting the FMOD bit to “0” (default after power on reset) will

select the Standard Fault Confinement mode. In this mode

the device goes from “bus off” to “error active” after monitor-

ing 128*11 recessive bits (including bus idle) on the bus. This

mode has been implemented for compatibility with existing

solutions. Setting the FMOD bit to “1” will select the En-

hanced Fault Confinement mode. In this mode the device

goes from “bus off” to “error active” after monitoring 128

“good” messages, as indicated by the reception of 11 con-

secutive “recessive” bits including the End of Frame,

whereas the standard mode may time out after 128 x 11 re-

cessive bits (e.g., bus idle).

LENGTH OF TIME SEGMENTS (See Figure 28)

•

The Synchronization Segment is 1 CAN Prescaler clock

(PSC)

The Propagation Segment can be programmed (PPS) to

be 1,2...,8 PSC in length.

Phase Segment 1 and Phase Segment 2 are program-

mable (PS) to be 1,2,..,8 PSC long.

Note: (BTL settings at high speed; PSC = 0) Due to the on-chip delay from

the rx-pins through the receive comparator (worst case assumption: 3

clocks delay * 2 (devices on the bus) + 1 tx delay) the user needs to set

the sample point to (2*3 + 1) i.e., 7 CKI clocks to ensure correct com-

munication on the bus under all circumstances. With prescaler settings

of 0 this is a given (i.e., no caution has to be applied).

TRANSMIT CONTROL/STATUS (TCNTL) (00AB)

NS1

Bit 7

NS0

TERR

RERR

CEIE

TIE

RIE

TXSS

Bit 0

NS1..NS0 Node Status, i.e., Error Status.

Example: for 1 Mbit CTIM = b’10000100 (PSS = 5; PS1 = 2). Example

for 500 kbit CTIM = b’01011100 (PPS = 3; PS1 = 8). − all at 10 MHz

CKI and CSCAL = 0.

TABLE 7. Node Status

NS1

NS0

Output

Error active

CAN BUS CONTROL REGISTER (CBUS) (00AA)

0

1

0

1

0

1

Re-

served

Bit 7

RIAF

TxEN1

TxEN0

RxREF1

RxREF0

Re-

FMOD

Bit 0

Error passive

Bus off

served

Bus off

Reserved These bits are reserved and should be zero.

RIAF Receive identifier acceptance filter bit

The Node Status bits are read only.

TERR Transmit Error

If the RIAF bit is set to zero, bits 4 to 10 of the received iden-

tifier are compared with the mask bits of RID4..RID10 and if

the corresponding bits match, the message is accepted. If

the RIAF bit is set to a one, the filter function is disabled and

all messages independent of the identifier will be accepted.

This bit is automatically set when an error occurs during the

transmission of a frame. TERR can be programmed to gen-

erate an interrupt by setting the Can Error Interrupt Enable

bit (CEIE). This bit must be cleared by the user’s software.

Note: This is used for messages for more than two bytes. If an error occurs

during the transmission of a frame with more than 2 data bytes, the us-

er’s software has to handle the correct reloading of the data bytes to

the TxD registers for retransmission of the frame. For frames with 2 or

fewer data bytes the interface logic of this chip does an automatic re-

transmission. Regardless of the number of data bytes, the user’s soft-

ware must reset this bit if CEIE is enabled. Otherwise a new interrupt

will be generated immediately after return from the interrupt service

routine.

TxEN0, TxEN1 TxD Output Driver Enable

TABLE 6. Output Drivers

TxEN1

TxEN0

Output

Tx0, Tx1 TRI-STATE, CAN

input comparator disabled

Tx0 enabled

0

RERR Receiver Error

0

1

0

This bit is automatically set when an error occurred during

the reception of a frame. RERR can be programmed to gen-

Tx1 enabled

23

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RECEIVE/TRANSMIT STATUS (RTSTAT) (Address

X’00AC)

Functional Block Description of

the CAN Interface ^(Continued)

TBE TXPND RRTR ROLD RORN RFV RCV RBF

erate an interrupt by setting the Can Error Interrupt Enable

bit (CEIE). This bit has to be cleared by the user’s software.

1

0

Bit 7

Bit 0

CEIE CAN Error Interrupt Enable

This register is read only.

TBE Transmit Buffer Empty

If set by the user’s software, this bit enables the transmit and

receive error interrupts. The interrupt pending flags are

TERR and RERR. Resetting this bit with a pending error in-

terrupt will inhibit the interrupt, but will not clear the cause of

the interrupt (RERR or TERR). If the bit is then set without

clearing the cause of the interrupt, the interrupt will reoccur.

This bit is set as soon as the TxD2 register is copied into the

Rx/Tx shift register, i.e., the 1st data byte of each pair has

been transmitted. The TBE bit is automatically reset if the

TxD2 register is written (the user should write a dummy byte

to the TxD2 register when transmitting an odd number of

bytes of zero bytes). TBE can be programmed to generate

an interrupt by setting the Transmit Interrupt Enable bit (TIE).

When servicing the interrupt the user has to make sure that

TBE gets cleared by executing a WRITE instruction on the

TxD2 register, otherwise a new interrupt will be generated

immediately after return from the interrupt service routine.

The TBE bit is read only. It is set to 1 upon reset. TBE is also

set upon completion of transmission of a valid message.

TIE Transmit Interrupt Enable

If set by the user’s software, this bit enables the transmit in-

terrupt. (See TBE and TXPND.) Resetting this bit with a

pending transmit interrupt will inhibit the interrupt, but will not

clear the cause of the interrupt. If the bit is then set without

clearing the cause of the interrupt, the interrupt will reoccur.

RIE Receive Interrupt Enable

If set by the user’s software, this bit enables the receive in-

terrupt or a remote transmission request interrupt (see RBF,

RFV and RRTR). Resetting this bit with a pending receive in-

terrupt will inhibit the interrupt, but will not clear the cause of

the interrupt. If the bit is then set without clearing the cause

of the interrupt, the interrupt will reoccur.

TXPND Transmission Pending

This bit is set as soon as the Transmit Start/Stop (TXSS) bit

is set by the user. It will stay set until the frame was success-

fully transmitted, until the transmission was successfully can-

celed by writing zero to the Transmission Start/Stop bit

(TXSS), or the device enters the bus-off state. Resetting the

TXSS bit will only cancel a transmission if the transmission

of a frame hasn’t been started yet (bus idle) or if arbitration

has been lost (receiving). If the device has already started

transmission (won arbitration) the TXPND flag will stay set

until the transmission is completed, even if the user’s soft-

ware has requested cancellation of the message. If an error

occurs during transmission, a requested cancellation may

occur prior to the begining of retransmission.

TXSS Transmission Start/Stop

This bit is set by the user’s software to initiate the transmis-

sion of a frame. Once this bit is set, a transmission is pend-

ing, as indicated by the TXPND flag being set. It can be reset

by software to cancel a pending transmission. Resetting the

TXSS bit will only cancel a transmission, if the transmission

of a frame hasn’t been started yet (bus idle), if arbitration has

been lost (receiving) or if an error occurs during transmis-

sion. If the device has already started transmission (won ar-

bitration) the TXPND and TXSS flags will stay set until the

transmission is completed, even if the user’s software has

written zero to the TXSS bit. If one or more data bytes are to

be transmitted, care must be taken by the user, that the

Transmit Data Register(s) have been loaded before the

TXSS bit is set. TXSS will be cleared on three conditions

only: Successful completion of a transmitted message; suc-

cessful cancellation of a pending transmision; Transition of

the CAN interface to the bus-off state.

RRTR Received Remote Transmission Request

This bit is set when the remote transmission request (RTR)

bit in a received frame was set. It is automatically reset

through a read of the RXD1 register.

To detect RRTR the user can either poll this flag or enable

the receive interrupt (the reception of a remote transmission

request will also cause an interrupt if the receive interrupt is

enabled). If the receive interrupt is enabled, the user should

check the RRTR flag in the service routine in order to distin-

guish between a RRTR interrupt and a RBF interrupt. It is the

responsibility of the user to clear this bit by reading the RXD1

register, before the next frame is received.

ROLD Received Overload Frame

This bit is automatically set when an Overload Frame was

received on the bus. It is automatically reset through a read

of the Receive/Transmit Status register. It is the responsibil-

ity of the user to clear this bit by reading the Receive/

Transmit Status register, before the next frame is received.

RORN Receiver Overrun

DS100044-19

This bit is automatically set on an overrun of the receive data

register, i.e., if the user’s program does not maintain the

RxDn registers when receiving a frame. It is automatically re-

set through a read of the Receive/Transmit Status register. It

is the responsibility of the user to clear this bit by reading the

Receive/Transmit Status register before the next frame is re-

ceived.

FIGURE 17. Acceptance Filter Block-Diagram

Writing a zero to the TXSS bit will request cancellation of a

pending transmission but TXSS will not be cleared until

completion of the operation. If an error occurs during trans-

mission of a frame, the logic will check for cancellation re-

quests prior to restarting transmission. If zero has been writ-

ten to TXSS, retransmission will be canceled.

RFV Received Frame Valid

This bit is set if the received frame is valid, i.e., after the pen-

ultimate bit of the End of Frame is received. It is automati-

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24

dow (16 messages). The upper 7 bits can be defined by the

user in the Receive Identifier High Register to mask out

groups of messages. If the RIAF bit is set, all messages will

be received.

Note: The CAN interface tolerates the extended CAN frame format of 29

identifier bits and gives an acknowledgment. If an error occurs the re-

ceive error counter will be increased, and decreased if the frame is

valid.

Functional Block Description of

the CAN Interface ^(Continued)

cally reset through a read of the Receive/Transmit Status

register. It is the responsibility of the user to clear this bit by

reading the receive/transmit status register (RTSTAT), be-

fore the next frame is received. RFV will cause a Receive In-

terrupt if enabled by RIE. The user should be careful to read

the last data byte (RxD1) of odd length messages (1, 3, 5 or

7 data bytes) on receipt of RFV. RFV is the only indication

that the last byte of the message has been received.

BUS SYNCHRONIZATION DURING OPERATION

Resetting the TxEN1 and TxEN0 bits in Bus Control Register

will disable the output drivers and do a resynchronization to

the bus. All other CAN related registers and flags will be un-

affected.

RCV Receive Mode

This bit is set after the data length code of a message that

passes the device’s acceptance filter has been received. It is

automatically reset after the CRC-delimiter of the same

frame has been received. It indicates to the user’s software

that arbitration is lost and that data is coming in for that node.

Bus synchronization of the device is this case is done in the

following way:

If the output was disabled (TxEN1, TxEN0 = “0”) and either

TxEN1 or TxEN0, or both are set to 1, the device will not start

transmission or reception of a frame until eleven consecutive

“recessive” bits have been received.

RBF Receive Buffer Full

This bit is set if the second Rx data byte was received. It is

reset automatically, after the RxD1-Register has been read

by the software. RBF can be programmed to generate an in-

terrupt by setting the Receive Interrupt Enable bit (RIE).

When servicing the interrupt, the user has to make sure that

RBF gets cleared by executing a LD instruction from the

RxD1 register, otherwise a new interrupt will be generated

immediately after return from the interrupt service routine.

The RBF bit is read only.

A “bus off” condition will also cause the output drivers Tx1

and Tx0 to be at TRI-STATE (independent of the status of

TxEN1 and TxEN0). The device will switch from “bus off” to

“error active” mode as described under the FMOD-bit de-

scription (see Can Bus Control register). This will ensure that

the device is synchronized to the bus, before starting to

transmit or receive.

For information on bus synchronization and status of the

CAN related registers after external reset refer to the RESET

section.

TRANSMIT ERROR COUNTER (TEC) (Address X’00AD)

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

ON-CHIP VOLTAGE REFERENCE

Bit 7

Bit 0

The on-chip voltage reference is a ratiometric reference. For

electrical characteristics of the voltage reference refer to the

electrical specifications section.

This register is read/write.

For test purposes and to identify the node status, the trans-

mit error counter, an 8-bit error counter, is mapped into the

data memory. If the lower seven bits of the counter overflow,

i.e., TEC7 is set, the device is error passive.

ANALOG SWITCHES

Analog switches are used for selecting between Rx0 and

CAUTION

V_REFand between Rx1 and V_REF

.

To prevent interference with the CAN fault confinement, the

user must not write to the REC/TEC registers. Both counters

are automatically updated following the CAN specification.

Basic CAN Concepts

The following paragraphs provide a generic overview of the

basic concepts of the Controller Area Network (CAN) as de-

scribed in Chapter 4 of ISO/DIS11519-1. Implementation re-

lated issues of the National Semiconductor device will be

discussed as well.

RECEIVE ERROR COUNTER (REC) (00AE)

ROVL REC6 REC5 REC4 REC3 REC2 REC1 REC0

Bit 7

Bit 0

This device will process standard frame format only. Ex-

tended frame formats will be acknowledged, however the

data will be discarded. For this reason the description of

frame formats in the following section will cover only the

standard frame format.

This register is read/write.

ROVL receive error counter overflow

For test purposes and to identify the node status the receive

error counter, a 7-bit error counter, is mapped into the data

memory. If the counter overflows the ROVL bit is set to indi-

cate that the device is error passive and won’t transmit any

active error frames. If ROVL is set then the counter is frozen.

The following section provides some more detail on how the

device will handle received extended frames:

If the device’s remote identifier acceptance filter bit (RIAF) is

set to “1”, extended frame messages will be acknowledged.

However, the data will be discarded and the device will not

reply to a remote transmission request received in extended

frame format. If the device’s RIAF bit is set to “0”, the upper

7 received ID bits of an extended frame that match the de-

vice’s receive identifier (RID) acceptance filtler bits, are

stroed in the device’s RID register. However, the device does

not reply to an RTR and any data is discarded. The device

will only acknowledge the message.

MESSAGE IDENTIFICATION

a. Transmitted Message

The user can select all 11 Transmit Identifier Bits to transmit

any message which fulfills the CAN 2.0, part B spec without

an extended identifier (see note below). Fully automatic re-

transmission is supported for messages no longer than 2

bytes.

b. Received Messages

The lower four bits of the Receive Identifier are don’t care,

i.e., the controller will receive all messages that fit in that win-

25

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overwritten by a message with a higher priority. As soon as a

transmitting module detects another module with a higher

priority accessing the bus, it stops transmitting its own frame

and switches to receive mode. For illustration see Figure 18.

Basic CAN Concepts (Continued)

MULTI-MASTER PRIORITY BASED BUS ACCESS

The CAN protocol is message based protocol that allows a

total of 2032 (= 2¹¹−16) different messages in the standard

format and 512 million (= 2²⁹−16) different messages in the

extended frame format.

AUTOMATIC RETRANSMISSION OF FRAMES

If a data or remote frame is overwritten by either a higher-

prioritized data frame, remote frame or an error frame, the

transmitting module will automatically retransmit it. This de-

vice will handle the automatic retransmission of up to two

data bytes automatically. Messages with more than 2 data

bytes require the user’s software to update the transmit reg-

isters.

MULTICAST FRAME TRANSFER BY

ACCEPTANCE FILTERING

Every CAN Frame is put on the common bus. Each module

receives every frame and filters out the frames which are not

required for the module’s task.

ERROR DETECTION AND ERROR SIGNALING

REMOTE DATA REQUEST

All messages on the bus are checked by each CAN node

and acknowledge if they are correct. If any node detects an

error it starts the transmission of an error frame.

A CAN master module has the ability to set a specific bit

called the “remote transmission request bit” (RTR) in a

frame. This causes another module, either another master or

a slave, to transmit a data frame after the current frame has

been completed.

Switching Off Defective Nodes

There are two error counters, one for transmitted data and

one for received data, which are incremented, depending on

the error type, as soon as an error occurs. If either counter

goes beyond a specific value the node goes to an error state.

A valid frame causes the error counters to decrease.

SYSTEM FLEXIBILITY

Additional modules can be added to an existing network

without a configuration change. These modules can either

perform completely new functions requiring new data or pro-

cess existing data to perform a new function.

The device can be in one of three states with respect to error

handling:

SYSTEM WIDE DATA CONSISTENCY

•

Error active

As the CAN network is message oriented, a message can be

used like a variable which is automatically updated by the

controlling processor. If any module cannot process informa-

tion it can send an overload frame. The device is incapable

of initiating an overload frame, but will join a overload frame

initiated by another device as required by CAN specifica-

tions.

An error active unit can participate in bus communication

and sends an active (“dominant”) error flag.

•

Error passive

An error passive unit can participate in bus communica-

tion. However, if the unit detects an error it is not allowed

to send an active error flag. The unit sends only a passive

(“recessive”) error flag.

•

Bus off

NON-DESTRUCTIVE CONTENTION-BASED

ARBITRATION

A unit that is “bus off” has the output drivers disabled, i.e., it

does not participate in any bus activity.

The CAN protocol allows several transmitting modules to

start a transmission at the same time as soon as they moni-

tor the bus to be idle. During the start of transmission every

node monitors the bus line to detect whether its message is

(See ERROR MANAGEMENT AND DETECTION for more

detailed information.)

DS100044-20

FIGURE 18. CAN Message Arbitration

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26

Frame Formats

INTRODUCTION

nodes have to synchronize to the leading edge (first edge af-

ter the bus was idle) caused by SOF of the node which starts

transmission first.

There are basically two different types of frames used in the

CAN protocol.

The data transmission frames are: data/remote frame

The control frames are: error/overload frame

Note: This device cannot send an overload frame as a result of not being

able to process all information. However, the device is able to recog-

nize an overload condition and join overload frames initiated by other

devices.

ARBITRATION FIELD

The arbitration field is composed of the identifier field and the

RTR (Remote Transmission Request) bit. The value of the

RTR bit is “dominant” in a data frame and “recessive” in a re-

mote frame.

If no message is being transmitted, i.e., the bus is idle, the

bus is kept at the “recessive” level. Figure 19 and Figure 20

give an overview of the various CAN frame formats.

CONTROL FIELD

The control field consists of six bits. It starts with two bits re-

served for future expansion followed by the four-bit Data

Length Code. Receivers must accept all possible combina-

tions of the two reserved bits. Until the function of these re-

served bits is defined, the transmitter only sends “0” (domi-

nant) bits. The first reserved bit (IDE) is actually defined to

indicate an extended frame with 29 Identifier bits if set to “1”.

CAN chips must tolerate extended frames, even if they can

only understand standard frames, to prevent the destruction

of an extended frames on an existing network.

DATA AND REMOTE FRAME

Data frames consist of seven bit fields and remote frames

consist of six different bit fields:

1. Start of Frame (SOF)

2. Arbitration field

3. Control field (IDE bit, R0 bit, and DLC field)

4. Data field (not in remote frame)

5. CRC field

The Data Length Code indicates the number of bytes in the

data field. This Data Length Code consists of four bits. The

data field can be of length zero. The permissible number of

data bytes for a data frame ranges from 0 to 8.

6. ACK field

7. End of Frame (EOF)

A remote frame has no data field and is used for requesting

data from other (remote) CAN nodes. Figure 21 shows the

format of a CAN data frame.

DATA FIELD

The Data field consists of the data to be transferred within a

data frame. It can contain 0 to 8 bytes and each byte con-

tains 8 bits. A remote frame has no data field.

FRAME CODING

Remote and Data Frames are NRZ codes with bit-stuffing in

every bit field which holds computable information for the in-

terface, i.e., Start of Frame arbitration field, control field, data

field (if present) and CRC field.

CRC FIELD

The CRC field consists of the CRC sequence followed by the

CRC delimiter. The CRC sequence is derived by the trans-

mitter from the modulo 2 division of the preceding bit fields,

starting with the SOF up to the end of the data field, exclud-

ing stuff-bits, by the generator polynomial:

Error and overload frames are NRZ coded without bit stuff-

ing.

χ¹⁵+ χ¹⁴+ χ¹⁰+ χ⁸+ χ⁷+ χ⁴+ χ³+ 1

BIT STUFFING

After five consecutive bits of the same value, a stuff bit of the

inverted value is inserted by the transmitter and deleted by

the receiver.

The remainder of this division is the CRC sequence transmit-

ted over the bus. On the receiver side the module divides all

bit fields up to the CRC delimiter, excluding stuff-bits, and

checks if the result is zero. This will then be interpreted as a

valid CRC. After the CRC sequence a single “recessive” bit

is transmitted as the CRC delimiter.

Destuffed Bit Stream

Stuffed Bit Stream

100000x

011111x

1000001x

0111110x

Note: x = {0,1}

START OF FRAME (SOF)

The Start of Frame indicates the beginning of data and re-

mote frames. It consists of a single “dominant” bit. A node is

only allowed to start transmission when the bus is idle. All

27

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Frame Formats (Continued)

DS100044-21

DS100044-22

A remote frame is identical to a data frame, except that the RTR bit is “recessive”, and there is no data field.

IDE = Identifier Extension Bit

The IDE bit in the standard format is transmitted “dominant”, whereas in the extended format the IDE bit is “recessive” and the id is expanded to 29 bits.

r = recessive

d = dominant

FIGURE 19. CAN Data Transmission Frames

DS100044-23

An error frame can start anywhere in the middle of a frame.

DS100044-24

INT = Intermission

Suspend Transmission is only for error passive nodes.

DS100044-25

An overload frame can only start at the end of a frame.

FIGURE 20. CAN Control Frames

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Frame Formats (Continued)

DS100044-26

FIGURE 21. CAN Frame Format

ERROR FRAME

ACK FIELD

The ACK field is two bits long and contains the ACK slot and

the ACK delimiter. The ACK slot is filled with a “recessive” bit

by the transmitter. This bit is overwritten with a “dominant” bit

by every receiver that has received a correct CRC se-

quence. The second bit of the ACK field is a “recessive” bit

called the acknowledge delimiter. As a consequence the ac-

knowledge flag of a valid frame is surrounded by two “reces-

sive” bits, the CRC-delimiter and the ACK delimiter.

The Error Frame consists of two bit fields: the error flag and

the error delimiter. The error field is built up from the various

error flags of the different nodes. Therefore, its length may

vary from a minimum of six bits up to a maximum of twelve

bits depending on when a module detects the error. When-

ever a bit error, stuff error, form error, or acknowledgment er-

ror is detected by a node, this node starts transmission of the

error flag at the next bit. If a CRC error is detected, transmis-

sion of the error flag starts at the bit following the acknowl-

edge delimiter, unless an error flag for a previous error con-

dition has already been started. Figure 24 shows how a local

fault at one module (module 2) leads to a 12-bit error frame

on the bus.

EOF FIELD

The End of Frame Field closes a data and a remote frame. It

consists of seven “recessive” bits.

INTERFRAME SPACE

The bus level may either be “dominant” for an error-active

node or “recessive” for an error-passive node. An error ac-

tive node detecting an error, starts transmitting an active er-

ror flag consisting of six “dominant” bits. This causes the de-

struction of the actual frame on the bus. The other nodes

detect the error flag as either a violation of the rule of bit-

stuffing or the value of a fixed bit field is destroyed. As a con-

sequence all other nodes start transmission of their own er-

ror flag. This means, that the error sequence which can be

monitored on the bus as a maximum length of twelve bits. If

an error passive node detects an error it transmits six “reces-

sive” bits on the bus. This sequence does not destroy a mes-

sage sent by another node and is not detected by other

nodes. However, if the node detecting an error was the

transmitter of the frame the other modules will get an error

condition by a violation of the fixed bit or stuff rule. Figure 24

shows how an error passive transmitter transmits a passive

error frame and when it is detected by the receivers.

Data and remote frames are separate from every preceding

frame (data, remote, error and overload frames) by the inter-

frame space see Figure 22 and Figure 23 for details. Error

and overload frames are not preceded by an interframe

space. They can be transmitted as soon as the condition oc-

curs. The interframe space consists of a minimum of three

bit fields depending on the error state of the node.

These bit fields are coded as follows:

The intermission has the fixed form of three “recessive” bits.

While this bit field is active, no node is allowed to start a

transmission of a data or a remote frame. The only action to

be taken is signaling an overload condition. This means that

an error in this bit field would be interpreted as an overload

condition. Suspend transmission has to be inserted by error-

passive nodes that were transmitter for the last message.

This bit field has the form of eight “recessive” bits. However,

it may be overwritten by a “dominant” start-bit from another

non error passive node which starts transmission. The bus

idle field consists of “recessive” bits. Its length is not speci-

fied and depends on the bus load.

After any module has transmitted its active or passive error

flag it waits for the error delimiter which consists of eight “re-

cessive” bits before continuing.

DS100044-27

FIGURE 22. Interframe Space for Nodes Which Are Not

Error Passive or Have Been Receiver for the Last Frame

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Frame Formats (Continued)

DS100044-28

FIGURE 23. Interframe Space for Nodes Which Are Error Passive

and Have Been Transmitter for the Last Frame

DS100044-29

module 1 = error active transmitter detects bit error at t2

module 2 = error active receiver with a local fault at t1

module 3 = error active receiver detects stuff error at t2

FIGURE 24. Error Frame—Error Active Transmitter

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30

Frame Formats (Continued)

DS100044-30

module 1 = error active receiver with a local fault at t1

module 2 = error passive transmitter detects bit error at t2

module 3 = error passive receiver detects stuff error at t2

FIGURE 25. Error Frame—Error Passive Transmitter

OVERLOAD FRAME

gets the bus. This is only valid for standard CAN frame for-

mat. Note that while the CAN specification allows valid stan-

dard identifiers only in the range 0x000 to 0x7EF, the device

will allow identifiers to 0x7FF.

Like an error frame, an overload frame consists of two bit

fields: the overload flag and the overload delimiter. The bit

fields have the same length as the error frame field: six bits

for the overload flag and eight bits for the delimiter. The over-

load frame can only be sent after the end of frame (EOF)

field and in they way destroys the fixed form of the intermis-

sion field.

There are three more items that should be taken into consid-

eration to avoid unrecoverable collisions on the bus:

•

Within one system each message must be assigned a

unique identifier. This is to prevent bit errors, as one mod-

ule may transmit a “dominant” data bit while the other is

transmitting a “recessive” data bit. This could happen if

two or more modules start transmission of a frame at the

same time and all win arbitration.

ORDER OF BIT TRANSMISSION

A frame is transmitted starting with the Start of Frame, se-

quentially followed by the remaining bit fields. In every bit

field the MSB is transmitted first.

•

Data frames with a given identifier and a non-zero data

length code may be initiated by one node only. Other-

wise, in worst case, two nodes would count up to the bus-

off state, due to bit errors, if they always start transmitting

the same ID with different data.

FRAME VALIDATION

Frames have a different validation point for transmitters and

receivers. A frame is valid for the transmitter of a message, if

there is no error until the end of the last bit of the End of

Frame field. A frame is valid for a receiver, if there is no error

until and including the end of the penultimate bit of the End

of Frame.

Every remote frame should have a system-wide data

length code (DLC). Otherwise two modules starting

transmission of a remote frame at the same time will

overwrite each other’s DLC which result in bit errors.

FRAME ARBITRATION AND PRIORITY

ACCEPTANCE FILTERING

Except for an error passive node which transmitted the last

frame, all nodes are allowed to start transmission of a frame

after the intermission, which can lead to two or more nodes

starting transmission at the same time. To prevent a node

from destroying another node’s frame, it monitors the bus

during transmission of the identifier field and the RTR-bit. As

soon as it detects a “dominant” bit while transmitting a “re-

cessive” bit it releases the bus, immediately stops transmis-

sion and starts receiving the frame. This causes no data or

remote frame to be destroyed by another. Therefore the

highest priority message with the identifier 0x000 out of

0x7EF (including the remote data request (RTR) bit) always

Every node may perform acceptance filtering on the identi-

fier of a data or a remote frame to filter out the messages

which are not required by the node. In they way only the data

of frames which match the acceptance filter is stored in the

corresponding data buffers. However, every node which is

not in the bus-off state and has received a correct CRC-

sequence acknowledges each frame.

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Frame Formats (Continued)

ERROR MANAGEMENT AND DETECTION

There are multiple mechanisms in the CAN protocol, to de-

tect errors and to inhibit erroneous modules from disabling

all bus activities.

DS100044-31

FIGURE 26. Order of Bit Transmission within a CAN Frame

The following errors can be detected:

Bit Error

•

Bus off

•

A unit that is “bus off” has the output drivers disabled, i.e., it

does not participate in any bus activity. A device is bus off

when the transmit error counter is greater than 255. A bus off

device will become error active again in one of two ways de-

pending on which mode is selected by the user through the

Fault Confinement Mode select bit (FMOD) in the CAN Bus

Control Register (CBUS). Setting the FMOD bit to “0” (de-

fault after power on reset) will select the Standard Fault Con-

finement mode. In this mode the device goes from “bus off”

to “error active” after monitoring 128*11 recessive bits (in-

cluding bus idle) on the bus. This mode has been imple-

mented for compatibility reasons with existing solutions. Set-

ting the FMOD bit to “1” will select the Enhanced Fault

Confinement mode. In this mode the device goes from “bus

off” to “error active” after monitoring 128 “good” messages,

as indicated by the reception of 11 consecutive “recessive”

bits including the End of Frame. The enhanced mode offers

the advantage that a “bus off” device (i.e., a device with a se-

rious fault) is not allowed to destroy any messages on the

bus until other devices can transmit at least 128 messages.

This is not guaranteed in the standard mode, where a defec-

tive device could seriously impact bus communication. When

the device goes from “bus off” to “error active”, both error

counters will have the value “0”.

A CAN device that is sending also monitors the bus. If the

monitored bit value is different from the bit value that is sent,

a bit error is detected. The reception of a “dominant” bit in-

stead of a “recessive” bit during the transmission of a pas-

sive error flag, during the stuffed bit stream of the arbitration

field or during the acknowledge slot, is not interpreted as a

bit error.

•

Stuff error

A stuff error is detected, if the bit level after 6 consecutive bit

times has not changed in a message field that has to be

coded according to the bit stuffing method.

•

Form Error

A form error is detected, if a fixed frame bit (e.g., CRC delim-

iter, ACK delimiter) does not have the specified value. For a

receiver a “dominant” bit during the last bit of End of Frame

does NOT constitute a form error.

•

Bit CRC Error

A CRC error is detected if the remainder of the CRC calcula-

tion of a received CRC polynomial is non-zero.

•

Acknowledgment Error

An acknowledgment error is detected whenever a transmit-

ting node does not get an acknowledgment from any other

node (i.e., when the transmitter does not receive a “domi-

nant” bit during the ACK frame).

In each CAN module there are two error counters to perform

a

sophisticated error management. The receive error

counter (REC) is 7 bits wide and switches the device to the

error passive state if it overflows. The transmit error counter

(TEC) is 8 bits wide. If it is greater than 127, the device is

switched to the error passive state. As soon as the TEC

overflows, the device is switched bus-off, i.e., it does not par-

ticipate in any bus activity.

The device can be in one of three states with respect to error

handling:

•

Error active

An error active unit can participate in bus communication

and sends an active (“dominant”) error flag.

•

Error passive

An error passive unit can participate in bus communication.

However, if the unit detects an error it is not allowed to send

an active error flag. The unit sends only a passive (“reces-

sive”) error flag. A device is error passive when the transmit

error counter is greater than 127 or when the receive error

counter is greater than 127. A device becoming error passive

sends an active error flag. An error passive device becomes

error active again when both transmit and receive error

counter are less than 128.

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32

When the device goes “error passive” and detects an ac-

knowledge error, the TEC counter is not incremented.

Therefore the device will not go from “error passive” to

the “bus off” state due to such a condition.

Frame Formats (Continued)

The counters are modified by the device’s hardware accord-

ing to the following rules:

Figure 27 shows the connection of different bus states ac-

cording to the error counters.

TABLE 8. Receive Error Counter Handling

Condition

Receive Error

Counter

A receiver detects a Bit Error

Increment by 8

during sending an active error flag.

A receiver detects a “dominant” bit

as the first bit after sending an

error flag.

Increment by 8

After detecting the 14th consecutive Increment by 8

“dominant” bit following an active

error flag or overload flag or after

detecting the 8th consecutive

“dominant” bit following a passive

error flag. After each sequence of

additional 8 consecutive “dominant”

bits.

DS100044-32

FIGURE 27. CAN Bus States

SYNCHRONIZATION

Every receiver starts with a “hard synchronization” on the

falling edge of the SOF bit. One bit time consists of four bit

segments: Synchronization segment, propagation segment,

phase segment 1 and phase segment 2.

Any other error condition (stuff,

frame, CRC, ACK).

Increment by 1

A valid reception or transmission.

Decrement by 1 if

Counter is not 0

A falling edge of the data signal should be in the synchroni-

zation segment. This segment has the fixed length of one

time quanta. To compensate for the various delays within a

network, the propagation segment is used. Its length is pro-

grammable from 1 to 8 time quanta. Phase segment 1 and

phase segment 2 are used to resynchronize during an active

frame. The length of these segments is from 1 to 8 time

quanta long.

TABLE 9. Transmit Error Counter Handling

Condition

Transmit Error

Counter

A transmitter detects a Bit Error

during sending an active error

flag.

Increment by 8

Two types of synchronization are supported:

Hard synchronization is done with the falling edge on the

bus while the bus is idle, which is then interpreted as the

SOF. It restarts the internal logic.

After detecting the 14th

Increment by 8

consecutive “dominant” bit

following an active error flag or

overload flag or after detecting

the 8th consecutive “dominant”

bit following a passive error

flag. After each sequence of

additional 8 consecutive

“dominant” bits.

Soft synchronization is used to lengthen or shorten the bit

time while a data or remote frame is received. Whenever a

falling edge is detected in the propagation segment or in

phase segment 1, the segment is lengthened by a specific

value, the resynchronization jump width (see Figure 29 ).

If a falling edge lies in the phase segment 2 (as shown in Fig-

ure 29 ) it is shortened by the resynchronization jump width.

Only one resynchronization is allowed during one bit time.

The sample point lies between the two phase segments and

is the point where the received data is supposed to be valid.

The transmission point lies at the end of phase segment 2 to

start a new bit time with the synchronization segment.

Any other error condition (stuff,

frame, CRC, ACK).

Increment by 8

A valid reception or

transmission.

Decrement by

1 if Counter is not 0

1. The resynchronization jump width (RJW) is automati-

cally determined from the programmed value of PS. If a

soft resynchronization is done during phase segment 1

or the propagation segment, then RJW will either be

equal to 4 internal CAN clocks (CKI/(1 + divider)) or the

programmed value of PS, whichever is less. PS2 will

never be shorter than 1 internal CAN clock.

Special error handling for the TEC counter is performed in

the following situations:

•

A stuff error occurs during arbitration, when a transmitted

“recessive” stuff bit is received as a “dorminant” bit. This

does not lead to an incrementation of the TEC.

•

An ACK-error occurs in an error passive device and no

“dominant” bits are detected while sending the passive

error flag. This does not lead to an incrementation of the

TEC.

2. (PS1—BTL settings any PSC setting) The PS1 of the

BTL should always be programmed to values greater

than 1. To allow device resynchronization for positive

and negative phase errors on the bus. (if PS1 is pro-

grammed to one, a bit time could only be lengthened

and never shortened which basically disables half of the

synchronization).

•

If only one device is on the bus and this device transmits

a message, it will get no acknowledgment. This will be

detected as an error and message will be repeated.

33

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Frame Formats (Continued)

DS100044-33

A) Synchronization segment

B) Propagation segment

FIGURE 28. Bit Timing

DS100044-34

FIGURE 29. Resynchronization 1

DS100044-35

FIGURE 30. Resynchronization 2

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34

The Software trap has the highest priority while the default

VIS has the lowest priority.

Interrupts

Each of the 14 maskable inputs has a fixed arbitration rank-

ing and vector.

INTRODUCTION

Each device supports fourteen vectored interrupts. Interrupt

sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L

Wakeup, Software Trap, MICROWIRE/PLUS, and External

Input.

Figure 31 shows the Interrupt Block Diagram.

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

DS100044-15

FIGURE 31. Interrupt Block Diagram

35

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interrupt, and jump to the interrupt handling routine corre-

sponding to the highest priority enabled and active interrupt.

Alternately, the user may choose to poll all interrupt pending

and enable bits to determine the source(s) of the interrupt. If

more than one interrupt is active, the user’s program must

decide which interrupt to service.

Interrupts (Continued)

MASKABLE INTERRUPTS

All interrupts other than the Software Trap are maskable.

Each maskable interrupt has an associated enable bit and

pending flag bit. The pending bit is set to 1 when the interrupt

condition occurs. The state of the interrupt enable bit, com-

bined with the GIE bit determines whether an active pending

flag actually triggers an interrupt. All of the maskable inter-

rupt pending and enable bits are contained in mapped con-

trol registers, and thus can be controlled by the software.

Within a specific interrupt service routine, the associated

pending bit should be cleared. This is typically done as early

as possible in the service routine in order to avoid missing

the next occurrence of the same type of interrupt event.

Thus, if the same event occurs a second time, even while the

first occurrence is still being serviced, the second occur-

rence will be serviced immediately upon return from the cur-

rent interrupt routine.

A maskable interrupt condition triggers an interrupt under the

following conditions:

1. The enable bit associated with that interrupt is set.

2. The GIE bit is set.

An interrupt service routine typically ends with an RETI in-

struction. This instruction sets the GIE bit back to 1, pops the

address stored on the stack, and restores that address to the

program counter. Program execution then proceeds with the

next instruction that would have been executed had there

been no interrupt. If there are any valid interrupts pending,

the highest-priority interrupt is serviced immediately upon re-

turn from the previous interrupt.

3. The device is not processing a non-maskable interrupt.

(If

a non-maskable interrupt is being serviced, a

maskable interrupt must wait until that service routine is

completed.)

An interrupt is triggered only when all of these conditions are

met at the beginning of an instruction. If different maskable

interrupts meet these conditions simultaneously, the highest

priority interrupt will be serviced first, and the other pending

interrupts must wait.

VIS INSTRUCTION

The general interrupt service routine, which starts at address

00FF Hex, must be capable of handling all types of inter-

rupts. The VIS instruction, together with an interrupt vector

table, directs the device to the specific interrupt handling rou-

tine based on the cause of the interrupt.

Upon Reset, all pending bits, individual enable bits, and the

GIE bit are reset to zero. Thus, a maskable interrupt condi-

tion cannot trigger an interrupt until the program enables it by

setting both the GIE bit and the individual enable bit. When

enabling an interrupt, the user should consider whether or

not a previously activated (set) pending bit should be ac-

knowledged. If, at the time an interrupt is enabled, any pre-

vious occurrences of the interrupt should be ignored, the as-

sociated pending bit must be reset to zero prior to enabling

the interrupt. Otherwise, the interrupt may be simply en-

abled; if the pending bit is already set, it will immediately trig-

ger an interrupt. A maskable interrupt is active if its associ-

ated enable and pending bits are set.

VIS is a single-byte instruction, typically used at the very be-

ginning of the general interrupt service routine at address

00FF Hex, or shortly after that point, just after the code used

for context switching. The VIS instruction determines which

enabled and pending interrupt has the highest priority, and

causes an indirect jump to the address corresponding to that

interrupt source. The jump addresses (vectors) for all pos-

sible interrupts sources are stored in a vector table.

The vector table may be as long as 32 bytes (maximum of 16

vectors) and resides at the top of the 256-byte block contain-

ing the VIS instruction. However, if the VIS instruction is at

the very top of a 256-byte block (such as at 00FF Hex), the

vector table resides at the top of the next 256-byte block.

Thus, if the VIS instruction is located somewhere between

00FF and 01DF Hex (the usual case), the vector table is lo-

cated between addresses 01E0 and 01FF Hex. If the VIS in-

struction is located between 01FF and 02DF Hex, then the

vector table is located between addresses 02E0 and 02FF

Hex, and so on.

An interrupt is an asychronous event which may occur be-

fore, during, or after an instruction cycle. Any interrupt which

occurs during the execution of an instruction is not acknowl-

edged until the start of the next normally executed instruction

is to be skipped, the skip is performed before the pending in-

terrupt is acknowledged.

At the start of interrupt acknowledgment, the following ac-

tions occur:

1. The GIE bit is automatically reset to zero, preventing any

subsequent maskable interrupt from interrupting the cur-

rent service routine. This feature prevents one maskable

interrupt from interrupting another one being serviced.

Each vector is 15 bits long and points to the beginning of a

specific interrupt service routine somewhere in the 32 kbyte

memory space. Each vector occupies two bytes of the vector

table, with the higher-order byte at the lower address. The

vectors are arranged in order of interrupt priority. The vector

of the maskable interrupt with the lowest rank is located to

0yE0 (higher-order byte) and 0yE1 (lower-order byte). The

next priority interrupt is located at 0yE2 and 0yE3, and so

forth in increasing rank. The Software Trap has the highest

rank and its vector is always located at 0yFE and 0yFF. The

number of interrupts which can become active defines the

size of the table.

2. The address of the instruction about to be executed is

pushed onto the stack.

3. The program counter (PC) is loaded with 00FF Hex,

causing a jump to that program memory location.

The device requires seven instruction cycles to perform the

actions listed above.

If the user wishes to allow nested interrupts, the interrupts

service routine may set the GIE bit to 1 by writing to the PSW

register, and thus allow other maskable interrupts to interrupt

the current service routine. If nested interrupts are allowed,

caution must be exercised. The user must write the program

in such a way as to prevent stack overflow, loss of saved

context information, and other unwanted conditions.

Table 10 shows the types of interrupts, the interrupt arbitra-

tion ranking, and the locations of the corresponding vectors

in the vector table.

The vector table should be filled by the user with the memory

locations of the specific interrupt service routines. For ex-

The interrupt service routine stored at location 00FF Hex

should use the VIS instruction to determine the cause of the

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36

gram context (A, B, X, etc.) and executing the RETI instruc-

tion, an interrupt service routine can be terminated by return-

ing to the VIS instruction. In this case, interrupts will be

serviced in turn until no further interrupts are pending and

the default VIS routine is started. After testing the GIE bit to

ensure that execution is not erroneous, the routine should

restore the program context and execute the RETI to return

to the interrupted program.

Interrupts (Continued)

ample, if the Software Trap routine is located at 0310 Hex,

then the vector location 0yFE and -0yFF should contain the

data 03 and 10 Hex, respectively. When a Software Trap in-

terrupt occurs and the VIS instruction is executed, the pro-

gram jumps to the address specified in the vector table.

The interrupt sources in the vector table are listed in order of

rank, from highest to lowest priority. If two or more enabled

and pending interrupts are detected at the same time, the

one with the highest priority is serviced first. Upon return

from the interrupt service routine, the next highest-level

pending interrupt is serviced.

This technique can save up to fifty instruction cycles (t

_c), or

more, (50 µs at 10 MHz oscillator) of latency for pending in-

terrupts with a penalty of fewer than ten instruction cycles if

no further interrupts are pending.

To ensure reliable operation, the user should always use the

VIS instruction to determine the source of an interrupt. Al-

though it is possible to poll the pending bits to detect the

source of an interrupt, this practice is not recommended. The

use of polling allows the standard arbitration ranking to be al-

tered, but the reliability of the interrupt system is compro-

mised. The polling routine must individually test the enable

and pending bits of each maskable interrupt. If a Software

Trap interrupt should occur, it will be serviced last, even

though it should have the highest priority. Under certain con-

ditions, a Software Trap could be triggered but not serviced,

resulting in an inadvertent “locking out” of all maskable inter-

rupts by the Software Trap pending flag. Problems such as

this can be avoided by using VIS instruction.

If the VIS instruction is executed, but no interrupts are en-

abled and pending, the lowest-priority interrupt vector is

used, and a jump is made to the corresponding address in

the vector table. This is an unusual occurrence, and may be

the result of an error. It can legitimately result from a change

in the enable bits or pending flags prior to the execution of

the VIS instruction, such as executing a single cycle instruc-

tion which clears an enable flag at the same time that the

pending flag is set. It can also result, however, from inadvert-

ent execution of the VIS command outside of the context of

an interrupt.

The default VIS interrupt vector can be useful for applica-

tions in which time critical interrupts can occur during the

servicing of another interrupt. Rather than restoring the pro-

TABLE 10. Interrupt Vector Table

Interrupt Source Description

Arbitration Rank

Vector Address

1

2

3

4

Software Trap

reserved

INTR Instruction

NMI

0yFE–0yFF

0yFC–0yFD

0yFA–0yFB

0yF8–0yF9

CAN Receive

CAN Error

RBF, RFV set

TERR, RERR set

(transmit/receive)

CAN Transmit

Pin G0 Edge

MICROWIRE/PLUS

SPI Interface

Timer T0

5

6

7

TBE set

0yF6–0yF7

0yF4–0yF5

0yF2–0yF3

External

BUSY Goes Low

SRBF or STBE set

Idle Timer Underflow

receive buffer full

transmit buffer empty

T2A/Underflow

T2B

8

0yF0–0yF1

0yEE–0yEF

0yEC–0yED

0yEA–0yEB

0yE8–0yE9

0yE6–0yE7

0yE4–0yE5

0yE2–0yE3

9

UART

10

11

12

13

14

15

UART

Timer T2

Timer T1

T1A/Underflow

T1B

Timer T1

Port L, Port M;

MIWU

Port L Edge or

Port M Edge

VIS Interrupt

16

Default VIS Interrupt

0yE0–0yE1

Note 17: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad-

dress of a block. In this case, the table must be in the next block.

37

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mains unchanged. The new PC is therefore pointing to the

vector of the active interrupt with the highest arbitration rank-

ing. This vector is read from program memory and placed

into the PC which is now pointed to the 1st instruction of the

service routine of the active interrupt with the highest arbitra-

tion ranking.

Interrupts (Continued)

VIS Execution

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc...) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FA is generated and so forth. If the only active inter-

rupt is software trap, than E0 is generated. This number re-

places the lower byte of the PC. The upper byte of the PC re-

Figure 32 illustrates the different steps performed by the VIS

instruction. Figure 33 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

DS100044-55

FIGURE 32. VIS Operation

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38

Interrupts (Continued)

DS100044-56

FIGURE 33. VIS Flowchart

39

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Interrupts (Continued)

Programming Example: External Interrupt

PSW

CNTRL

RBIT

SBIT

JP

=00EF

=00EE

0,PORTGC

0,PORTGD

IEDG, CNTRL

EXEN, PSW

GIE, PSW

WAIT

; G0 pin configured Hi-Z

; Ext interrupt polarity; falling edge

; Enable the external interrupt

; Set the GIE bit

WAIT:

; Wait for external interrupt

.

.=0FF

VIS

; The interrupt causes a

; branch to address 0FF

; The VIS causes a branch to

;interrupt vector table

.

.=01FA

.ADDRW SERVICE

; Vector table (within 256 byte

; of VIS inst.) containing the ext

; interrupt service routine

.

INT_EXIT:

SERVICE:

RETI

.

RBIT

EXPND, PSW

; Interrupt Service Routine

; Reset ext interrupt pend. bit

.

JP

INT_EXIT

; Return, set the GIE bit

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40

flag; upon return to the first Software Trap routine, the

STPND flag will have the wrong state. This will allow

maskable interrupts to be acknowledged during the servicing

of the first Software Trap. To avoid problems such as this, the

user program should contain the Software Trap routine to

perform a recovery procedure rather than a return to normal

execution.

Interrupts (Continued)

NON-MASKABLE INTERRUPT

Pending Flag

There is a pending flag bit associated with the non-maskable

interrupt, called STPND. This pending flag is not memory-

mapped and cannot be accessed directly by the software.

Under normal conditions, the STPND flag is reset by a

RPND instruction in the Software Trap service routine. If a

programming error or hardware condition (brownout, power

supply glitch, etc.) sets the STPND flag without providing a

way for it to be cleared, all other interrupts will be locked out.

To alleviate this condition, the user can use extra RPND in-

structions in the main program and in the WATCHDOG ser-

vice routine (if present). There is no harm in executing extra

RPND instructions in these parts of the program.

The pending flag is reset to zero when a device Reset oc-

curs. When the non-maskable interrupt occurs, the associ-

ated pending bit is set to 1. The interrupt service routine

should contain an RPND instruction to reset the pending flag

to zero. The RPND instruction always resets the STPND

flag.

Software Trap

The Software Trap is a special kind of non-maskable inter-

rupt which occurs when the INTR instruction (used to ac-

knowledge interrupts) is fetched from program memory and

placed in the instruction register. This can happen in a vari-

ety of ways, usually because of an error condition. Some ex-

amples of causes are listed below.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

If the program counter incorrectly points to a memory loca-

tion beyond the available program memory space, the non-

existent or unused memory location returns zeroes which is

interpreted as the INTR instruction.

If the stack is popped beyond the allowed limit (address 06F

Hex), a 7FFF will be loaded into the PC, if this last location in

program memory is unprogrammed or unavailable, a Soft-

ware Trap will be triggered.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

A Software Trap can be triggered by a temporary hardware

condition such as a brownout or power supply glitch.

The Software Trap has the highest priority of all interrupts.

When a Software Trap occurs, the STPND bit is set. The GIE

bit is not affected and the pending bit (not accessible by the

user) is used to inhibit other interrupts and to direct the pro-

gram to the ST service routine with the VIS instruction. Noth-

ing can interrupt a Software Trap service routine except for

another Software Trap. The STPND can be reset only by the

RPND instruction or a chip Reset.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

The Software Trap indicates an unusual or unknown error

condition. Generally, returning to normal execution at the

point where the Software Trap occurred cannot be done re-

liably. Therefore, the Software Trap service routine should

reinitialize the stack pointer and perform a recovery proce-

dure that restarts the software at some known point, similar

to a device Reset, but not necessarily performing all the

same functions as a device Reset. The routine must also ex-

ecute the RPND instruction to reset the STPND flag. Other-

wise, all other interrupts will be locked out. To the extent pos-

sible, the interrupt routine should record or indicate the

context of the device so that the cause of the Software Trap

can be determined.

INTERRUPT SUMMARY

The device uses the following types of interrupts, listed be-

low in order of priority:

1. The Software Trap non-maskable interrupt, triggered by

the INTR (00 opcode) instruction. The Software Trap is

acknowledged immediately. This interrupt service rou-

tine can be interrupted only by another Software Trap.

The Software Trap should end with two RPND instruc-

tions followed by a restart procedure.

2. Maskable interrupts, triggered by an on-chip peripheral

block or an external device connected to the device. Un-

der ordinary conditions, a maskable interrupt will not in-

If the user wishes to return to normal execution from the

point at which the Software Trap was triggered, the user

must first execute RPND, followed by RETSK rather than

RETI or RET. This is because the return address stored on

the stack is the address of the INTR instruction that triggered

the interrupt. The program must skip that instruction in order

to proceed with the next one. Otherwise, an infinite loop of

Software Traps and returns will occur.

terrupt any other interrupt routine in progress.

maskable interrupt routine in progress can be inter-

rupted by the non-maskable interrupt request.

maskable interrupt routine should end with an RETI in-

struction or, prior to restoring context, should return to

execute the VIS instruction. This is particularly useful

when exiting long interrupt service routiness if the time

between interrupts is short. In this case the RETI instruc-

tion would only be executed when the default VIS rou-

tine is reached.

A

Programming a return to normal execution requires careful

consideration. If the Software Trap routine is interrupted by

another Software Trap, the RPND instruction in the service

routine for the second Software Trap will reset the STPND

41

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shift register (SIO) with serial data input (SI), serial data out-

put (SO) and serial shift clock (SK). Figure 34 shows a block

diagram of the MICROWIRE/PLUS logic.

Detection of Illegal Conditions

The device can detect various illegal conditions resulting

from coding errors, transient noise, power supply voltage

drops, runaway programs, etc.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS ar-

rangement with the internal clock source is called the Master

mode of operation. Similarly, operating the MICROWIRE/

PLUS arrangement with an external shift clock is called the

Slave mode of operation.

Reading of underfined ROM gets zeros. The opcode for soft-

ware interrupt is zero. If the program fetches instructions

from undefined ROM, this will force a software interrupt, thus

signaling that an illegal condition has occurred.

The subroutine stack grows down for each call (jump to sub-

routine), interrupt, or PUSH, and grows up for each return or

POP. The stack pointer is initialized to RAM location 02F Hex

during reset. Consequently, if there are more returns than

calls, the stack pointer will point to addresses 030 and 031

Hex (which are undefined RAM). Undefined RAM from ad-

dress 030 to 03F Hex is read as all 1’s, which in turn will

cause the program to return to address 7FFF Hex. This is an

undefined ROM location and the instruction fetched (all 0’s)

from this location will generate a software interrupt signaling

an illegal condition.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the mas-

ter mode the SK clock rate is selected by the two bits, SL0

and SL1, in the CNTRL register. Table 11 details the different

clock rates that may be selected.

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave. Figure 35 shows how

two COP888 family microcontrollers and several peripherals

may be interconnected using the MICROWIRE/PLUS ar-

rangements.

Thus, the chip can detect the following illegal conditions:

1. Executing from undefined ROM.

2. Over “POP”ing the stack by having more returns than

calls.

When the software interrupt occurs, the user can re-initialize

the stack pointer and do a recovery procedure before restart-

ing (this recovery program is probably similar to that follow-

ing reset, but might not contain the same program initializa-

tion procedures).

WARNING:

The SIO register should only be loaded when the SK clock is

low. Loading the SIO register while the SK clock is high will

result in undefined data in the SIO register. SK clock is nor-

mally low when not shifting.

MICROWIRE/PLUS

MICROWIRE/PLUS is a serial synchronous communications

interface. The MICROWIRE/PLUS capability enables the de-

vice to interface with any of National Semiconductor’s MI-

CROWIRE peripherals (i.e., A/D converters, display drivers,

E2PROMs etc.) and with other microcontrollers which sup-

port the MICROWIRE interface. It consists of an 8-bit serial

Setting the BUSY flag when the input SK clock is high in the

MICROWIRE/PLUS slave mode may cause the current SK

clock for the SIO shift register to be narrow. For safety, the

BUSY flag should only be set when the input SK clock is low.

DS100044-36

FIGURE 34. MICROWIRE/PLUS Block Diagram

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42

MICROWIRE/PLUS (Continued)

DS100044-37

FIGURE 35. MICROWIRE/PLUS Application

MICROWIRE/PLUS Master Mode Operation

Alternate SK Phase Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE

Master always initiates all data exchanges. The MSEL bit in

the CNTRL register must be set to enable the SO and SK

functions onto the G Port. The SO and SK pins must also be

selected as outputs by setting appropriate bits in the Port G

configuraiton register. Table 11 summarizes the bit settings

required for Master or Slave mode of operation.

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK is normally low. In the normal mode

data is shifted in on the rising edge of the SK clock and the

data is shifted out on the falling edge of the SK clock. The

SIO register is shifted on each falling edge of the SK clock in

the normal mode. In the alternate SK phase mode the SIO

register is shifted on the rising edge of the SK clock.

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configura-

tion bit. The SKSEL flag will power up in the reset condition,

selecting the normal SK signal.

TABLE 11. MICROWIRE/PLUS Master Mode

Clock Selection

SL1

0

SL0

SK

0

1

x

2 X t_c

4 X t_c

8 X t_c

0

1

TABLE 12. MICROWIRE/PLUS Mode Selection

This table assumes that the control flag MSEL is set.

Where t_cis the instruction cycle clock

MICROWIRE/PLUS Slave Mode Operation

G4

G5

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and re-

setting the appropriate bit in the Port G configuration regis-

ter. Table 12 summarizes the settings required to enter the

Slave mode of operation.

(SO)

(SK)

G4

Fun.

G5

Fun.

Operation

Config. Config.

Bit

1

SO

Int. SK MICROWIRE/

PLUS Master

0

1

TRI-STATE Int. SK MICROWIRE/

PLUS Master

The user must set the BUSY flag immediately upon entering

the Salve mode. This will ensure that all data bits sent by the

Master will be shifted properly. After eight clock pulses the

BUSY flag will be cleared and the sequence may be re-

peated.

1

0

SO

Ext. SK MICROWIRE/

PLUS Slave

TRI-STATE Ext. SK MICROWIRE/

PLUS Slave

43

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Serial Peripheral Interface

DS100044-38

FIGURE 36. SPI Transmission Example

The Serial Peripheral Interface (SPI) is used in master-slave

bus systems. It is a synchronous bidirectional serial commu-

nication interface with two data lines MISO and MOSI (Mas-

ter In Slave Out, Master Out Slave In). A serial clock and a

slave select (SS) signal are always generated by the SPI

Master. The interface receives/transmits protocol frames

with up to 12 bytes length within a frame, where a frame is

defined as the time between a falling edge and a rising edge

of SS.

(ESS[7:0]) or as host programmable general purpose sig-

nals. The SS-Expander is programmed with the content of

the first MOSI-byte (i.e., the content of the 1st byte [7:0] ap-

pears at ESS[7:0]) (N-port[7:0]), respectively), if the ESS

programming mode is selected. The ESS programming

mode is selected by the condition MOSI = L at the falling

edge of SS.

Use of the ESS expander requires the setup of four condi-

tions by the user.

1. Set the SESSEN bit of SPICNTL.

THEORY OF OPERATION

2. Set PORTNX to select which bits are used for SS expan-

sion.

Figure 38 shows a block diagram illustrating the basic opera-

tion of the SPI circuit. In the SPI interface, data is

transmitted/received in packets of 8 bits length which are

shifted into/out of a shift register with the active edge of the

shift clock SCK. Two 12 byte FIFOs, which serve as a re-

ceive and a transmit buffer, allow a maximum message

length of 12 x 8 bits in both transmit and receive direction

without CPU intervention. With CPU intervention, many

more bytes can be received. Two registers, the SPI Control

Register (SPICNTL) and the SPI Status Register (SPISTAT),

are used to control the SPI interface via the internal COP

bus. Several different operation modes, such as master or

slave operation, are possible.

3. Configure the PORTNC register to enable the desired

SS expansion bits as outputs.

4. Have an ESS condition (MOSI = low at the falling edge

of SS).

Loop Back Mode

Setting the SLOOP bit enables the Loop Back mode, which

can be used for test purposes. If the Loop Back mode is se-

lected, TX FIFO data are communicated to the RX FIFO via

the SPI Register. In the slave mode, MISO output is inter-

nally connected to the MOSI input. In the master mode, the

MOSI output is internally connected to the MISO input.

An SS-Expander allows the generation of up to 8 signals on

the N-port, which can be used as additional SS-signals

DS100044-39

FIGURE 37. Loop Back Mode Block Diagram

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44

Serial Peripheral Interface (Continued)

DS100044-40

FIGURE 38. SPI Block Diagram

The SPIU Control Register

TABLE 13. SPI Control (SPICNTL) (0098)

Bit 7

Bit 6

STIE

0

Bit 5

SESSEN

0

Bit 4

Bit 3

Bit 2

SCE

0

Bit 1

Bit 0

SRIE

0

SPIMOD[1:0]

SPIEN SLOOP

0

B7

B6

B5

SRIE

SPI Receive Interrupt Enable

0—disable receive interrupt

0—enable receive interrupt

STIE

SPI Transmit buffer Interrupt Enable

0—disable transmit buffer interrupt

0—enable transmit buffer interrupt

SPI SS Expander (ESS) enable

SESSEN

0—The detection of the ESS programming mode is disabled, i.e., the value of MOSI at the falling

edge of SS is “don’t care”.

1—ESS programming mode detection is enabled, i.e., if the condition “MOSI = 0 at the falling edge

of SS” occurs, the SS-Expander is selected and bits [7:0] of the first transmitted byte determine the

state of the N-port (ESS[7:0]). ESS[7:0] will go 1 at the positive edge of SS.

45

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Serial Peripheral Interface (Continued)

B[4:3]

SPIMOD[1:0] SPI operation mode select

SPIMOD[1:0]

0 0: Slave mode,

—SCK is SPI clock input

—MISO is SPI data output

—MOSI is SPI data input

—SS is slave select input

1 0: Standard Master mode,

—SCK is SPI clock output (CKI/40)

—MISO is SPI data input

—MOSI is SPI data output

—SS is slave select output

In the Master mode, 3 different SPI clock frequencies are available:

0 1: f_SCK= 1/(t_c) = CKI/10

1 0: f_SCK= 1/(4 t_c) = CKI/40

1 1: f_SCK= 1/(16 t_c) = CKI/160

B2

B1

SCE

SPI active clock edge select

0: data are shifted out on the falling edge of SCK and are shifted in on the rising edge of SCK

1: data are shifted out on the rising edge of SCK and are shifted in on the falling edge of SCK

SPI enable

SPIEN

Enables the SPI interface and the alternate functions of the MISO, MOSI, SCK and SS pins.

0: disable SPI

1: enable SPI, all Port M ESS signals are set to 1

SPI loop back mode

B0

SLOOP

0: disable loop back mode

1: enable loop back mode, MISO and MOSI are internally connected (see Figure 39)

PROGRAMMING THE SPI EXPANDER

The selected N-port bits will be set to 1 after the positive

edge of SS.

If the SS Expander is enabled by setting SESSEN = 1 in the

SPI Control Register (SPICNTL), the N-port will be pro-

grammed with the content of the first MOSI-byte (i.e., the

content of the 1st byte [7:0] appears at N-port[7:0] after com-

plete reception of the first byte), if the ESS programming

mode is detected. If any bytes follow after the 1st MOSI byte,

all data will be ignored by the SPI.

Single N-port bits may be enabled for use as SS expansion,

or disabled to allow for general purpose I/O, by the respec-

tive bits in the PORTNX register.

The ESS programming mode is detected by the ESS control

logic, which decodes the condition “MOSI = L at the falling

edge of SS. For further details, see Figure 39.

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46

Serial Peripheral Interface (Continued)

DS100044-41

FIGURE 39. Programming the SPI Expander

DS100044-42

SESSEN = 1, SCE = 0. If MOSI = 0 at the falling edge of SS, the ESS programming

mode is detected and all N-port alternate functions are enabled.

FIGURE 40. Programming the SS Expander

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SPI Status Register

DS100044-43

a) Slave mode; rising SCK edge is active edge. (SPIMOD[1,0] = [0,0], SCE = 0)

DS100044-44

b) Slave mode; falling SCK edge is active edge. (SPIMOD[1,0] = [0,0], SCE = 1)

FIGURE 41. Slave Mode Communication

DS100044-45

a) Master mode; rising SCK edge is active edge. (SPIMOD[1,0] = [1,0], SCE = 0)

DS100044-46

b) Master mode; falling SCK edge is active edge. (SPIMOD[1,0] = [1,0], SCE = 1)

FIGURE 42. Master Mode Communication

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48

SPI Status Register (Continued)

TABLE 14. SPI Status Register (SPISTAT) (0099)

Bit 7

Bit 6

Bit 5

STBF

1

Bit 4

STBE

1

Bit 3

Bit 2

Bit 1

Bit 0

SRORN SRBNE

STFL SESSDET

x

0

The SPI Status Register is a read only register.

B7

SRORN

SPI receiver overrun.

This bit is set on the attempt to overwrite valid data in the RX FIFO by the SPI interface. (The condition to

detect this is: SRWP = SRRP & COP has not read the data at SRRP and attempting to write to the RX FIFO

by the SPI interface.) This bit can generate a receive interrupt if the receive interrupt is enabled (SRIE = 1).

(Notes 18, 19, 20)

B6

B5

SRBNE

STBF

SPI Receive buffer not empty

This bit is set with a write to the SPI RX FIFO resulting in SRWP ! = SRRP (caution at rollover!). This bit is

reset with the read of the SPIRXD register resulting in SRWP to be equal to SRRP.

This bit can generate a receive interrupt if enabled with the RIE bit.

SPI Transmit buffer full

This bit is set after a write operation to the SPITXD register (from the COP side), which results in STRP =

STWP. It gets reset as soon as the STRP gets incremented - by the SPI if reading data out of the TX FIFO.

B4

B3

STBE

STFL

SPI transmit buffer empty

This bit is set after the last bit of the a read from the SPITXD register, which results in STRP = STWP. It gets

reset as soon as the STWP gets incremented - by the COP if writing data into the TX FIFO. It is set on reset.

SPI Transmit buffer flush

This bit indicates that the contents of the transmit buffer got discharged by the SS signal becoming high

before all data in the transmit buffer could be transmitted. This bit gets set if the SS signal gets high and

1.STRP ! = STWP or

2.STRP = STWP and the current byte has not been completely transmitted from the SPI shift register

These conditions will reset STRP and STWP to 0. These are virtual pointers and cannot be viewed. (Note 21)

SPI SS Expander detection

B2

SESSDET

This bit indicates the detection of a SS expand condition (MOSI = 0 at the falling edge of SS) immediately

after the N-port has been programmed (8th SCK bit, 8 µs at SCK = 1 MHz).

This bit is reset at the rising edge of SS.

1: SS expand condition detected.

0: normal communication. (Note 22)

Reserved

B1

B0

Reserved

Note 18: At this condition the write operation will not be executed and all data get lost.

Note 19: The SRORN bit stays set until the reset condition.

This bit is reset with a dummy write to the SPISTAT register. (As the register is read only a dummy write does not have any effect on any other bits in this register.)

As a result of the SRORN condition, the SRWP becomes frozen (i.e., does not change until the SRORN bit is reset) and the SPI will not store any new data in the

RX FIFO.

Note 20: With the SRRP being still available, the user can read the data in the RX FIFO before resetting the SRORN bit.

Note 21: STRP = STWP & STBE = 1 will generate an interrupt.

This bit gets reset with a write to the SPITXD register.

Note 22: The SPI master must hold SS = 0 long enough to allow the device to read SESSDET. Otherwise the SESSDET information will get lost.

49

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the STWP location and increment the STWP afterwards. A

read from the controller to this register will read the TX FIFO

at the current STWP location. The pointer is not changed.

SPI Status Register (Continued)

SPI SYNCHRONIZATION

After the SPI is enabled (SPIEN = 1), the SPI internal re-

ceive and transmit shift clock is kept disabled until SS be-

comes inactive. This includes SS being active at the time

SPIEN is set, i.e., no receive/transmit is possible until SS

becomes inactive after enabling the SPI.

Writing data into this register will start a transmission of data

in the master mode.

Note: No read modify write instructions should be used on this register.

Reading this register from the SPI side will read the byte at

the current STRP location and afterwards increment STRP.

HALT/IDLE MODE

SPI RX FIFO

If the device enters the HALT/IDLE mode, both RX and TX

FIFOs get reset (Flushed). If the device is exiting HALT/

IDLE mode, and SPI synchronization takes place as de-

scribed above. SPIRXD and SPITXD have the same state

as after Reset, SPISTAT bits after HALT/IDLE mode are:

The SPI RX FIFO is a 12 byte first in first out buffer. SPI RX

FIFO data are read from the controller by reading the

SPIRXD register. A pointer (SRRP) controls the controller

read location. Data is written to this register by the SPI inter-

face. The write location is controlled by the SRWP. SRWP is

incremented after data is stored to the FIFO SRWP is never

SRORN:

SRBNE:

STBF:

unchanged

→

decremented SRWP has a roll-over 10

11

0

1

0

1

→

2

etc. It is a circularly linked list.

SRRP is incremented after data is read from the FIFO SRRP

STBE:

→

0

is never decremented SRRP has a roll-over 10

11

STFL:

→

1

2

etc. It is a circularly linked list.

SESSDET: x (depending on SS and MOSI line)

Both pointers are cleared at reset.

The following bits indicate the status of the RX FIFO:

SRBNE = (SRWP != SRRP) and !SRORN .SRORN is set at

(SRWP = SRRP) and after a write from the SPI side, reset at

write to SPISTAT.

TRANSMISSION START IN MASTER MODE

The transmission of data in the Master mode is started if

the user controlled SS signal is switched active. No SCK

will be generated in Master mode and thus no data is

transmitted if the SS signal is kept high, i.e., SS must be

switched low to generate SCK. Resetting the SS signal in

the Master mode will immediately stop the transmission

and flush the transmit FIFO. Thus, the user must only re-

set the SS if:

Special conditions: if .SRORN is set, no writes to the RX

FIFO are allowed from the SPI side. SRWP is frozen. Reset-

ting. SRORN (after it was set) clears both SRWP and SRRP.

To prevent erroneous clearing of the Receive FIFO when en-

tering HALT/IDLE mode, the user needs to enable the MIWU

or port M3 (SS) by setting bit 3 in MWKEN register.

1. TBE is set or

2. SCK is high (SCE = 0) or low (SCE = 1)

SPI TX FIFO

The SPI TX FIFO is a 12 byte first in first out buffer. Data is

written to the FIFO by the controller executing a write instruc-

tion to the SPITXD register. A pointer (STWP) controls the

controller write location. Data is read from this register by the

SPI interface. The read location is controlled by the STRP.

STRP is incremented after data is read from the FIFO STRP

TX AND RX FIFO

If the SPI is disabled (SPIEN = 0), all SPI FIFO related

pointers are reset and kept at zero until the SPI is enabled

again. Also, the Read/Write operation to both SPITXD and

SPIRXD will not cause the pointers to change, if SPIEN is

set, Read operations from the RXFIFO and Write opera-

tion to TXFIFO will increment the respective Read/Write

pointers.

→

is never decremented STRP has a roll-over 10

11

0

→

1

2

etc. It is a circularly linked list.

STWP is incremented after data is written to the FIFO STWP

→

0

is never decremented STWP has a roll-over 10

11

SPIRXD SPI Receive Data Register

→

1

2

etc. It is a circularly linked list.

SPIRXD is at address location “009A”. It is a read/write

register.

Both pointers are cleared at reset.

The following bits indicate the status of the TX FIFO: STBF

= set at (STRP = STWP) after a write from the controller re-

set at ((STRP != STWP) I STBE) after a read from the SPI

STBE = (STRP = STWP) after a read from the SPI.

This register holds the receive data at the current SRRP

location: a COP read operation from this register to the ac-

cumulator will read the RX FIFO at the SRRP location and

increment SRRP afterwards. A write to this register (by the

controllers SW) will write to the RX FIFO at the current

SRRP location. The SRRP is not changed.

Special conditions: If the SS signal becomes high before

data the last bit of the last byte in the TX FIFO is transmitted

both STRP and STWP will be set to 0. The STFL bit will be

set. (STBE will be set as well.)

Note: The SRRP, SRWP, STRP and STWP registers are not available to the

user. Their operation description is included for clarity and to enhance

the user’s understanding.

Note: During breakpoint the SRRP is not incremented.

A write to this register from the SPI interface side will write to

the current SRWP location and increment SRWP afterwards.

SPITXD SPI Transmit Data Register

SPITXD is at address location “009B”. It is a read/write reg-

ister.

A/D Converter

The device contains an 8-channel, multiplexed input, suc-

cessive approximation, Analog-to Digital converter. The de-

vice’s VCC and GND pins are used for voltage reference.

This register holds the transmit data at the current STWP lo-

cation: a write from the controller to this register will write to

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50

Differential mode:

A/D Converter (Continued)

Bit 7

Bit 6

Bit 5

Channel Pairs (+, −)

OPERATING MODES

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0, 1

1, 0

2, 3

3, 2

4, 5

5, 4

6, 7

7, 6

The A/D converter supports ratiometric measurements. It

supports both Single Ended and Differential modes of opera-

tion.

Four specific analog channel selection modes are sup-

ported. These are as follows:

Allow any specific channel to be selected at one time. The

A/D converter performs the specific conversion requested

and stops.

Allow any specific channel to be scanned continuously. In

other words, the user specifies the channel and the A/D con-

verter scans it continuously. At any arbitrary time the user

can immediately read the result of the last conversion. The

user must wait for only the first conversion to complete.

MODE SELECT

This 2-bit field is used to select the mode of operation (single

conversion, continuous conversions, differential, single

ended) as shown in the following table.

Allow any differential channel pair to be selected at one time.

The A/D converter performs the specific differential conver-

sion requested and stops.

Bit 4

Bit 3

Mode

0

Single Ended mode, single

conversion

Allow any differential channel pair to be scanned continu-

ously. In other words, the user specifies the differential chan-

nel pair and the A/D converter scans it continuously. At any

arbitrary time the user can immediately read the result of the

last differential conversion. The user must wait for only the

first conversion to complete.

0

1

Single Ended mode, continuous scan

of a single channel into the result

register

1

0

1

Differential mode, single conversion

The A/D converter is supported by two memory mapped reg-

isters, the result register and the mode control register.

When the device is reset, the mode control register (ENAD)

is cleared, the A/D is powered down and the A/D result reg-

ister has unknown data.

Differential mode, continuous scan of

a channel pair into the result register

PRESCALER SELECT

This 2-bit field is used to select one of the four prescaler

clocks for the A/D converter. The following table shows the

various prescaler options.

A/D Control Register

A/D Converter Clock Prescale

The ENAD control register contains 3 bits for channel selec-

tion, 2 bits for prescaler selection, 2 bits for mode selection

and a Busy bit. An A/D conversion is initiated by setting the

ADBSY bit in the ENAD control register. The result of the

conversion is available to the user in the A/D result register,

ADRSLT, when ADBSY is cleared by the hardware on

completion of the conversion.

Bit 2

Bit 1

Clock Select

Divide by 2

Divide by 4

Divide by 6

Divide by 12

0

1

0

1

0

1

ENAD (Address 0xCB)

BUSY BIT

CHANNEL

SELECT

MODE

PRESCALER

SELECT

BUSY

The ADBSY bit of the ENAD register is used to control start-

ing and stopping of the A/D conversion. When ADBSY is

cleared, the prescale logic is disabled and the A/D clock is

turned off. Setting the ADBSY bit starts the A/D clock and ini-

tiates a conversion based on the mode select value currently

in the ENAD register. Normal completion of an A/D conver-

sion clears the ADBSY bit and turns off the A/D converter.

SELECT

ADCH2 ADCH1 ADCH0 ADMOD1 ADMOD0 PSC1 PSC0 ADBSY

Bit 7

Bit 0

CHANNEL SELECT

This 3-bit field selects one of eight channels to be the V_IN+

The mode selection determines the V_IN−input.

.

Single Ended mode:

The ADBSY bit remains a one during continuous conversion.

The user can stop continuous conversion by writing a zero to

the ADBSY bit.

Bit 7

Bit 6

Bit 5

Channel No.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

If the user wishes to restart a conversion which is already in

progress, this can be accomplished only by writing a zero to

the ADBSY bit to stop the current conversion and then by

writing a one to ADBSY to start a new conversion. This can

be done in two consecutive instructions.

ADC Operation

The A/D converter interface works as follows. Setting the

ADBSY bit in the A/D control register ENAD initiates an A/D

conversion. The conversion sequence starts at the begin-

ning of the write to ENAD operation which sets ADBSY, thus

powering up the A/D. At the first falling edge of the converter

clock following the write operation, the sample signal turns

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The 17 A/D clock cycles needed for conversion consist of 1

cycle at the beginning for reset, 7 cycles for sampling, 8

cycles for converting, and 1 cycle for loading the result into

the A/D result register (ADRSLT). This A/D result register is a

read-only register. The user cannot write into ADRSLT.

A/D Converter (Continued)

on for seven clock cycles. If the A/D is in single conversion

mode, the conversion complete signal from the A/D will gen-

erate a power down for the A/D converter and will clear the

ADBSY bit in the ENAD register at the next instruction cycle

boundary. If the A/D is in continuous mode, the conversion

complete signal will restart the conversion sequence by de-

selecting the A/D for one converter clock cycle before start-

ing the next sample. The A/D 8-bit result is immediately

loaded into the A/D result register (ADRSLT) upon comple-

tion. Internal logic prevents transient data (resulting from the

A/D writing a new result over an old one) being read from

ADRSLT.

The ADBSY flag provides an A/D clock inhibit function, which

saves power by powering down the A/D when it is not in use.

Note: The A/D converter is also powered down when the device is in either

the HALT or IDLE modes. If the A/D is running when the device enters

the HALT or IDLE modes, the A/D powers down and then restarts the

conversion with a corrupted sampled voltage (and thus an invalid re-

sult) when the device comes out of the HALT or IDLE modes.

Analog Input and Source Resistance Considerations

Figure 43 shows the A/D pin model in single ended mode.

The differential mode has a similar A/D pin model. The leads

to the analog inputs should be kept as short as possible.

Both noise and digital clock coupling to an A/D input can

cause conversion errors. The clock lead should be kept

away from the analog input line to reduce coupling. The A/D

channel input pins do not have any internal output driver cir-

cuitry connected to them because this circuitry would load

the analog input signals due to output buffer leakage current.

Inadvertent changes to the ENAD register during conversion

are prevented by the control logic of the A/D. Any attempt to

write any bit of the ENAD Register except ADBSY, while

ADBSY is a one, is ignored. ADBSY must be cleared either

by completion of an A/D conversion or by the user before the

prescaler, conversion mode or channel select values can be

changed. After stopping the current conversion, the user can

load different values for the prescaler, conversion mode or

channel select and start a new conversion in one instruction.

Source impedances greater than 3 kΩ on the analog input

lines will adversely affect the internal RC charging time dur-

ing input sampling. As shown inFigure 43, the analog switch

to the DAC array is closed only during the 7 A/D cycle

sample time. Large source impedances on the analog inputs

may result in the DAC array not being charged to the correct

voltage levels, causing scale errors.

It is important for the user to realize that, when used in differ-

ential mode, only the positive input to the A/D converter is

sampled and held. The negative input is constantly con-

nected and should be held stable for the duration of the con-

version. Failure to maintain a stable negative input will result

in incorrect conversion.

If large source resistance is necessary, the recommended

solution is to slow down the A/D clock speed in proportion to

the source resistance. The A/D converter may be operated

at the maximum speed for R_Sless than 3 kΩ. For R_Sgreater

than 3 kΩ, A/D clock speed needs to be reduced. For ex-

ample, with R_S= 6 kΩ, the A/D converter may be operated

at half the maximum speed. A/D converter clock speed may

be slowed down by either increasing the A/D prescaler

divide-by or decreasing the CKI clock frquency. The A/D

minimum clock speed is 100 kHz.

PRESCALER

The A/D Converter (A/D) contains a prescaler option that al-

lows four different clock selections. The A/D clock frequency

is equal to CKI divided by the prescaler value. Note that the

prescaler value must be chosen such that the A/D clock falls

within the specified range. The maximum A/D frequency is

1.67 MHz. This equates to a 600 ns A/D clock cycle.

The A/D converter takes 17 A/D clock cycles to complete a

conversion. Thus the minimum A/D conversion time for the

device is 10.2 µs when a prescaler of 6 has been selected.

DS100044-62

*

The analog switch is closed only during the sample time.

FIGURE 43. A/D Pin Model (Single Ended Mode)

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52

Other functions of the ENUR register include saving the

ninth bit received in the data frame, enabling or disabling the

USART’s attention mode of operation and providing addi-

tional receiver/transmitter status information via RCVG and

XMTG bits. The determination of an internal or external clock

source is done by the ENUI register, as well as selecting the

number of stop bits and enabling or disabling transmit and

receive interrupts. A control flag in this register can also se-

lect the USART mode of operation: asynchronous or

synchronous.

USART

The device contains a full-duplex software programmable

USART. The USART Figure 44 consists of a transmit shift

register, a receiver shift register and seven addressable reg-

isters, as follows: a transmit buffer register (TBUF), a re-

ceiver buffer register (RBUF), a USART control and status

register (ENU), a USART receive control and status register

(ENUR), a USART interrupt and clock source register

(ENUI), a prescaler select register (PSR) and baud (BAUD)

register. The ENU register contains flags for transmit and re-

ceive functions; this register also determines the length of

the data frame (7, 8 or 9 bits), the value of the ninth bit in

transmission, and parity selection bits. The ENUR register

flags framing, data overrun and parity errors while the US-

ART is receiving.

DS100044-48

FIGURE 44. USART Block Diagram

53

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DOE = 0

DOE = 1

Indicates no Data Overrun Error has been de-

tected since the last time the ENUR register

was read.

USART (Continued)

USART CONTROL AND STATUS REGISTERS

The operation of the USART is programmed through three

registers: ENU, ENUR and ENUI.

Indicates the occurrence of a Data Overrun Er-

ror.

FE: Flags a Framing Error. Read only, cleared on read,

cleared on reset.

DESCRIPTION OF USART REGISTER BITS

ENU-USART Control and Status Register (Address at

0BA)

FE = 0

Indicates no Framing Error has been detected

since the last time the ENUR register was read.

PEN PSEL1 XBIT9/ CHL1

CHL0

ERR

RBFL TBMT

FE = 1

Indicates the occurrence of a Framing Error.

PSEL0

PE: Flags a Parity Error. Read only, cleared on read, cleared

on reset.

Bit 7

Bit 0

PE = 0

Indicates no Parity Error has been detected since

the last time the ENUR register was read.

PEN: This bit enables/disables Parity (7- and 8-bit modes

only). Read/Write, cleared on reset.

PE = 1

Indicates the occurrence of a Parity Error.

PEN = 0

PEN = 1

Parity disabled.

Parity enabled.

SPARE: Reserved for future use. Read/Write, cleared on re-

set.

PSEL1, PSEL0: Parity select bits. Read/Write, cleared on

RBIT9: Contains the ninth data bit received when the US-

ART is operating with nine data bits per frame. Read only,

cleared on reset.

reset.

PSEL1 = 0, PSEL0 = 0

PSEL1 = 0, PSEL0 = 1

PSEL1 = 1, PSEL0 = 0

PSEL1 = 1, PSEL0 = 1

Odd Parity (if Parity enabled)

Even Parity (if Parity enabled)

Mark(1) (if Parity enabled)

Space(0) (if Parity enabled)

ATTN: ATTENTION Mode is enabled while this bit is set.

This bit is cleared automatically on receiving a character with

data bit nine set. Read/Write, cleared on reset.

XBIT9/PSEL0: Programs the ninth bit for transmission when

the USART is operating with nine data bits per frame. For

seven or eight data bits per frame, this bit in conjunction with

PSEL1 selects parity. Read/Write, cleared on reset.

XMTG: This bit is set to indicate that the USART is transmit-

ting. It gets reset at the end of the last frame (end of last Stop

bit). Read only, cleared on reset.

RCVG: This bit is set high whenever a framing error occurs

and goes low when RDX goes high. Read only, cleared on

reset.

CHL1, CHL0: These bits select the character frame format.

Parity is not included and is generated/verified by hardware.

Read/Write, cleared on reset.

ENUI-USART Interrupt and Clock Source Register

(Address at 0BC)

CHL1 = 0, CHL0 = 0

CHL1 = 0, CHL0 = 1

The frame contains eight data bits.

The frame contains seven data

bits.

STP2 STP78 ETDX SSEL XRCLK XTCLK

Bit 7

ERI

ETI

Bit 0

CHL1 = 1, CHL0 = 0

CHL1 = 1, CHL0 = 1

The frame contains nine data bits.

STP2: This bit programs the number of Stop bits to be trans-

mitted. Read/Write, cleared on reset.

Loopback Mode selected. Trans-

mitter output internally looped back

to receiver input. Nine bit framing

format is used.

STP2 = 0

STP2 = 1

One Stop bit transmitted.

Two Stop bits transmitted.

ERR: This bit is a global USART error flag which gets set if

any or a combination of the errors (DOE, FE, PE) occur.

Read only; it cannot be written by software, cleared on reset.

STP78: This bit is set to program the last Stop bit to be 7/8th

of a bit in length. Read/Write, cleared on reset.

ETDX: TDX (USART Transmit Pin) is the alternate function

assigned to Port L pin L2; it is selected by setting ETDX bit.

To simulate line break generation, software should reset

ETDX bit and output logic zero to TDX pin through Port L

data and configuration registers. Read/Write, cleared on re-

set.

RBFL: This bit is set when the USART has received a com-

plete character and has copied it into the RBUF register. It is

automatically reset when software reads the character from

RBUF. Read only; it cannot be written by software, cleared

on reset.

TBMT: This bit is set when the USART transfers a byte of

data from the TBUF register into the TSFT register for trans-

mission. It is automatically reset when software writes into

the TBUF register. Read only, bit is set to “one” on reset; it

cannot be written by software.

SSEL: USART mode select. Read/Write, cleared on reset.

SSEL = 0

SSEL = 1

Asynchronous Mode.

Synchronous Mode.

XRCLK: This bit selects the clock source for the receiver

section. Read/Write, cleared on reset.

ENUR-USART Receive Control and Status Register

(Address at 0BB)

XRCLK = 0

XRCLK = 1

The clock source is selected through the

PSR and BAUD registers.

DOE FE PE Reserved RBIT9 ATTN XMTG RCVG

Signal on CKX (L1) pin is used as the clock.

XTCLK: This bit selects the clock source for the transmitter

section. Read/Write, cleared on reset.

Bit 7

Bit 0

Note 23: Bit is reserved for future use. User must set to zero.

XTCLK = 0

The clock source is selected through the

PSR and BAUD registers.

DOE: Flags a Data Overrun Error. Read only, cleared on

read, cleared on reset.

XTCLK = 1

Signal on CKX (L1) pin is used as the clock.

ERI: This bit enables/disables interrupt from the receiver

section. Read/Write, cleared on reset.

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54

character, the contents of the RSFT register are copied into

the RBUF register and the Received Buffer Full Flag (RBFL)

is set. RBFL is automatically reset when software reads the

character from the RBUF register. RBUF is a read only reg-

ister. There is also the RCVG bit which is set high when a

framing error occurs and goes low once RDX goes high.

TBMT, XMTG, RBFL and RCVG are read only bits.

USART (Continued)

ERI = 0

ERI = 1

Interrupt from the receiver is disabled.

Interrupt from the receiver is enabled.

ETI: This bit enables/disables interrupt from the transmitter

section. Read/Write, cleared on reset.

ETI = 0

ETI = 1

Interrupt from the transmitter is disabled.

Interrupt from the transmitter is enabled.

SYNCHRONOUS MODE

In this mode data is transferred synchronously with the

clock. Data is transmitted on the rising edge and received on

the falling edge of the synchronous clock.

Associated I/O Pins

Data is transmitted on the TDX pin and received on the RDX

pin. TDX is the alternate function assigned to Port L pin L2;

it is selected by setting ETDX (in the ENUI register) to one.

RDX is an inherent function of Port L pin L3, requiring no

setup.

This mode is selected by setting SSEL bit in the ENUI regis-

ter. The input frequency to the USART is the same as the

baud rate.

When an external clock input is selected at the CKX pin, data

transmit and receive are performed synchronously with this

clock through TDX/RDX pins.

The baud rate clock for the USART can be generated on-

chip, or can be taken from an external source. Port L pin L1

(CKX) is the external clock I/O pin. The CKX pin can be ei-

ther an input or an output, as determined by Port L Configu-

ration and Data registers (Bit 1). As an input, it accepts a

clock signal which may be selected to drive the transmitter

and/or receiver. As an output, it presents the internal Baud

Rate Generator output.

If data transmit and receive are selected with the CKX pin as

clock output, the device generates the synchronous clock

output at the CKX pin. The internal baud rate generator is

used to produce the synchronous clock. Data transmit and

receive are performed synchronously with this clock.

FRAMING FORMATS

The USART supports several serial framing formats (Figure

45) . The format is selected using control bits in the ENU,

ENUR and ENUI registers.

USART Operation

The USART has two modes of operation; asynchronous

mode and synchronous mode.

The first format (1, 1a, 1b, 1c) for data transmission (CHL0 =

1, CHL1 = 0) consists of Start bit, seven Data bits (excluding

parity) and 7/8, one or two Stop bits. In applications using

parity, the parity bit is generated and verified by hardware.

ASYNCHRONOUS MODE

This mode is selected by resetting the SSEL (in the ENUI

register) bit to zero. The input frequency to the USART is 16

times the baud rate.

The second format (CHL0 = 0, CHL1 = 0) consists of one

Start bit, eight Data bits (excluding parity) and 7/8, one or

two Stop bits. Parity bit is generated and verified by hard-

ware.

The TSFT and TBUF registers double-buffer data for trans-

mission. While TSFT is shifting out the current character on

the TDX pin, the TBUF register may be loaded by software

with the next byte to be transmitted. When TSFT finishes

transmitting the current character the contents of TBUF are

transferred to the TSFT register and the Transmit Buffer

Empty Flag (TBMT in the ENU register) is set. The TBMT

flag is automatically reset by the USART when software

loads a new character into the TBUF register. There is also

the XMTG bit which is set to indicate that the USART is

transmitting. This bit gets reset at the end of the last frame

(end of last Stop bit). TBUF is a read/write register.

The third format for transmission (CHL0 = 0, CHL1 = 1) con-

sists of one Start bit, nine Data bits and 7/8, one or two Stop

bits. This format also supports the USART “ATTENTION”

feature. When operating in this format, all eight bits of TBUF

and RBUF are used for data. The ninth data bit is transmitted

and received using two bits in the ENU and ENUR registers,

called XBIT9 and RBIT9. RBIT9 is a read only bit. Parity is

not generated or verified in this mode.

For any of the above framing formats, the last Stop bit can

be programmed to be 7/8th of a bit in length. If two Stop bits

are selected and the 7/8th bit is set (selected), the second

Stop bit will be 7/8th of a bit in length.

The RSFT and RBUF registers double-buffer data being re-

ceived. The USART receiver continually monitors the signal

on the RDX pin for a low level to detect the beginning of a

Start bit. Upon sensing this low level, it waits for half a bit

time and samples again. If the RDX pin is still low, the re-

ceiver considers this to be a valid Start bit, and the remaining

bits in the character frame are each sampled a single time, at

the mid-bit position. Serial data input on the RDX pin is

shifted into the RSFT register. Upon receiving the complete

The parity is enabled/disabled by PEN bit located in the ENU

register. Parity is selected for 7-bit and 8-bit modes only. If

parity is enabled (PEN = 1), the parity selection is then per-

formed by PSEL0 and PSEL1 bits located in the ENU

register.

55

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USART Operation (Continued)

DS100044-49

FIGURE 45. Framing Formats

Note that the XBIT9/PSEL0 bit located in the ENU register

serves two mutually exclusive functions. This bit programs

the ninth bit for transmission when the USART is operating

with nine data bits per frame. There is no parity selection in

this framing format. For other framing formats XBIT9 is not

needed and the bit is PSEL0 used in conjunction with PSEL1

to select parity.

can be individually enabled or disabled using Enable Trans-

mit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in

the ENUI register.

The interrupt from the Transmitter is set pending, and re-

mains pending, as long as both the TBMT and ETI bits are

set. To remove this interrupt, software must either clear the

ETI bit or write to the TBUF register (thus clearing the TBMT

bit).

The frame formats for the receiver differ form the transmitter

in the number to Stop bits required. The receiver only re-

quires one Stop bit in a frame, regardless of the setting of the

Stop bit selection bits in the control register. Note that an im-

plicit assumption is made for full duplex USART operatioin

that the framing formats are the same for the transmitter and

receiver.

The interrupt from the receiver is set pending, and remains

pending, as long as both the RBFL and ERI bits are set. To

remove this interrupt, software must either clear the ERI bit

or read from the RBUF register (thus clearing the RBFL bit).

Baud Clock Generation

The clock inputs to the transmitter and receiver sections of

the USART can be individually selected to come either from

an external source at the CKX pin (port L, pin L1) or from a

source selected in the PSR and BAUD registers. Internally,

the basic baud clock is created from the oscillator frequency

through a two-stage divider chain consisting of a 1–16 (in-

crements of 0.5) prescaler and an 11-bit binary counter. (Fig-

ure 46) The divide factors are specified through two read/

USART INTERRUPTS

The USART is capable of generating interrupts. Interrupts

are generated on Receive Buffer Full and Transmit Buffer

Empty. Both interrupts have individual interrupt vectors. Two

bytes of program memory space are reserved for each inter-

rupt vector. The two vectors are located at addresses 0xEC

to 0xEF Hex in the program memory space. The interrupts

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56

Baud Clock Generation (Continued)

Prescaler

Select

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Prescaler

Factor

4

write registers shown in Figure 47. Note that the 11-bit Baud

Rate Divisor spills over into the Prescaler Select Register

(PSR). PSR is cleared upon reset.

4.5

5

As shown in Table 15, a Prescaler Factor of 0 corresponds to

NO CLOCK. NO CLOCK condition is the USART power

down mode where the USART clock is turned off for power

saving purpose. The user must also turn the USART clock

off when a different baud rate is chosen.

5.5

6

6.5

7

The correspondences between the 5-bit Prescaler Select

and Prescaler factors are shown in Table 15. There are

many ways to calculate the two divisor factors, but one par-

ticularly effective method would be to achieve a 1.8432 MHz

frequency coming out of the first stage. The 1.8432 MHz

prescaler output is then used to drive the software program-

mable baud rate counter to create a x16 clock for the follow-

ing baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400,

3600, 4800, 7200, 9600, 19200 and 38400 (Table 16). Other

baud rates may be created by using appropriate divisors.

The x16 clock is then divided by 16 to provide the rate for the

serial shift registers of the transmitter and receiver.

7.5

8

8.5

9

9.5

10

10.5

11

11.5

12

TABLE 15. Prescaler Factors

12.5

13

Prescaler

Select

00000

00001

00010

00011

00100

00101

00110

Prescaler

Factor

13.5

14

NO CLOCK

1

1.5

2

14.5

15

15.5

16

2.5

3

3.5

DS100044-50

FIGURE 46. USART BAUD Clock Generation

DS100044-51

FIGURE 47. USART BAUD Clock Divisor Registers

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BR = (5 x 10⁶)/(16 x 5 x 6.5) = 9615.384

Baud Clock Generation (Continued)

*

% error = (9615.385 − 9600)/9600 100 = 0.16

TABLE 16. Baud Rate Divisors

(1.8432 MHz Prescaler Output)

Effect of HALT/IDLE

Baud

Rate

Baud Rate

The USART logic is reinitialized when either the HALT or

IDLE modes are entered. This reinitialization sets the TBMT

flag and resets all read only bits in the USART control and

status registers. Read/Write bits remain unchanged. The

Transmit Buffer (TBUF) is not affected, but the Transmit Shift

register (TSFT) bits are set to one. The receiver registers

RBUF and RSFT are not affected.

Divisor −1 (N-1)

110 (110.03)

134.5 (134.58)

150

1046

855

767

383

191

95

300

The device will exit from the HALT/IDLE modes when the

Start bit of a character is detected at the RDX (L3) pin. This

feature is obtained by using the Multi-Input Wakeup scheme

provided on the device.

600

1200

1800

63

2400

47

Before entering the HALT or IDLE modes the user program

must select the Wakeup source to be on the RXD pin. This

selection is done by setting bit 3 of WKEN (Wakeup Enable)

register. The Wakeup trigger condition is then selected to be

high to low transition. This is done via the WKEDG register.

(Bit 3 is one.)

3600

31

4800

23

7200

15

9600

11

If the device is halted and crystal oscillator is used, the

Wakeup signal will not start the chip running immediately be-

cause of the finite start up time requirement of the crystal os-

cillator. The idle timer (T0) generates a fixed (256 t_c) delay to

ensure that the oscillator has indeed stabilized before allow-

ing the device to execute code. The user has to consider this

delay when data transfer is expected immediately after exit-

ing the HALT mode.

19200

38400

5

2

Note: The entries in Table 16 assume a prescaler output of 1.8432 MHz. In

the asynchronous mode the baud rate could be as high as 625k.

As an example, considering the Asynchronous Mode and a

CKI clock of 4.608 MHz, the prescaler factor selected is:

4.608/1.8432 = 2.5

The 2.5 entry is available in Table 15. The 1.8432 MHz pres-

caler output is then used with proper Baud Rate Divisor

(Table 16) to obtain different baud rates. For a baud rate of

19200 e.g., the entry in Table 16 is 5.

Diagnostic

Bits CHL0 and CHL1 in the ENU register provide a loopback

feature for diagnostic testing of the USART. When these bits

are set to one, the following occur: The receiver input pin

(RDX) is internally connected to the transmitter output pin

(TDX); the output of the Transmitter Shift Register is “looped

back” into the Receive Shift Register input. In this mode,

data that is transmitted is immediately received. This feature

allows the processor to verify the transmit and receive data

paths of the USART.

N − 1 = 5 (N − 1 is the value from Table 16)

N = 6 (N is the Baud Rate Divisor)

Baud Rate = 1.8432 MHz/(16 x 6) = 19200

The divide by 16 is performed because in the asynchronous

mode, the input frequency to the USART is 16 times the

baud rate. The equation to calculate baud rates is given be-

low.

Note that the framing format for this mode is the nine bit for-

mat; one Start bit, nine data bits, and 7/8, one or two Stop

bits. Parity is not generated or verified in this mode.

The actual Baud Rate may be found from:

BR = Fc/(16 X N X P)

Where:

BR is the Baud Rate

Attention Mode

Fc is the CKI frequency

N is the Baud Rate Divisior (Table 16).

The USART Receiver section supports an alternate mode of

operation, referred to as ATTENTION Mode. This mode of

operation is selected by the ATTN bit in the ENUR register.

The data format for transmission must also be selected as

having nine Data bits and either 7/8, one or two Stop bits.

P is the Prescaler Divide Factor selected by the value in the

Prescaler Select Register (Table 15)

Note: In the Synchronous Mode, the divisor 16 is replaced by two.

The ATTENTION mode of operation is intended for use in

networking the device with other processors, Typically in

such environments the messages consists of device ad-

dresses, indicating which of several destinations should re-

ceive them, and the actual data. This Mode supports a

scheme in which addresses are flagged by having the ninth

bit of the data field set to a 1. If the ninth bit is reset to a zero

the byte is a Data byte.

Example:

Asynchronous Mode:

Crystal Frequency = 5 MHz

Desired baud rate = 9600

Using the above equation N X P can be calculated first.

N x P = (5 X 10⁶)/(16 x 9600) = 32.552

Now 32.552 is divided by each Prescaler Factor (Table 15) to

obtain a value closet to an integer. This factor happens to be

6.5 (P = 6.5).

While in ATTENTION mode, the USART monitors the com-

munication flow, but ignores all characters until an address

character is received. Upon receiving an address character,

the USART signals that the character is ready by setting the

RBFL flag, which in turn interrupts the processor if USART

Receiver interrupts are enabled. The ATTN bit is also cleared

N = 32.552/6.5 = 5.008 (N = 5)

The programmed value (from Table 16) should be 4 (N −1).

Using the above values calculated for N and P:

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58

Attention Mode (Continued)

Clock Monitor

The Clock Monitor aboard the device can be selected or de-

selected under program control. The Clock Monitor is guar-

anteed not to reject the clock if the instruction cycle clock

(1/t_c) is greater or equal to 10 kHz. This equates to a clock in-

put rate on CKI of greater or equal to 100 kHz.

automatically at this point, so that data characters as well as

address characters are recognized. Software examines the

contents of the RBUF and responds by deciding either to ac-

cept the subsequent data stream (by leaving the ATTN bit re-

set) or to wait until the next address character is seen (by

setting the ATTN bit again).

WATCHDOG Operation

Operation of the USART Transmitter is not affected by selec-

tion of this Mode. The value of the ninth bit to be transmitted

is programmed by setting XBIT9 appropriately. The value of

the ninth bit received is obtained by reading RBIT9. Since

this bit is located in ENUR register where the error flags re-

side, a bit operation on it will reset the error flags.

The WATCHDOG and Clock Monitor are disabled during re-

set. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

WATCHDOG

The device contains a WATCHDOG and clock monitor. The

WATCHDOG is designed to detect the user program getting

stuck in infinite loops resulting in loss of program control or

“runaway” programs. The Clock Monitor is used to detect the

absence of a clock or a very slow clock below a specified

rate on the CKI pin.

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR reg-

ister involves two irrevocable choices: (i) the selection of the

WATCHDOG service window (ii) enabling or disabling of the

Clock Monitor. Hence, the first write to WDSVR Register in-

volves selecting or deselecting the Clock Monitor, select the

WATCHDOG service window and match the WATCHDOG

key data. Subsequent writes to the WDSVR register will

compare the value being written by the user to the WATCH-

DOG service window value and the key data (bits 7 through

1) in the WDSVR Register. Table 19 shows the sequence of

events that can occur.

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 18 shows the WDSVR register.

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The WATCH-

DOG may not be serviced more than once in every lower

limit of the service window. The user may service the

WATCHDOG as many times as wished in the time period be-

tween the lower and upper limits of the service window. The

first write to the WDSVR Register is also counted as a

WATCHDOG service.

TABLE 17. WATCHDOG Service Register (WDSVR)

Window

Select

X

Key Data

Clock

Monitor

Y

X

0

1

0

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the Port G. WDOUT is active

low. The WDOUT pin is in the high impedance state in the in-

active state. Upon triggering the WATCHDOG, the logic will

pull the WDOUT (G1) pin low for an additonal 16 t_c–32 t_c

cycle after the signal level on WDOUT pin goes below the

lower Schmitt trigger threshold. After this delay, the device

will stop forcing the WDOUT output low.

Bit 7

Bit 0

The lower limit of the service window is fixed at 2048 instruc-

tion cycles. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 18 shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

The WATCHDOG service window will restart when the WD-

OUT pin goes high. It is recommended that the user tie the

WDOUT pin back to V_CCthrough a resistor in order to pull

WDOUT high.

TABLE 18. WATCHDOG Service Window Select

A WATCHDOG service while the WDOUT signal is active will

be ignored. The state of the WDOUT pin is not guaranteed

on reset, but if the powers up low then the WATCHDOG will

time out and WDOUT will enter high impedance state.

WDSVR WDSVR

Clock

Service Window

(Lower-Upper Limits)

2048–8k t_CCycles

Bit 7

Bit 6

Monitor

0

1

x

0

1

0

1

x

0

1

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error. The Clock Monitor error will continue

until the clock frequency has reached the minimum specified

value, after which the G1 output will enter the high imped-

ance TRI-STATE mode following 16 t_c–32 t_cclock cycles.

The Clock Monitor generates a continual Clock Monitor error

if the oscillator fails to start, or fails to reach the minimum

specified frequency. The specification for the Clock Monitor

is as follows:

2048–16k t_CCycles

2048–32k t_CCycles

2048–64k t_CCycles

Clock Monitor Disabled

Clock Monitor Enabled

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

>

1/t_c10 kHz—No clock rejection.

<

1/t_c10 Hz—Guaranteed clock rejection.

59

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•

With the crystal oscillator mask option selected, or with

the single-pin R/C oscillator mask option selected and the

CLKDLY bit set, the WATCHDOG service window will be

set to its selected value from WDSVR following HALT.

Consequently, the WATCHDOG should not be serviced

for at least 2048 instruction cycles following HALT, but

must be serviced within the selected window to avoid a

WATCHDOG error.

WATCHDOG Operation (Continued)

WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the COP888 WATCH-

DOG and CLOCK MONITOR should be noted:

•

Both the WATCHDOG and Clock Monitor detector cir-

cuits are inhibited during RESET.

•

Following RESET, the WATCHDOG and CLOCK MONI-

TOR are both enabled, with the WATCHDOG having the

maximum service window selected.

•

The IDLE timer T0 is not initialized with RESET.

The user can sync in to the IDLE counter cycle with an

IDLE counter (T0) interrupt or by monitoring the T0PND

flag. The T0PND flag is set whenever the thirteenth bit of

the IDLE counter toggles (every 4096 instruction cycles).

The user is responsible for resetting the T0PND flag.

•

The WATCHDOG service window and Clock Monitor

enable/disable option can only be changed once, during

the initial WATCHDOG service following RESET.

The initial WATCHDOG service must match the key data

value in the WATCHDOG Service register WDSVR in or-

der to avoid a WATCHDOG error.

•

A hardware WATCHDOG service occurs just as the de-

vice exits the IDLE mode. Consequently, the WATCH-

DOG should not be serviced for at least 2048 instruction

cycles following IDLE, but must be serviced within the se-

lected window to avoid a WATCHDOG error.

Subsequent WATCHDOG services must match all three

data fields in WDSVR in order to avoid WATCHDOG er-

rors.

Following RESET, the initial WATCHDOG service (where

the service window and the CLOCK MONITOR enable/

disable must be selected) may be programmed any-

where within the maximum service window (65,536 in-

struction cycles) initialized by RESET. Note that this initial

WATCHDOG service may be programmed within the inti-

tial 2048 instruction cycles without causing a WATCH-

DOG error.

The correct key data value cannot be read from the

WATCHDOG Service register WDSVR. Any attempt to

read this key data value of 01100 from WDSVR will read

as key data value of all 0’s.

•

The WATCHDOG detector circuit is inhibited during both

the HALT and IDLE modes.

The Clock Monitor detector circuit is active during both

the HALT and IDLE modes. Consequently, the device in-

advertently entering the HALT mode will be detected as a

Clock Monitor error (provided that the Clock Monitor en-

able option has been selected by the program).

•

With the single-pin R/C oscillator mask option selected

and the CLKDLY bit reset, the WATCHDOG service win-

dow will resume following HALT mode from where it left

off before entering the HALT mode.

TABLE 19. WATCHDOG Service Actions

Key

Window

Data

Match

Clock

Action

Data

Monitor

Match

Valid Service: Restart Service Window

Error: Generate WATCHDOG Output

Don’t Care

Mismatch

Don’t Care

Mismatch

Don’t Care

Mismatch

www.national.com

60

Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

Contents

00A2

TDLC, Transmit Data Length

Code and Identifier Low

00A3

00A4

00A5

00A6

TID, Transmit Identifier High

RXD1, Receive Data 1

RXD2, Receive Data 2

Address

Contents

0000 to 006F

On-Chip RAM bytes (112

bytes)

RIDL, Receive Data Length

Code

0070 to 007F

0080

Unused RAM Address Space

(Reads as All Ones)

00A7

00A8

00A9

00AA

00AB

RID, Receive Identify HIgh

CSCAL, CAN Prescaler

PORTMD, Port M Data

Register

0081

PORTMC, Port M

Configuration Register

CTIM, Bus Timing Register

CBUS, Bus Control Register

0082

PORTMP, Port M Input Pins

(Read Only)

TCNTL, Transmit/Receive

Control Register

0083

0084

Reserved for Port M

00AC

00AD

00AE

00AF

RTSTAT Receive/Transmit

Status Register

MMIWU Edge Select Register

(MWKEDG)

TEC, Transmit Error Count

Register

0085

0086

MMIWU Enable Register

(MWKEN)

REC, Receive Error Count

Register

MMIWU Pending Register

(MWKPND)

PLATST, CAN Bit Stream

Processor Test Register

0087

0088

Reserved for MMIWU

PORTND, Port N Data

Register

00B8

00B9

00BA

00BB

UART Transmit Buffer (TBUF)

UART Receive Buffer (RBUF)

UART Control Status (ENU)

0089

PORTNC, Port N

Configuration Register

UART Receive Control Status

(ENUR)

008A

PORTNP, Port N Input Pins

(Read Only)

00BC

UART Interrupt and Clock

(ENUI)

008B

PORTNX, Port N Alternate

Function Enable

00BD

00BE

UART Baud Register (BAUD)

008C to 008F

0090

Unused RAM Address Space

(Reads Undefined Data)

UART Prescaler Register

(PSR)

PORTED, Port E Data

Register

00BF

00C0

Reserved for UART

Timer T2 Lower Byte

(TMR2LO)

0091

PORTEC, Port E

Configuration Register

00C1

00C2

00C3

00C4

00C5

00C6

00C7

00C8

00C9

00CA

Timer T2 Upper Byte

(TMR2HI)

0092

PORTEP, Port E Input Pins

(Read Only)

Timer T2 Autoload Register

T2RA Lower Byte (T2RALO)

0093

0094

Reserved for Port E

PORTFD, Port F Data

Register

Timer T2 Autoload Register

T2RA Upper Byte (T2RAHI)

0095

0096

PORTFC, Port F

Configuration Register

Timer T2 Autoload Register

T2RB Lower Byte (T2RBLO)

PORTFP, Port F Input Pins

(Read Only)

Timer T2 Autoload Register

T2RB Upper Byte (T2RBHI)

0097

0098

Reserved for Port F

Timer T2 Control Register

(T2CNTRL)

SPICNTL, SPI Control

Register

WATCHDOG Service

Register (Reg:WDSVR)

0099

009A

SPISTAT, SPI Status Register

SPIRXD, SPI Current Receive

Data (Read Only)

LMIWU Edge Select Register

(LWKEDG)

009B

SPITXD, SPI Transmit Data

Reserved

LMIWU Enable Register

(LWKEN)

009C to 009F

00A0

TXD1, Transmit 1 Data

TXD2, Transmit 2 Data

LLMIWU Pending Register

(LWKPND)

00A1

61

www.national.com

Memory Map (Continued)

Address

Contents

00F0 to

00FB

On-Chip RAM Mapped as

Registers

Address

Contents

00CB

A/D Converter Control

Register (Reg:ENAD)

00FC

X Register

SP Register

B Register

S Register

00FD

00CC

A/D Converter Result Register

(Reg:ADRSLT)

00FE

00FF

00CD to

00CE

Reserved

0100 to 013F

On-Chip RAM Bytes (64

Bytes)

00CF

00D0

00D1

00D2

IDLE Timer Control Register

(Reg:ITMR)

Reading memory locations 0070H–007FH will

return all ones. Reading unused memory locations

00xxH–00xxH will return undefined data. Reading

memory locations from other Segments (i.e.

segment 2, segment 3, ...etc.) will return undefined

data.

PORTLD, Port L Data

Register

PORTLC, Port L

Configuration Register

PORTLP, Port L Input Pins

(Read Only)

Addressing Modes

There are ten addressing modes, six for operand addressing

and four for transfer of control.

00D3

00D4

Reserved for Port L

PORTGD, Port G Data

Register

OPERAND ADDRESSING MODES

00D5

00D6

PORTGC, Port G

Configuration Register

Register Indirect

PORTGP, Port G Input Pins

(Read Only)

This is the “normal” addressing mode. The operand is the

data memory addressed by the B pointer or X pointer.

00D7

00D8

00D9

Port I Input Pins (Read Only)

Port CD, Port C Data Register

Register Indirect (with auto post increment or

decrement of pointer)

Port CC, Port C Configuration

Register

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

pointer or X pointer. This is a register indirect mode that au-

tomatically post increments or decrements the B or X regis-

ter after executing the instruction.

00DA

Port CP, Port C Input Pins

(Read Only)

00DB

00DC

Reserved for Port C

Port D

Direct

00DD to

00DF

Reserved for Port D

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

00E0 to

00E5

Reserved for EE Control

Registers

Immediate

The instruction contains an 8-bit immediate field as the oper-

and.

00E6

Timer T1 Autoload Register

T1RB Lower Byte (T1BRLO)

00E7

Timer T1 Autoload Register

T1RB Upper Byte (T1BRHI)

Short Immediate

This addressing mode is used with the Load B Immediate in-

struction. The instruction contains a 4-bit immediate field as

the operand.

00E8

00E9

ICNTRL Register

MICROWIRE/PLUS Shift

Register (SOIR)

Indirect

00EA

00EB

00EC

00ED

Timer T1 Lower Byte

(TMR1LO)

This addressing mode is used with the LAID instruction. The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

Timer T1 Upper Byte

(TMR1HI)

Timer T1 Autoload Register

T1RA Lower Byte (T1RALO)

TRANSFER OF CONTROL ADDRESSING MODES

Timer T1 Autoload Register

T1RA Upper Byte (T1RAHI)

Relative

This mode is used for the JP instruction, with the instruction

field being added to the program counter to get the new pro-

gram location. JP has a range from −31 to +32 to allow a

1-byte relatie jump (JP + 1 is implemented by a NOP instruc-

tion). There are no “pages” when using JP, since all 15 bits of

PC are used.

00EE

00EF

CNTRL, Control Register

PSW, Processor Status Word

Register

www.national.com

62

Addressing Modes (Continued)

Instruction Set

Absolute

Register and Symbol Definition

The mode is used with the JMP and JSR instructions, with

the instruction field of 12 bits replacing the lower 12 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory segment.

Registers

A

8-Bit Accumulator Register

8-Bit Address Register

B

X

8-Bit Address Register

Absolute Long

SP

PC

PU

PL

C

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

This mode is used with the JMPL and JSRL instructions, with

the instruction field of 15 bits replacing the entire 15 bits of

the program counter (PC). This allows jumping to any loca-

tion up to 32k in the program memory space.

Lower 8 Bits of PC

Indirect

1 Bit of PSW Register for Carry

1 Bit of PSW Register for Half Carry

1 Bit of PSW Register for Global Interrupt Enable

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

This mode is used with the JID instruction. The contents of

the accumulator are used as a partial address (lower 8 bits of

PC) for accessing a location in the program memory. The

contents of this program memory location serve as a partial

address (lower 8 bits of PC) for the jump to the next instruc-

tion.

Note: The VIS is a special case of the Indirect Transfer of Control addressing

mode, where the double byte vector associated with the interrupt is

transferred from adjacent addresses in the program memory into the

program counter (PC) in order to jump to the associated interrupt ser-

vice routine.

HC

GIE

VU

VL

Symbols

[B]

Memory Indirectly Addressed by B Register

Memory Indirectly Addressed by X Register

Direct Addressed Memory

Direct Addressed Memory or [B]

Direct Addressed Memory or [B] or

Immediate Data

[X]

MD

Mem

Meml

Imm

Reg

8-Bit Immediate Data

Register Memory: Addresses F0 to FF

(Includes B, X and SP)

Bit

←

↔

Bit Number (0 to 7)

Loaded with

Exchanged with

63

www.national.com

Instruction Set (Continued)

INSTRUCTION SET

←

ADD

ADC

A,Meml

ADD

A

A + Meml

A + Meml + C, C Carry,

←

ADD with Carry

←

HC Half Carry,

← ←

A − MemI + C, C Carry,

SUBC

A,Meml

Subtract with Carry

A

←

HC Half Carry

←

AND

ANDSZ

OR

A,Meml

A,Imm

A,Meml

MD,Imm

A,Meml

#

Logical AND

A

A and Meml

Logical AND Immed., Skip if Zero

Logical OR

Skip next if (A and Imm) = 0

←

A

A or Meml

XOR

IFEQ

IFNE

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

RPND

X

Logical EXclusive OR

IF EQual

A xor Meml

Compare MD and Imm, Do next if MD = Imm

Compare A and Meml, Do next if A = Meml

IF EQual

≠

Compare A and Meml, Do next if A Meml

IF Not Equal

>

Compare A and Meml, Do next if A Meml

≠

Do next if lower 4 bits of B Imm

IF Greater Than

IF B Not Equal

←

Reg

Decrement Reg., Skip if Zero

Set BIT

Reg Reg − 1, Skip if Reg = 0

#,Mem

1 to bit, Mem (bit = 0 to 7 immediate)

0 to bit, Mem

Reset BIT

IF BIT

If bit in A or Mem is true do next instruction

Reset Software Interrupt Pending Flag

Reset PeNDing Flag

EXchange A with Memory

EXchange A with Memory [X]

LoaD A with Memory

LoaD A with Memory [X]

LoaD B with Immed.

LoaD Memory Immed.

LoaD Register Memory Immed.

EXchange A with Memory [B]

EXchange A with Memory [X]

LoaD A with Memory [B]

LoaD A with Memory [X]

LoaD Memory [B] Immed.

CLeaR A

↔

←

A,Mem

A,[X]

A

B

Mem

[X]

X

LD

A,Meml

A,[X]

Meml

[X]

LD

B,Imm

Mem,Imm

Reg,Imm

A, [B]

A, [X]

A, [B]

A,[X]

Imm

←

Mem Imm

LD

←

Reg Imm

LD

↔

←

[B], (B B 1)

X

A

←

[X], (X X 1)

X

←

[B], (B B 1)

LD

←

[X], (X X 1)

LD

← ←

[B] Imm, (B B 1)

LD

[B],Imm

A

←

→

CLR

INC

A

C

0

A

INCrement A

A + 1

DEC

LAID

DCOR

RRC

RLC

SWAP

SC

A

DECrement A

A − 1

Load A InDirect from ROM

Decimal CORrect A

Rotate A Right thru C

Rotate A Left thru C

SWAP nibbles of A

Set C

ROM (PU,A)

A

BCD correction of A (follows ADC, SUBC)

→

←

→

←

→

←

A7

…

A0

C

←

↔

A7…A4 A3…A0

←

C

1, HC

0, HC

1

0

RC

Reset C

IFC

IF C

IF C is true, do next instruction

IFNC

POP

PUSH

VIS

IF Not C

If C is not true, do next instruction

← ←

SP SP + 1, A [SP]

A

POP the stack into A

PUSH A onto the stack

Vector to Interrupt Service Routine

Jump absolute Long

Jump absolute

←

[SP] A, SP SP − 1

←

PU [VU], PL [VL]

←

PC ii (ii = 15 bits, 0 to 32k)

JMPL

JMP

JP

Addr.

Disp.

←

PC9…0 i (i = 12 bits)

←

PC PC + r (r is −31 to +32, except 1)

Jump relative short

www.national.com

64

Instruction Set (Continued)

INSTRUCTION SET (Continued)

← ← ←

[SP] PL, [SP−1] PU,SP−2, PC ii

JSRL

JSR

Addr.

Jump SubRoutine Long

Jump SubRoutine

Jump InDirect

←

[SP] PL, [SP−1] PU,SP−2, PC9…0

i

←

PL ROM (PU,A)

JID

← ←

SP + 2, PL [SP], PU [SP−1]

RET

RETurn from subroutine

RETurn and SKip

RETurn from Interrupt

Generate an Interrupt

No OPeration

← ←

SP + 2, PL [SP],PU [SP−1]

RETSK

RETI

INTR

NOP

←

SP + 2, PL [SP],PU [SP−1],GIE

1

←

[SP] PL, [SP−1] PU, SP−2, PC 0FF

←

PC PC + 1

65

www.national.com

Instructions Using A and C

Instruction Set (Continued)

CLRA

INCA

DECA

LAID

1/1

1/3

1/1

1/3

2/2

INSTRUCTION EXECUTION TIME

Most instructions are single byte (with immediate addressing

mode instructions taking two bytes).

Most single byte instructions take one cycle time to execute.

Skipped instructions require x number of cycles to be

skipped, where x equals the number of bytes in the skipped

instruction opcode.

DCORA

RRCA

RLCA

SWAPA

SC

See the BYTES and CYCLES per INSTRUCTION table for

details.

Bytes and Cycles per Instruction

RC

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

IFC

Arithmetic and Logic Instructions

IFNC

PUSHA

POPA

ANDSZ

[B]

1/1

Direct

3/4

Immed.

2/2

ADD

ADC

SUBC

AND

OR

3/4

2/2

Transfer of Control Instructions

3/4

2/2

3/4

2/2

JMPL

JMP

JP

3/4

2/3

1/3

3/5

2/5

1/3

1/5

1/7

1/1

3/4

2/2

XOR

IFEQ

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

3/4

2/2

3/4

2/2

JSRL

JSR

3/4

2/2

JID

1/3

3/4

VIS

1/1

RET

RETSK

RETI

INTR

NOP

RPND

Memory Transfer Instructions

Register

Indirect

Register Indirect

Direct Immed. Auto Incr. and Decr.

[B]

[X]

[B+, B−]

[X+, X−]

X A, (Note *NO

TARGET FOR

FNXref

1/1

1/3

2/3

1/2

1/3

NS13180*)

LD A, (Note 24)

LD B, Imm

1/1

2/2

1/3

2/3

2/2

1/1

2/3

1/2

2/2

1/3

<

(IF B 16)

>

(IF B 15)

LD B, Imm

LD Mem, Imm

LD Reg, Imm

IFEQ MD, Imm

3/3

2/3

3/3

>

Memory location addressed by B or X or directly.

Note 24:

=

www.national.com

66

N i b b l e L o w e r

67

www.national.com

cludes BCLIDE (Byte Craft Limited Integrated Develop-

ment Environment) for Win32, editor, optimizing C Cross-

Compiler, macro cross assembler, BC-Linker, and

MetaLink tools support. (DOS/SUN versions available;

Compiler is installable under WCOP8 IDE; Compatible

with DriveWay COP8).

Development Tools Support

OVERVIEW

National is engaged with an international community of inde-

pendent 3rd party vendors who provide hardware and soft-

ware development tool support. Through National’s interac-

tion and guidance, these tools cooperate to form a choice of

solutions that fits each developer’s needs.

•

EWCOP8-KS: Very Low cost ANSI C-Compiler and Em-

bedded Workbench from IAR (Kickstart version:

COP8Sx/Fx only with 2k code limit; No FP). A fully inte-

grated Win32 IDE, ANSI C-Compiler, macro assembler,

editor, linker, Liberian, C-Spy simulator/debugger, PLUS

MetaLink EPU/DM emulator support.

This section provides a summary of the tool and develop-

ment kits currently available. Up-to-date information, selec-

tion guides, free tools, demos, updates, and purchase infor-

mation can be obtained at our web site at:

www.national.com/cop8.

EWCOP8-AS: Moderately priced COP8 Assembler and

Embedded Workbench from IAR (no code limit). A fully in-

tegrated Win32 IDE, macro assembler, editor, linker, li-

brarian, and C-Spy high-level simulator/debugger with

I/O and interrupts support. (Upgradeable with optional

C-Compiler and/or MetaLink Debugger/Emulator sup-

port).

SUMMARY OF TOOLS

COP8 Evaluation Tools

•

COP8–NSEVAL: Free Software Evaluation package for

Windows. A fully integrated evaluation environment for

COP8, including versions of WCOP8 IDE (Integrated De-

velopment Environment), COP8-NSASM, COP8-MLSIM,

•

EWCOP8-BL: Moderately priced ANSI C-Compiler and

Embedded Workbench from IAR (Baseline version: All

COP8 devices; 4k code limit; no FP). A fully integrated

Win32 IDE, ANSI C-Compiler, macro assembler, editor,

linker, librarian, and C-Spy high-level simulator/debugger.

(Upgradeable; CWCOP8-M MetaLink tools interface sup-

port optional).

™

COP8C, DriveWay COP8, Manuals, and other COP8

information.

•

COP8–MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

COP8–EPU: Very Low cost COP8 Evaluation & Pro-

gramming Unit. Windows based evaluation and

hardware-simulation tool, with COP8 device programmer

and erasable samples. Includes COP8-NSDEV, Drive-

way COP8 Demo, MetaLink Debugger, I/O cables and

power supply.

•

EWCOP8: Full featured ANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, and C-Spy high-level

simulator/debugger. (CWCOP8-M MetaLink tools inter-

face support optional).

•

COP8–EVAL-ICUxx: Very Low cost evaluation and de-

sign test board for COP8ACC and COP8SGx Families,

from ICU. Real-time environment with add-on A/D, D/A,

and EEPROM. Includes software routines and reference

designs.

EWCOP8-M: Full featured ANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, C-Spy high-level

simulator/debugger, PLUS MetaLink debugger/hardware

interface (CWCOP8-M).

Manuals, Applications Notes, Literature: Available free

from our web site at: www.national.com/cop8.

COP8 Productivity Enhancement Tools

COP8 Integrated Software/Hardware Design Develop-

ment Kits

•

WCOP8 IDE: Very Low cost IDE (Integrated Develop-

ment Environment) from KKD. Supports COP8C, COP8-

NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink

debugger under a common Windows Project Manage-

ment environment. Code development, debug, and emu-

lation tools can be launched from the project window

framework.

•

COP8-EPU: Very Low cost Evaluation & Programming

Unit. Windows based development and hardware-

simulation tool for COPSx/xG families, with COP8 device

programmer and samples. Includes COP8-NSDEV,

Driveway COP8 Demo, MetaLink Debugger, cables and

power supply.

•

DriveWay-COP8: Low cost COP8 Peripherals Code

Generation tool from Aisys Corporation. Automatically

generates tested and documented C or Assembly source

code modules containing I/O drivers and interrupt han-

dlers for each on-chip peripheral. Application specific

code can be inserted for customization using the inte-

grated editor. (Compatible with COP8-NSASM, COP8C,

and WCOP8 IDE.)

•

COP8-DM: Moderate cost Debug Module from MetaLink.

A Windows based, real-time in-circuit emulation tool with

COP8 device programmer. Includes COP8-NSDEV,

DriveWay COP8 Demo, MetaLink Debugger, power sup-

ply, emulation cables and adapters.

COP8 Development Languages and Environments

•

COP8-NSASM: Free COP8 Assembler v5 for Win32.

Macro assembler, linker, and librarian for COP8 software

development. Supports all COP8 devices. (DOS/Win16

v4.10.2 available with limited support). (Compatible with

WCOP8 IDE, COP8C, and DriveWay COP8).

•

COP8-UTILS: Free set of COP8 assembly code ex-

amples, device drivers, and utilities to speed up code de-

velopment.

COP8-MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

•

COP8-NSDEV: Very low cost Software Development

Package for Windows. An integrated development envi-

ronment for COP8, including WCOP8 IDE, COP8-

NSASM, COP8-MLSIM.

COP8C: Moderately priced C Cross-Compiler and Code

Development System from Byte Craft (no code limit). In-

www.national.com

68

COP8 Device Programmer Support

Development Tools Support

•

MetaLink’s EPU and Debug Module include development

device programming capability for COP8 devices.

(Continued)

COP8 Real-Time Emulation Tools

•

Third-party programmers and automatic handling equip-

ment cover needs from engineering prototype and pilot

production, to full production environments.

•

COP8-DM: MetaLink Debug Module. A moderately

priced real-time in-circuit emulation tool, with COP8 de-

vice programmer. Includes COP8-NSDEV, DriveWay

COP8 Demo, MetaLink Debugger, power supply, emula-

tion cables and adapters.

•

Factory programming available for high-volume require-

ments.

•

IM-COP8: MetaLink iceMASTER^®. A full featured, real-

time in-circuit emulator for COP8 devices. Includes Met-

aLink Windows Debugger, and power supply. Package-

specific probes and surface mount adaptors are ordered

separately.

TOOLS ORDERING NUMBERS FOR THE COP87L88EB/RB FAMILY DEVICES

Vendor

Tools

Order Number

COP8-NSEVAL

Cost

Notes

National COP8-NSEVAL

COP8-NSASM

COP8-MLSIM

COP8-NSDEV

COP8-EPU

Free Web site download

COP8-NSASM

Free Included in EPU and DM. Web site download

COP8-MLSIM

COP8-NSDEV

VL

Included in EPU and DM. Order CD from website

Not available for this device

Contact MetaLink

COP87L88EB/RB

COP8-DM

Development

Devices

VL

L

16k or 32k OTP devices

OTP

EDI -44+68PL/40D-

ZAL-W-COP888EB

For programming 44/68 PLCC on any programmer.

Contact EDI

Programming

Adapters

IM-COP8

MetaLink COP8-EPU

COP8-DM

Contact MetaLink

Not available for this device

DM4-COP8-888EB (10

MHz), plus PS-10, plus

DM-COP8/xxx (ie. 44P)

M

L

Included p/s (PS-10), target cable of choice (PLCC;

i.e. DM-COP8/40P), EDI 44/68 PLCC OTP adapter

OTP

Programming

Adapters

EDI -44/68PL/40D-

ZAL-W-COP888EB

For programming 44/68 PLCC

IM-COP8

IM-COP8-AD-464 (-220)

(10 MHz maximum)

H

Base unit 10 MHz; -220 = 220V; add probe card

(required) and target adapter (if needed); included

software and manuals

IM Probe Card

PC-888EB44P5-AD-10

PC-888EB68P5-AD-10

Not available for this device

WCOP8-IDE

M

10 MHz 44 PLCC probe card; 2.5V to 6.0V

10 MHz 68 PLCC probe card; 2.5V to 6.0V

ICU

KKD

IAR

COP8-EVAL

WCOP8-IDE

EWCOP8-xx

COP8C

VL

Included in EPU and DM

See summary above

COP8C

L - H Included all software and manuals

Byte

Craft

M

Included all software and manuals

Aisys

DriveWay COP8

Contact vendors

L

Included all software and manuals

OTP Programmers

L - H For approved programmer listings and vendor

information, go to our OTP support page at:

www.national.com/cop8

<

Cost: Free; VL = $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k

69

www.national.com

Development Tools Support (Continued)

WHERE TO GET TOOLS

Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.

Vendor

Home Office

U.S.A.: Santa Clara, CA

1-408-327-8820

Electronic Sites

Other Main Offices

Distributors

Aisys

www.aisysinc.com

@

info aisysinc.com

fax: 1-408-327-8830

U.S.A.

Byte Craft

IAR

www.bytecraft.com

Distributors

@

1-519-888-6911

info bytecraft.com

fax: 1-519-746-6751

Sweden: Uppsala

+46 18 16 78 00

fax: +46 18 16 78 38

www.iar.se

U.S.A.: San Francisco

1-415-765-5500

@

info iar.se

@

info iar.com

fax: 1-415-765-5503

U.K.: London

@

info iarsys.co.uk

@

info iar.de

+44 171 924 33 34

fax: +44 171 924 53 41

Germany: Munich

+49 89 470 6022

fax: +49 89 470 956

Switzeland: Hoehe

+41 34 497 28 20

fax: +41 34 497 28 21

ICU

Sweden: Polygonvaegen

+46 8 630 11 20

www.icu.se

@

support icu.se

@

fax: +46 8 630 11 70

Denmark:

support icu.ch

KKD

www.kkd.dk

MetaLink

U.S.A.: Chandler, AZ

1-800-638-2423

www.metaice.com

Germany: Kirchseeon

80-91-5696-0

@

sales metaice.com

@

fax: 1-602-926-1198

support metaice.com

fax: 80-91-2386

@

bbs: 1-602-962-0013

www.metalink.de

islanger metalink.de

Distributors Worldwide

National

U.S.A.: Santa Clara, CA

1-800-272-9959

www.national.com/cop8

Europe: +49 (0) 180 530 8585

fax: +49 (0) 180 530 8586

Distributors Worldwide

@

support nsc.com

@

fax: 1-800-737-7018

europe.support nsc.com

The following companies have approved COP8 program-

mers in a variety of configurations. Contact your local office

or distributor. You can link to their web sites and get the lat-

est listing of approved programmers from National’s COP8

OTP Support page at: www.national.com/cop8.

Customer Support

Complete product information and technical support is avail-

able from National’s customer response centers, and from

our on-line COP8 customer support sites.

Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys-

tems; ICE Technology; Lloyd Research; Logical Devices;

MQP; Needhams; Phyton; SMS; Stag Programmers; Sys-

tem General; Tribal Microsystems; Xeltek.

www.national.com

70

Physical Dimensions inches (millimeters) unless otherwise noted

44-Lead Molded Plastic Leaded Chip Carrier

Order Number COP87L88EBV-XE or COP87L88RBV-XE

NS Plastic Chip Package Number V44A

68-Lead Molded Plastic Leaded Chip Carrier

Order Number COP87L89EBV-XE or COP87L89RBV-XE

NS Plastic Chip Package Number V68A

71

www.national.com

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Email: nsj.crc@jksmtp.nsc.com

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 87 90

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	COP87L88
厂家：	National Semiconductor
描述：	8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART 8位CMOS微控制器OTP用16K或32K的内存， CAN接口， 8位A / D和USART 微控制器
文件：	总72页 (文件大小：815K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

COP87L88 [NSC]

相关型号：

COP87L88CF

COP87L88CFN-XE

COP87L88CFV-XE

COP87L88CFV-XE/NOPB

COP87L88CL

COP87L88CLN-XE

COP87L88CLV-XE

COP87L88CLV-XE

COP87L88CLV-XE/NOPB

COP87L88EB

COP87L88EB-XE

COP87L88EBV-XE