COP87L88CFN-XE_技术文档

September 1999

COP87L88CF

8-Bit CMOS OTP Microcontrollers with 16k Memory and

A/D Converter

Family features include an 8-bit memory mapped architec-

ture, 10 MHz CKI (-XE = crystal oscallator) with 1 µs instruc-

tion cycle, two multi-function 16-bit timer/counters,

General Description

The COP87L88CF OTP (One Time Programmable) micro-

™

controllers are highly integrated COP8 Feature core de-

™

MICROWIRE/PLUS serial I/O, one 8-bit/8-channel A/D

vices with 16k memory and advanced features including an

A/D converter. These multi-chip CMOS devices are suited

for applications requiring a full featured controller with an

8-bit A/D converter, and as pre-production devices for a

masked ROM design. Lower cost pin and software compat-

ible 16k ROM versions are available (COP888CF) as well as

a range of COP8 software and hardware development tools.

converter with prescaler and both differential and single

ended modes, two power saving HALT/IDLE modes, idle

timer, MIWU, high current outputs, software selectable I/O

™

options, WATCHDOG timer and Clock Monitor, 2.7V to

5.5V operation and 28/40/44 pin packages.

Devices included in this datasheet are:

Device

Memory (bytes)

16k OTP EPROM

RAM (bytes)

128

I/O Pins

24

Packages

28 DIP/SOIC

Temperature

-40 to +85˚C

COP87L84CF

COP87L88CF

128

36/40

40 DIP, 44 PLCC

n Schmitt trigger inputs on Port G

Key Features

n A/D converter (8-bit, 8-channel, with prescaler and both

differential and single ended modes)

n Two 16-bit timers, each with two 16-bit registers

supporting:

CPU/Instruction Set Feature

n 1 µs instruction cycle time

n Ten multi-source vectored interrupts servicing

— External interrupt with selectable edge

— Idle Timer T0

— Processor Independent PWM mode

— External Event counter mode

— Two Timers (Each with 2 interrupts)

— MICROWIRE/PLUS

— Multi-Input Wake Up

— Input Capture mode

n 16 kbytes on-board OTP EPROM with security feature

n 128 bytes on-board RAM

— Software Trap

— Default VIS (default interrupt)

n Versatile and easy to use instruction set

n 8-bit Stack Pointer (SP)—stack in RAM

n Two 8-bit Register Indirect Data Memory Pointers (B, X)

Additional Peripheral Features

n Idle Timer

n Multi-Input Wake Up (MIWU) with optional interrupts (8)

n WATCHDOG and Clock Monitor logic

n MICROWIRE/PLUS serial I/O

Fully Static CMOS

n Two power saving modes: HALT and IDLE

n Single supply operation: 2.7V to 5.5V

n Temperature ranges: -40˚C to +85˚C

I/O Features

™

n Software selectable I/O options (TRI-STATE Output,

Push-Pull Output, Weak Pull-Up Input, High Impedance

Input)

n High current outputs

Development Support

n Emulation device for the COP888CF/COP884CF

n Real time emulation and full program debug offered by

MetaLink Development System

n Packages:

— 44 PLCC with 38 I/O pins

— 40 DIP with 34 I/O pins

— 28 DIP/SO with 22 I/O pins

™

COP8 is a trademark of National Semiconductor Corporation.

™

MICROWIRE is a trademark of National Semiconductor Corporation.

™

MICROWIRE/PLUS is a trademark of National Semiconductor Corporation.

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

™

WATCHDOG is a trademark of National Semiconductor Corporation.

™

iceMASTER is a trademark of MetaLink Corporation.

DS101134

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Block Diagram

DS101134-1

FIGURE 1. Block Diagram

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2

Connection Diagrams

Plastic Chip Carrier

Dual-In-Line Package

DS101134-37

DS101134-2

Top View

Order Number COP87L88CFV-XE

See NS Plastic Chip Package Number V44A

Order Number COP87L84CFN-XE or

COP87L84CFM-XE

See NS Package Number N28B or M28B

Dual-In-Line Package

DS101134-4

Top View

Order Number COP87L84CFN-XE,

See NS Molded Package Number N40A

Note: -X = Crystal Oscillator

-E = Halt Mode Enable

FIGURE 2. Connection Diagrams

3

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Connection Diagrams (Continued)

Pinouts for 28-, 40-, and 44-Pin Packages

Port

Type

I/O

Alt. Fun

MIWU

Alt. Fun

28-Pin Pack.

40-Pin Pack.

44-Pin Pack.

L0

L1

L2

L3

L4

L5

L6

L7

11

12

13

14

15

16

17

18

25

26

27

28

1

17

18

19

20

21

22

23

24

35

36

37

38

3

—

19

20

25

26

27

28

39

40

41

42

3

I/O

MIWU

INT

I/O

T2A

T2B

I/O

G0

G1

G2

G3

G4

G5

G6

G7

I0

I/O

WDOUT

I/O

T1B

I/O

T1A

I/O

SO

I/O

SK

2

4

I

SI

3

5

I/CKO

HALT Restart

ACH0

ACH1

ACH2

ACH3

ACH4

ACH5

ACH6

ACH7

4

6

I

7

9

I1

I

8

10

11

12

13

14

10

11

12

13

14

15

16

29

30

31

32

33

34

35

36

43

44

1

I2

I

I3

I

I4

I

I5

I

I6

I

I7

I

D0

D1

D2

D3

D4

D5

D6

D7

C0

C1

C2

C3

C4

C5

C6

C7

V_REF

AGND

V_CC

GND

CKI

RESET

O

19

20

21

22

25

26

27

28

29

30

31

32

39

40

1

O

I/O

+V_REF

AGND

2

21

22

23

24

18

17

8

10

9

16

15

8

6

23

5

33

7

37

7

24

34

38

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4

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Total Current into V_CCPin (Source)

Total Current out of GND Pin (Sink)

Storage Temperature Range

Note 1: Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

100 mA

110 mA

−65˚C to +140˚C

Supply Voltage (V_CC

Voltage at Any Pin

)

7V

−0.3V to V_CC+ 0.3V

DC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

5.5

Units

Operating Voltage

2.7

V

Power Supply Ripple (Note 2)

Supply Current (Note 3)

CKI = 10 MHz

Peak-to-Peak

0.1 V_CC

V_CC= 5.5V, t_c= 1

µs

16.5

6.5

12

mA

µA

CKI = 4 MHz

V_CC= 4V, t_c= 2.5

µs

HALT Current (Note 4)

V_CC= 5.5V, CKI = 0

MHz

IDLE Current

CKI = 10 MHz

V_CC= 5.5V, t_c= 1

µs

3.5

0.7

mA

CKI = 1 MHz

Input Levels

V_CC= 4V, t_c= 10 µs

RESET

Logic High

0.8 V_CC

0.7 V_CC

V

Logic Low

0.2 V_CC

CKI (External and Crystal Osc. Modes)

Logic High

V

Logic Low

All Other Inputs

Logic High

V

Logic Low

0.2 V_CC

+2

Hi-Z Input Leakage

Input Pullup Current

G and L Port Input Hysteresis

Output Current Levels

D Outputs

V_CC= 5.5V

−2

40

µA

V

250

0.05 V_CC

0.35 V_CC

Source

V_CC= 4.5V, V_OH

3.3V

=

0.4

10

mA

Sink

V_CC= 4.5V, V_OL

1V

All Others

Source (Weak Pull-Up Mode)

V_CC= 4.5V, V_OH

2.7V

=

10

0.4

1.6

−2

100

µA

mA

µA

Source (Push-Pull Mode)

Sink (Push-Pull Mode)

V_CC= 4.5V, V_OH

3.3V

V_CC= 4.5V, V_OL

0.4V

TRI-STATE Leakage

Allowable Sink/Source

Current per Pin

V_CC= 5.5V

+2

15

D Outputs (Sink)

mA

5

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DC Electrical Characteristics (Continued)

−40˚C ≤ T_A≤ +85˚C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

Units

mA

All others

3

±

Maximum Input Current

without Latchup (Note 9)

T_A= 25˚C

100

mA

RAM Retention Voltage, V_r

500 ns Rise

2

V

and Fall Time (Min)

Input Capacitance

7

pF

Load Capacitance on D2

1000

Note 2: Rate of voltage change must be less then 0.5 V/ms.

Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.

Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V , L and G0–G5 configured as

CC

outputs and set high. The D port set to zero. The A/D is disabled. V

is tied to AGND (effectively shorting the Reference resistor). The clock monitor is disabled.

REF

Note 5: The user must guarantee that D2 pin does not source more than 10 ma during RESET. If D2 sources more than 10 mA during reset, the device will go into

programming mode.

AC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C unless otherwise specified

Parameter

Instruction Cycle Time (t_c)

Conditions

Min

Typ

Max

Units

Crystal, Resonator

R/C Oscillator

1

3

DC

µs

Inputs

t_SETUP

4V ≤ V_CC≤ 6V

200

60

ns

t_HOLD

4V ≤ V_CC≤ 6V

Output Propagation Delay (Note 6)

R_L= 2.2k, C_L= 100 pF

t_PD1, t_PD0

SO, SK

4V ≤ V_CC≤ 6V

0.7

1

µs

ns

All Others

™

MICROWIRE Setup Time (t_UWS

)

20

56

MICROWIRE Hold Time (t_UWH

)

MICROWIRE Output Propagation Delay (t_UPD

Input Pulse Width

)

220

Interrupt Input High Time

Interrupt Input Low Time

Timer Input High Time

1

t_c

Timer Input Low Time

t_c

Reset Pulse Width

µs

Note 6: The output propagation delay is referenced to end of the instruction cycle where the output change occurs.

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6

A/D Converter Specifications

±

V_CC= 5V 10% (V_SS− 0.050V) ≤ Any Input ≤ (V_CC+ 0.050V)

Parameter Conditions

Min

Typ

Max

8

Units

Bits

V

Resolution

Reference Voltage Input

Absolute Accuracy

Non-Linearity

AGND = 0V

3

V_CC

±

V_REF= V_CC

2

LSB

V_REF= V_CC

1

±

Deviation from the

Best Straight Line

V_REF= V_CC

⁄

2

LSB

1

±

Differential Non-Linearity

⁄

LSB

kΩ

Input Reference Resistance

Common Mode Input Range (Note 10)

DC Common Mode Error

1.6

4.8

AGND

V_REF

V

1

±

⁄4

LSB

Off Channel Leakage Current

On Channel Leakage Current

A/D Clock Frequency (Note 8)

Conversion Time (Note 7)

1

µA

0.1

1.67

MHz

A/D Clock

Cycles

12

Note 7: Conversion Time includes sample and hold time.

Note 8: See Prescaler description.

Note 9: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V

and the pins will

CC

have sink current to V when biased at voltages greater than V (the pins do not have source current when biased at a voltage below V ). The effective resis-

CC

tance to V

is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.

CC

Note 10: For V (−)≥V (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog

IN

input voltages below ground or above the V supply. Be careful, during testing at low V levels (4.5V), as high level analog inputs (5V) can cause this input diode

CC

to conduct — especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means

that as long as the analog V does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V to 5 V input

IN

DC

voltage range will therefore require a minimum supply voltage of 4.950 V over temperature variations, initial tolerance and loading. The voltage on any analog input

DC

should be −0.3V to V

+0.3V.

CC

DS101134-26

FIGURE 3. MICROWIRE/PLUS Timing

7

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Typical Performance Characteristics (−40˚C to +85˚C)

Halt—I_DDvs V_CC

Idle—I_DD

(Crystal Clock Option)

DS101134-29

DS101134-30

Dynamic—I_DD

(Crystal Clock Option)

Port L/C/G Weak Pull-Up

Source Current

DS101134-31

DS101134-32

Port L/C/G Push-Pull

Source Current

Port L/C/G Push-Pull Sink Current

DS101134-34

DS101134-33

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Typical Performance Characteristics (−40˚C to +85˚C) (Continued)

Port D Source Current

Port D Sink Current

DS101134-35

DS101134-36

Pin Descriptions

V_CCand GND are the power supply pins.

V_REFand AGND are the reference voltage pins for the

on-board A/D converter.

CKI is the clock input. This can come from an R/C generated

oscillator, or a crystal oscillator (in conjunction with CKO).

See Oscillator Description section.

RESET is the master reset input. See Reset Description sec-

tion.

The device contains three bidirectional 8-bit I/O ports (C, G

and L), where each individual bit may be independently con-

figured as an input (Schmitt trigger inputs on ports G and L),

output or TRI-STATE under program control. Three data

memory address locations are allocated for each of these

I/O ports. Each I/O port has two associated 8-bit memory

mapped registers, the CONFIGURATION register and the

output DATA register. A memory mapped address is also re-

served for the input pins of each I/O port. (See the memory

map for the various addresses associated with the I/O ports.)

Figure 4 shows the I/O port configurations. The DATA and

CONFIGURATION registers allow for each port bit to be in-

dividually configured under software control as shown below:

DS101134-6

FIGURE 4. I/O Port Configurations

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers

on the inputs.

Port L supports Multi-Input Wakeup (MIWU) on all eight pins.

L4 and L5 are used for the timer input functions T2A and

T2B. L0 and L1 are not available on the 44-pin version of the

device, since they are replaced by V_REFand AGND. L0 and

L1 are not terminated on the 44-pin version. Consequently,

reading L0 or L1 as inputs will return unreliable data with the

44-pin package, so this data should be masked out with user

software when the L port is read for input data. It is recom-

mended that the pins be configured as outputs.

CONFIGURA-

TION

DATA

Port Set-Up

Register

0

Register

0

Hi-Z Input

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

0

1

0

1

Port L has the following alternate features:

L7

L6

L5

L4

L3

L2

L1

L0

MIWU

MIWU or T2B

MIWU or T2A

MIWU

9

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Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

Pin Descriptions (Continued)

ternal loads on this pin must ensure that the output voltages stay

above 0.8 V

to prevent the chip from entering special modes. Also

CC

Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input

pin (G6), and two dedicated output pins (G1 and G7). Pins

G0 and G2–G6 all have Schmitt Triggers on their inputs. Pin

G1 serves as the dedicated WDOUT WATCHDOG output,

while pin G7 is either input or output depending on the oscil-

lator mask option selected. With the crystal oscillator option

selected, G7 serves as the dedicated output pin for the CKO

clock output. With the single-pin R/C oscillator mask option

selected, G7 serves as a general purpose input pin, but is

also used to bring the device out of HALT mode with a low to

high transition on G7. There are two registers associated

with the G Port, a data register and a configuration register.

Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-

vidually configured under software control.

keep the external loading on D2 to less than 1000 pF.

Functional Description

The architecture of the device is modified Harvard architec-

ture. With the Harvard architecture, the control store pro-

gram memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The ar-

chitecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t_c) cycle time.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin or general purpose input (R/C clock configu-

ration), the associated bits in the data and configuration reg-

isters for G6 and G7 are used for special purpose functions

as outlined below. Reading the G6 and G7 data bits will re-

turn zeros.

There are five CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

Note that the chip will be placed in the HALT mode by writing

a “1” to bit 7 of the Port G Data Register. Similarly the chip

will be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

phase of the SK clock. The G7 configuration bit, if set high,

enables the clock start up delay after HALT when the R/C

clock configuration is used.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). The SP is initialized to RAM ad-

dress 06F with reset.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

Config Reg.

CLKDLY

Data Reg.

HALT

G7

G6

PROGRAM MEMORY

Alternate SK

IDLE

Program memory consists of 4096 bytes of OTP EPROM.

These bytes may hold program instructions or constant data

(data tables for the LAID instruction, jump vectors for the JID

instruction, and interrupt vectors for the VIS instruction). The

program memory is addressed by the 15-bit program

counter (PC). All interrupts vector to program memory loca-

tion 0FF Hex.

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G0 INTR (External Interrupt Input)

The device can be configured to inhibit external reads of the

program memory. This is done by programming the Security

Byte.

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose

input

SECURITY FEATURE

The program memory array has an associate Security Byte

that is located outside of the program address range. This

byte can be addressed only from programming mode by a

programmer tool.

G1 WDOUT WATCHDOG and/or Clock Monitor dedicated

output.

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation for these unterminated pins

will return unpredictable values.

Security is an optional feature and can only be asserted after

the memory array has been programmed and verified. A se-

cured part will read all 00(hex) by a programmer. The part

will fail Blank Check and will fail Verify operations. A Read

operation will fill the programmer’s memory with 00(hex).

The Security Byte itself is always readable with value of

00(hex) if unsecure and FF(hex) if secure.

Port I is an 8-bit Hi-Z input port, and also provides the analog

inputs to the A/D converter. The 28-pin device does not have

a full complement of Port I pins. The unavailable pins are not

terminated (i.e. they are floating). A read operation from

these unterminated pins will return unpredictable values.

The user should ensure that the software takes this into ac-

count by either masking out these inputs, or else restricting

the accesses to bit operations only. If unterminated, Port I

pins will draw power only when addressed.

DATA MEMORY

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

register, and the various registers, and counters associated

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs (ex-

cept D2) together in order to get a higher drive.

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10

quency at the termination of reset. A Clock Monitor error will

cause an active low error output on pin G1. This error output

will continue until 16–32 t_cclock cycles following the clock

frequency reaching the minimum specified value, at which

time the G1 output will enter the TRI-STATE mode.

Functional Description (Continued)

with the timers (with the exception of the IDLE timer). Data

memory is addressed directly by the instruction or indirectly

by the B, X and SP pointers.

The device has 128 bytes of RAM. Sixteen bytes of RAM are

mapped as “registers” at addresses 0F0 to 0FF Hex. These

registers can be loaded immediately, and also decremented

and tested with the DRSZ (decrement register and skip if

zero) instruction. The memory pointer registers X, SP, and B

are memory mapped into this space at address locations

0FC to 0FE Hex respectively, with the other registers (other

than reserved register 0FF) being available for general us-

age.

The external RC network shown in Figure 5 should be used

to ensure that the RESET pin is held low until the power sup-

ply to the chip stabilizes.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumula-

tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

DS101134-7

>

RC 5 x Power Supply Rise Time

FIGURE 5. Recommended Reset Circuit

Reset

Oscillator Circuits

The RESET input when pulled low initializes the microcon-

troller. Initialization will occur whenever the RESET input is

pulled low. Upon initialization, the data and configuration

registers for Ports L, G, and C are cleared, resulting in these

Ports being initialized to the TRI-STATE mode. Pin G1 of the

G Port is an exception (as noted below) since pin G1 is dedi-

cated as the WATCHDOG and/or Clock Monitor error output

pin. Port D is initialized high with RESET. The PC, PSW, CN-

TRL, ICNTRL, and T2CNTRL control registers are cleared.

The Multi-Input Wakeup registers WKEN, WKEDG, and

WKPNDare cleared. The A/D control register ENAD is

cleared, resulting in the ADC being powered down initially.

The Stack Pointer, SP, is initialized to 06F Hex.

The chip can be driven by a clock input on the CKI input pin

which can be between DC and 10 MHz. The CKO output

clock is on pin G7 (crystal configuration). The CKI input fre-

quency is divided down by 10 to produce the instruction

cycle clock (1/t_c).

Figure 6 shows the Crystal and R/C diagrams.

CRYSTAL OSCILLATOR

CKI and CKO can be connected to make a closed loop crys-

tal (or resonator) controlled oscillator.

Table 1 shows the component values required for various

standard crystal values.

The device comes out of reset with both the WATCHDOG

logic and the Clock Monitor detector armed, and with both

the WATCHDOG service window bits set and the Clock

Monitor bit set. The WATCHDOG and Clock Monitor detector

circuits are inhibited during reset. The WATCHDOG service

window bits are initialized to the maximum WATCHDOG ser-

vice window of 64k t_cclock cycles. The Clock Monitor bit is

initialized high, and will cause a Clock Monitor error following

reset if the clock has not reached the minimum specified fre-

R/C OSCILLATOR

By selecting CKI as a single pin oscillator input, a single pin

R/C oscillator circuit can be connected to it. CKO is available

as a general purpose input, and/or HALT restart pin.

Table 2 shows the variation in the oscillator frequencies as

functions of the component (R and C) values.

DS101134-9

DS101134-8

FIGURE 6. Crystal and R/C Oscillator Diagrams

11

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The Half-Carry flag is also affected by all the instructions that

affect the Carry flag. The SC (Set Carry) and R/C (Reset

Carry) instructions will respectively set or clear both the carry

flags. In addition to the SC and R/C instructions, ADC,

SUBC, RRC and RLC instructions affect the Carry and Half

Carry flags.

Oscillator Circuits (Continued)

TABLE 1. Crystal Oscillator Configuration, T_A= 25˚C

R1

R2

C1

C2

CKI

Freq

(MHz)

10

Conditions

(kΩ)

(MΩ)

(pF)

30

(pF)

30–36

ICNTRL Register (Address X'00E8)

0

1

V_CC= 5V

Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB

30

30–36

4

Bit 7

Bit 0

200

100–150

0.455

The ICNTRL register contains the following bits:

Reserved This bit is reserved and must be zero

TABLE 2. R/C Oscillator Configuration, T_A= 25˚C

LPEN

L Port Interrupt Enable (Multi-Input Wakeup/

R

C

CKI Freq

Instr.

Cycle

Interrupt)

Conditions

T0PND

T0EN

Timer T0 Interrupt pending

(kΩ)

3.3

(pF)

82

(MHz)

(µs)

Timer T0 Interrupt Enable (Bit 12 toggle)

MICROWIRE/PLUS interrupt pending

Enable MICROWIRE/PLUS interrupt

2.2 to 2.7

1.1 to 1.3

0.9 to 1.1

3.7 to 4.6

7.4 to 9.0

8.8 to 10.8

V_CC= 5V

µWPND

µWEN

5.6

100

T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-

ture edge

6.8

Note: 3k ≤ R ≤ 200k

50 pF ≤ C ≤ 200 pF

T1ENB

Timer T1 Interrupt Enable for T1B Input cap-

ture edge

Control Registers

T2CNTRL Register (Address X'00C6)

CNTRL Register (Address X'00EE)

T2C3

Bit 7

T2C2

T2C1

T2C0

T2PNDA

T2ENA

T2PNDB

T2ENB

Bit 0

T1C3

Bit 7

T1C2

T1C1

T1C0 MSEL

IEDG

SL1

SL0

Bit 0

The T2CNTRL control register contains the following bits:

T2C3

T2C2

T2C1

T2C0

Timer T2 mode control bit

The Timer1 (T1) and MICROWIRE/PLUS control register

contains the following bits:

T1C3

T1C2

T1C1

T1C0

Timer T1 mode control bit

Timer T1 Start/Stop control in timer

Timer T2 Start/Stop control in timer

modes 1 and 2, T2 Underflow Interrupt Pend-

ing Flag in timer mode 3

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload

RA in mode 1, T2 Underflow in mode 2, T2A

capture edge in mode 3)

modes 1 and 2, T1 Underflow Interrupt

Pending Flag in timer mode 3

MSEL

IEDG

Selects G5 and G4 as MICROWIRE/PLUS

signals SK and SO respectively

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

External interrupt edge polarity select

(0 = Rising edge, 1 = Falling edge)

T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

by (00 = 2, 01 = 4, 1x = 8)

T2ENB

Timer T2 Interrupt Enable for Timer Underflow

or T2B Input capture edge

PSW Register (Address X'00EF)

Timers

HC

C

T1PNDA T1ENA EXPND BUSY EXEN GIE

Bit 0

The device contains a very versatile set of timers (T0, T1,

T2). All timers and associated autoreload/capture registers

power up containing random data.

Bit 7

The PSW register contains the following select bits:

Figure 7 shows a block diagram for the timers.

HC

C

Half Carry Flag

Carry Flag

TIMER T0 (IDLE TIMER)

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload

RA in mode 1, T1 Underflow in Mode 2, T1A

capture edge in mode 3)

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE timer T0, which is a

16-bit timer. The Timer T0 runs continuously at the fixed rate

of the instruction cycle clock, t_c. The user cannot read or

write to the IDLE Timer T0, which is a count down timer.

T1ENA

Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

EXPND External interrupt pending

BUSY

EXEN

GIE

MICROWIRE/PLUS busy shifting flag

The Timer T0 supports the following functions:

Exit out of the Idle Mode (See Idle Mode description)

WATCHDOG logic (See WATCHDOG description)

Start up delay out of the HALT mode

Enable external interrupt

Global interrupt enable (enables interrupts)

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12

In this mode the timer Tx counts down at a fixed rate of t_c.

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, RxA and RxB. The very

first underflow of the timer causes the timer to reload from

the register RxA. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

register RxB.

Timers (Continued)

The IDLE Timer T0 can generate an interrupt when the thir-

teenth bit toggles. This toggle is latched into the T0PND

pending flag, and will occur every 4 ms at the maximum

clock frequency (t_c= 1 µs). A control flag T0EN allows the in-

terrupt from the thirteenth bit of Timer T0 to be enabled or

disabled. Setting T0EN will enable the interrupt, while reset-

ting it will disable the interrupt.

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the

timer for PWM mode operation.

Figure 8 shows a block diagram of the timer in PWM mode.

TIMER T1 AND TIMER T2

The underflows can be programmed to toggle the TxA output

pin. The underflows can also be programmed to generate in-

terrupts.

The device has a set of two powerful timer/counter blocks,

T1 and T2. The associated features and functioning of a

timer block are described by referring to the timer block Tx.

Since the two timer blocks, T1 and T2, are identical, all com-

ments are equally applicable to either timer block.

Underflows from the timer are alternately latched into two

pending flags, TxPNDA and TxPNDB. The user must reset

these pending flags under software control. Two control en-

able flags, TxENA and TxENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag TxENA will cause an interrupt when a timer un-

derflow causes the RxA register to be reloaded into the timer.

Setting the timer enable flag TxENB will cause an interrupt

when a timer underflow causes the RxB register to be re-

loaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

Each timer block consists of a 16-bit timer, Tx, and two sup-

porting 16-bit autoreload/capture registers, RxA and RxB.

Each timer block has two pins associated with it, TxA and

TxB. The pin TxA supports I/O required by the timer block,

while the pin TxB is an input to the timer block. The powerful

and flexible timer block allows the device to easily perform all

timer functions with minimal software overhead. The timer

block has three operating modes: Processor Independent

PWM mode, External Event Counter mode, and Input Cap-

ture mode.

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

DS101134-13

FIGURE 8. Timer in PWM Mode

Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin. The

Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to

be clocked either on a positive or negative edge from the

TxA pin. Underflows from the timer are latched into the TxP-

NDA pending flag. Setting the TxENA control flag will cause

an interrupt when the timer underflows.

DS101134-11

FIGURE 7. Timers

Mode 1. Processor Independent PWM Mode

In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB con-

trol flag is set. The occurrence of a positive edge on the TxB

input pin is latched into the TxPNDB flag.

As the name suggests, this mode allows the COP888CF to

generate a PWM signal with very minimal user intervention.

The user only has to define the parameters of the PWM sig-

nal (ON time and OFF time). Once begun, the timer block will

continuously generate the PWM signal completely indepen-

dent of the microcontroller. The user software services the

timer block only when the PWM parameters require updat-

ing.

Figure 9 shows a block diagram of the timer in External

Event Counter mode.

Note: The PWM output is not available in this mode since the TxA pin is being

used as the counter input clock.

13

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Timers (Continued)

DS101134-15

FIGURE 10. Timer in Input Capture Mode

DS101134-14

FIGURE 9. Timer in External Event Counter Mode

Mode 3. Input Capture Mode

TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

The device can precisely measure external frequencies or

time external events by placing the timer block, Tx, in the in-

put capture mode.

TxC3

TxC2

TxC1

TxC0

Timer mode control

In this mode, the timer Tx is constantly running at the fixed t_c

rate. The two registers, RxA and RxB, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

RxA acts in conjunction with the TxA pin and the register RxB

acts in conjunction with the TxB pin.

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in

Mode 3 (Input Capture)

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

TxC3, TxC2 and TxC1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger con-

dition for each input pin can be specified independently.

TxPNDA Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively latched into the

pending flags, TxPNDA and TxPNDB. The control flag Tx-

ENA allows the interrupt on TxA to be either enabled or dis-

abled. Setting the TxENA flag enables interrupts to be gener-

ated when the selected trigger condition occurs on the TxA

pin. Similarly, the flag TxENB controls the interrupts from the

TxB pin.

TxPNDB Timer Interrupt Pending Flag

TxENB

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the TxC0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the TxENA control flag. When a TxA interrupt

occurs in the Input Capture mode, the user must check both

the TxPNDA and TxC0 pending flags in order to determine

whether a TxA input capture or a timer underflow (or both)

caused the interrupt.

Figure 10 shows a block diagram of the timer in Input Cap-

ture mode.

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14

Timers (Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

Interrupt A

Source

Interrupt B

Source

Timer

Mode

TxC3

TxC2

TxC1

Description

Counts On

1

0

1

0

PWM: TxA Toggle

Autoreload RA

Autoreload RB

t_C

1

PWM: No TxA

Toggle

t_C

0

1

0

1

0

External Event

Counter

Timer

Underflow

Pos. TxB Edge

Pos. TxA

Edge

2

External Event

Counter

Timer

Underflow

Pos. TxA

Edge

Captures:

Pos. TxA Edge

or Timer

t_C

TxA Pos. Edge

TxB Pos. Edge

Captures:

Underflow

1

0

1

0

1

Pos. TxA

Neg. TxB

Edge

TxA Pos. Edge

TxB Neg. Edge

Captures:

Edge or Timer

Underflow

3

Neg. TxA

Neg. TxB

Edge

TxA Neg. Edge

TxB Neg. Edge

Captures:

Edge or Timer

Underflow

Neg. TxA

Neg. TxB

Edge

TxA Neg. Edge

TxB Neg. Edge

Edge or Timer

Underflow

Power Save Modes

The device offers the user two power save modes of opera-

tion: HALT and IDLE. In the HALT mode, all microcontroller

activities are stopped. In the IDLE mode, the on-board oscil-

lator circuitry and timer T0 are active but all other microcon-

troller activities are stopped. In either mode, all on-board

RAM, registers, I/O states, and timers (with the exception of

T0) are unaltered.

resonators have a delayed start up time to reach full ampli-

tude and frequency stability. The IDLE timer is used to gen-

erate a fixed delay to ensure that the oscillator has indeed

stabilized before allowing instruction execution. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry is enabled. The IDLE timer is loaded with a value of

256 and is clocked with the t_cinstruction cycle clock. The t_c

clock is derived by dividing the oscillator clock down by a fac-

tor of 10. The Schmitt trigger following the CKI inverter on

the chip ensures that the IDLE timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specifications. This Schmitt trigger is not part

of the oscillator closed loop. The startup timeout from the

IDLE timer enables the clock signals to be routed to the rest

of the chip.

HALT MODE

The device is placed in the HALT mode by writing a “1” to the

HALT flag (G7 data bit). All microcontroller activities, includ-

ing the clock, timers, and A/D converter, are stopped. The

WATCHDOG logic is disabled during the HALT mode. How-

ever, the clock monitor circuitry if enabled remains active

and will cause the WATCHDOG output pin (WDOUT) to go

low. If the HALT mode is used and the user does not want to

activate the WDOUT pin, the Clock Monitor should be dis-

abled after the device comes out of reset (resetting the Clock

Monitor control bit with the first write to the WDSVR register).

In the HALT mode, the power requirements of the device are

minimal and the applied voltage (V_CC) may be decreased to

V_r(V_r= 2.0V) without altering the state of the machine.

If an RC clock option is being used, the fixed delay is intro-

duced optionally. A control bit, CLKDLY, mapped as configu-

ration bit G7, controls whether the delay is to be introduced

or not. The delay is included if CLKDLY is set, and excluded

if CLKDLY is reset. The CLKDLY bit is cleared on reset.

The device has two mask options associated with the HALT

mode. The first mask option enables the HALT mode feature,

while the second mask option disables the HALT mode. With

the HALT mode enable mask option, the device will enter

and exit the HALT mode as described above. With the HALT

disable mask option, the device cannot be placed in the

HALT mode (writing a “1” to the HALT flag will have no ef-

fect).

The device supports three different ways of exiting the HALT

mode. The first method of exiting the HALT mode is with the

Multi-Input Wakeup feature on the L port. The second

method is with a low to high transition on the CKO (G7) pin.

This method precludes the use of the crystal clock configura-

tion (since CKO becomes a dedicated output), and so may

be used with an RC clock configuration. The third method of

exiting the HALT mode is by pulling the RESET pin low.

The WATCHDOG detector circuit is inhibited during the

HALT mode. However, the clock monitor circuit if enabled re-

mains active during HALT mode in order to ensure a clock

monitor error if the device inadvertently enters the HALT

mode as a result of a runaway program or power glitch.

Since a crystal or ceramic resonator may be selected as the

oscillator, the Wakeup signal is not allowed to start the chip

running immediately since crystal oscillators and ceramic

15

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negative edge on that particular L Port pin. Resetting the bit

selects the trigger condition to be a positive edge. Changing

an edge select entails several steps in order to avoid a

pseudo Wakeup condition as a result of the edge change.

First, the associated WKEN bit should be reset, followed by

the edge select change in WKEDG. Next, the associated

WKPND bit should be cleared, followed by the associated

WKEN bit being re-enabled.

Power Save Modes (Continued)

IDLE MODE

The device is placed in the IDLE mode by writing a “1” to the

IDLE flag (G6 data bit). In this mode, all activity, except the

associated on-board oscillator circuitry, the WATCHDOG

logic, the clock monitor and the IDLE Timer T0, is stopped.

As with the HALT mode, the device can be returned to nor-

mal operation with a reset, or with a Multi-Input Wakeup from

the L Port. Alternately, the microcontroller resumes normal

operation from the IDLE mode when the thirteenth bit (repre-

senting 4.096 ms at internal clock frequency of 1 MHz,

t_c= 1 µs) of the IDLE Timer toggles.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for L Port bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

RBIT 5, WKEN

SBIT 5, WKEDG ; Change edge polarity

RBIT 5, WKPND ; Reset pending flag

; Disable MIWU

This toggle condition of the thirteenth bit of the IDLE Timer

T0 is latched into the T0PND pending flag.

The user has the option of being interrupted with a transition

on the thirteenth bit of the IDLE Timer T0. The interrupt can

be enabled or disabled via the T0EN control bit. Setting the

T0EN flag enables the interrupt and vice versa.

SBIT 5, WKEN

; Enable MIWU

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid inherited pseudo

wakeup conditions. After the selected L port bits have been

changed from output to input but before the associated

WKEN bits are enabled, the associated edge select bits in

WKEDG should be set or reset for the desired edge selects,

followed by the associated WKPND bits being cleared.

The user can enter the IDLE mode with the Timer T0 inter-

rupt enabled. In this case, when the T0PND bit gets set, the

device will first execute the Timer T0 interrupt service routine

and then return to the instruction following the “Enter Idle

Mode” instruction.

Alternatively, the user can enter the IDLE mode with the

IDLE Timer T0 interrupt disabled. In this case, the device will

resume normal operation with the instruction immediately

following the “Enter IDLE Mode” instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions

are necessary to allow clock resynchronization following the HALT or

IDLE modes.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The occurrence of the selected trigger condition for

Multi-Input Wakeup is latched into a pending register called

WKPND. The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the cor-

responding Port L pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

register for the occurrence of selected wakeup conditions,

the device will not enter the HALT mode if any Wakeup bit is

both enabled and pending. Consequently, the user has the

responsibility of clearing the pending flags before attempting

to enter the HALT mode.

Multi-Input Wakeup

The Multi-Input Wakeup feature is used to return (wakeup)

the device from either the HALT or IDLE modes. Alternately

Multi-Input Wakeup/Interrupt feature may also be used to

generate up to 8 edge selectable external interrupts.

The WKEN, WKPND and WKEDG are all read/write regis-

ters, and are cleared at reset.

Figure 11 shows the Multi-Input Wakeup logic.

The Multi-Input Wakeup feature utilizes the L Port. The user

selects which particular L port bit (or combination of L Port

bits) will cause the device to exit the HALT or IDLE modes.

The selection is done through the Reg: WKEN. The Reg:

WKEN is an 8-bit read/write register, which contains a con-

trol bit for every L port bit. Setting a particular WKEN bit en-

ables a Wakeup from the associated L port pin.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

The user can select whether the trigger condition on the se-

lected L Port pin is going to be either a positive edge (low to

high transition) or a negative edge (high to low transition).

This selection is made via the Reg: WKEDG, which is an

8-bit control register with a bit assigned to each L Port pin.

Setting the control bit will select the trigger condition to be a

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16

Multi-Input Wakeup (Continued)

DS101134-16

FIGURE 11. Multi-Input Wake Up Logic

The GIE (global interrupt enable) bit enables the interrupt

function. A control flag, LPEN, functions as a global interrupt

enable for Port L interrupts. Setting the LPEN flag will enable

interrupts and vice versa. A separate global pending flag is

not needed since the register WKPND is adequate.

A/D Converter

The device contains an 8-channel, multiplexed input, suc-

cessive approximation, A/D converter. Two dedicated pins,

V_REFand AGND are provided for voltage reference.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

OPERATING MODES

The A/D converter supports ratiometric measurements. It

supports both Single Ended and Differential modes of opera-

tion.

Four specific analog channel selection modes are sup-

ported. These are as follows:

Allow any specific channel to be selected at one time. The

A/D converter performs the specific conversion requested

and stops.

The Wakeup signal will not start the chip running immedi-

ately since crystal oscillators or ceramic resonators have a fi-

nite start up time. The IDLE Timer (T0) generates a fixed de-

lay to ensure that the oscillator has indeed stabilized before

allowing the device to execute instructions. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is

loaded with a value of 256 and is clocked from the t_cinstruc-

tion cycle clock. The t_cclock is derived by dividing down the

oscillator clock by a factor of 10. A Schmitt trigger following

the CKI on-chip inverter ensures that the IDLE timer is

clocked only when the oscillator has a sufficiently large am-

plitude to meet the Schmitt trigger specifications. This

Schmitt trigger is not part of the oscillator closed loop. The

startup timeout from the IDLE timer enables the clock signals

to be routed to the rest of the chip.

Allow any specific channel to be scanned continuously. In

other words, the user will specify the channel and the A/D

converter will keep on scanning it continuously. The user can

come in at any arbitrary time and immediately read the result

of the last conversion. The user does not have to wait for the

current conversion to be completed.

Allow any differential channel pair to be selected at one time.

The A/D converter performs the specific differential conver-

sion requested and stops.

Allow any differential channel pair to be scanned continu-

ously. In other words, the user will specify the differential

channel pair and the A/D converter will keep on scanning it

continuously. The user can come in at any arbitrary time and

immediately read the result of the last differential conversion.

The user does not have to wait for the current conversion to

be completed.

If the RC clock option is used, the fixed delay is under soft-

ware control. A control flag, CLKDLY, in the G7 configuration

bit allows the clock start up delay to be optionally inserted.

Setting CLKDLY flag high will cause clock start up delay to

be inserted and resetting it will exclude the clock start up de-

lay. The CLKDLY flag is cleared during reset, so the clock

start up delay is not present following reset with the RC clock

options.

The A/D converter is supported by two memory mapped reg-

isters, the result register and the mode control register.

When the device is reset, the control register is cleared and

the A/D is powered down. The A/D result register has un-

known data following reset.

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PRESCALER SELECT

A/D Converter (Continued)

This 3-bit field is used to select one of the seven prescaler

clocks for the A/D converter. The prescaler also allows the

A/D clock inhibit power saving mode to be selected. The fol-

lowing table shows the various prescaler options.

A/D Control Register

A control register, Reg: ENAD, contains 3 bits for channel se-

lection, 3 bits for prescaler selection, and 2 bits for mode se-

lection. An A/D conversion is initiated by writing to the ENAD

control register. The result of the conversion is available to

the user from the A/D result register, Reg: ADRSLT.

Bit 2

Bit 1

Bit 0

Clock Select

Inhibit A/D clock

Divide by 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reg: ENAD

Divide by 2

CHANNEL

SELECT

MODE

SELECT

PRESCALER

SELECT

Divide by 4

Divide by 6

Bits 7, 6, 5

Bits 4,3

Bits 2, 1, 0

Divide by 12

Divide by 8

CHANNEL SELECT

This 3-bit field selects one of eight channels to be the V_IN+

The mode selection determines the V_IN−input.

.

Divide by 16

Single Ended mode:

ADC Operation

Bit 7

Bit 6

Bit 5

Channel No.

The A/D converter interface works as follows. Writing to the

A/D control register ENAD initiates an A/D conversion unless

the prescaler value is set to 0, in which case the ADC clock

is stopped and the ADC is powered down. The conversion

sequence starts at the beginning of the write to ENAD opera-

tion powering up the ADC. At the first falling edge of the con-

verter clock following the write operation (not counting the

falling edge if it occurs at the same time as the write opera-

tion ends), the sample signal turns on for two clock cycles.

The ADC is selected in the middle of the sample period. If the

ADC is in single conversion mode, the conversion complete

signal from the ADC will generate a power down for the A/D

converter. If the ADC is in continuous mode, the conversion

complete signal will restart the conversion sequence by de-

selecting the ADC for one converter clock cycle before start-

ing the next sample. The ADC 8-bit result is loaded into the

A/D result register (ADRSLT) except during LOAD clock

high, which prevents transient data (resulting from the ADC

writing a new result over an old one) being read from

ADRSLT.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

0

1

Differential mode:

Bit 7

Bit 6

Bit 5

Channel Pairs (+. −)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0, 1

1, 0

2, 3

3, 2

4, 5

5, 4

6, 7

7, 6

Inadvertant changes to the ENAD register during conversion

are prevented by the control logic of the A/D. Any attempt to

write any bit of the ENAD Register except ADBSY, while

ADBSY is a one, is ignored. ADBSY must be cleared either

by completion of an A/D conversion or by the user before the

prescaler, conversion mode or channel select values can be

changed. After stopping the current conversion, the user can

load different values for the prescaler, conversion mode or

channel select and start a new conversion in one instruction.

MODE SELECT

This 2-bit field is used to select the mode of operation (single

conversion, continuous conversions, differential, single

ended) as shown in the following table.

Bit 4

Bit 3

Mode

It is important for the user to realize that, when used in differ-

ential mode, only the positive input to the A/D converter is

sampled and held. The negative input is constantly con-

nected and should be held stable for the duration of the con-

version. Failure to maintain a stable negative input will result

in incorrect conversion.

0

1

Single Ended mode, single conversion

Single Ended mode, continuous scan

of a single channel into the result

register

1

0

1

Differential mode, single conversion

PRESCALER

Differential mode, continuous scan of

a channel pair into the result register

The A/D Converter (ADC) contains a prescaler option which

allows seven different clock selections. The A/D clock fre-

quency is equal to CKI divided by the prescaler value. Note

that the prescaler value must be chosen such that the A/D

clock falls within the specified range. The maximum A/D fre-

quency is 1.67 MHz. This equates to a 600 ns ADC clock

cycle.

The A/D converter takes 12 ADC clock cycles to complete a

conversion. Thus the minimum ADC conversion time for the

device is 7.2 µs when a prescaler of 6 has been selected.

These 12 ADC clock cycles necessary for a conversion con-

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18

Analog Input and Source Resistance Considerations

A/D Converter (Continued)

Figure 12 shows the A/D pin model in single ended mode.

The differential mode has similiar A/D pin model. The leads

to the analog inputs should be kept as short as possible.

Both noise and digital clock coupling to an A/D input can

cause conversion errors. The clock lead should be kept

away from the analog input line to reduce coupling. The A/D

channel input pins do not have any internal output driver cir-

cuitry connected to them because this circuitry would load

the analog input signals due to output buffer leakage current.

sist of 1 cycle at the beginning for reset, 2 cycles for sam-

pling, 8 cycles for converting, and 1 cycle for loading the re-

sult into the A/D result register (ADRSLT). This A/D result

register is a read-only register. The device cannot write into

ADRSLT.

The prescaler also allows an A/D clock inhibit option, which

saves power by powering down the A/D when it is not in use.

Note: The A/D converter is also powered down when the device is in either

the HALT or IDLE modes. If the ADC is running when the device enters

the HALT or IDLE modes, the ADC will power down during the HALT or

IDLE, and then will reinitialize the conversion when the device comes

out of the HALT or IDLE modes.

DS101134-28

*The analog switch is closed only during the sample time.

FIGURE 12. A/D Pin Model (Single Ended Mode)

Source impedances greater than 1 kΩ on the analog input

lines will adversely affect internal RC charging time during in-

put sampling. As shown in Figure 12, the analog switch to

the DAC array is closed only during the 2 A/D cycle sample

time. Large source impedances on the analog inputs may re-

sult in the DAC array not being charged to the correct volt-

age levels, causing scale errors.

Interrupts

INTRODUCTION

Each device supports nine vectored interrupts. Interrupt

sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L

Wakeup, Software Trap, MICROWIRE/PLUS, and External

Input.

If large source resistance is necessary, the recommended

solution is to slow down the A/D clock speed in proportion to

the source resistance. The A/D converter may be operated

at the maximum speed for R_Sless than 1 kΩ. For R_Sgreater

than 1 kΩ, A/D clock speed needs to be reduced. For ex-

ample, with R_S= 2 kΩ, the A/D converter may be operated

at half the maximum speed. A/D converter clock speed may

be slowed down by either increasing the A/D prescaler

divide-by or decreasing the CKI clock frequency. The A/D

clock speed may be reduced to its minimum frequency of

100 kHz.

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

The Software trap has the highest priority while the default

VIS has the lowest priority.

Each of the 9 maskable inputs has a fixed arbitration ranking

and vector.

Figure 13 shows the Interrupt Block Diagram.

19

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Interrupts (Continued)

DS101134-18

FIGURE 13. Interrupt Block Diagram

MASKABLE INTERRUPTS

edged until the start of the next normally executed instruction

is to be skipped, the skip is performed before the pending in-

terrupt is acknowledged.

All interrupts other than the Software Trap are maskable.

Each maskable interrupt has an associated enable bit and

pending flag bit. The pending bit is set to 1 when the interrupt

condition occurs. The state of the interrupt enable bit, com-

bined with the GIE bit determines whether an active pending

flag actually triggers an interrupt. All of the maskable inter-

rupt pending and enable bits are contained in mapped con-

trol registers, and thus can be controlled by the software.

At the start of interrupt acknowledgment, the following ac-

tions occur:

1. The GIE bit is automatically reset to zero, preventing any

subsequent maskable interrupt from interrupting the cur-

rent service routine. This feature prevents one maskable

interrupt from interrupting another one being serviced.

A maskable interrupt condition triggers an interrupt under the

following conditions:

2. The address of the instruction about to be executed is

pushed onto the stack.

1. The enable bit associated with that interrupt is set.

2. The GIE bit is set.

3. The program counter (PC) is loaded with 00FF Hex,

causing a jump to that program memory location.

3. The device is not processing a non-maskable interrupt.

The device requires seven instruction cycles to perform the

actions listed above.

(If

a non-maskable interrupt is being serviced, a

maskable interrupt must wait until that service routine is

completed.)

If the user wishes to allow nested interrupts, the interrupts

service routine may set the GIE bit to 1 by writing to the PSW

register, and thus allow other maskable interrupts to interrupt

the current service routine. If nested interrupts are allowed,

caution must be exercised. The user must write the program

in such a way as to prevent stack overflow, loss of saved

context information, and other unwanted conditions.

An interrupt is triggered only when all of these conditions are

met at the beginning of an instruction. If different maskable

interrupts meet these conditions simultaneously, the highest

priority interrupt will be serviced first, and the other pending

interrupts must wait.

Upon Reset, all pending bits, individual enable bits, and the

GIE bit are reset to zero. Thus, a maskable interrupt condi-

tion cannot trigger an interrupt until the program enables it by

setting both the GIE bit and the individual enable bit. When

enabling an interrupt, the user should consider whether or

not a previously activated (set) pending bit should be ac-

knowledged. If, at the time an interrupt is enabled, any pre-

vious occurrences of the interrupt should be ignored, the as-

sociated pending bit must be reset to zero prior to enabling

the interrupt. Otherwise, the interrupt may be simply en-

abled; if the pending bit is already set, it will immediately trig-

ger an interrupt. A maskable interrupt is active if its associ-

ated enable and pending bits are set.

The interrupt service routine stored at location 00FF Hex

should use the VIS instruction to determine the cause of the

interrupt, and jump to the interrupt handling routine corre-

sponding to the highest priority enabled and active interrupt.

Alternately, the user may choose to poll all interrupt pending

and enable bits to determine the source(s) of the interrupt. If

more than one interrupt is active, the user’s program must

decide which interrupt to service.

Within a specific interrupt service routine, the associated

pending bit should be cleared. This is typically done as early

as possible in the service routine in order to avoid missing

the next occurrence of the same type of interrupt event.

Thus, if the same event occurs a second time, even while the

first occurrence is still being serviced, the second occur-

rence will be serviced immediately upon return from the cur-

rent interrupt routine.

An interrupt is an asychronous event which may occur be-

fore, during, or after an instruction cycle. Any interrupt which

occurs during the execution of an instruction is not acknowl-

An interrupt service routine typically ends with an RETI in-

struction. This instruction sets the GIE bit back to 1, pops the

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20

The interrupt sources in the vector table are listed in order of

rank, from highest to lowest priority. If two or more enabled

and pending interrupts are detected at the same time, the

one with the highest priority is serviced first. Upon return

from the interrupt service routine, the next highest-level

pending interrupt is serviced.

Interrupts (Continued)

address stored on the stack, and restores that address to the

program counter. Program execution then proceeds with the

next instruction that would have been executed had there

been no interrupt. If there are any valid interrupts pending,

the highest-priority interrupt is serviced immediately upon re-

turn from the previous interrupt.

If the VIS instruction is executed, but no interrupts are en-

abled and pending, the lowest-priority interrupt vector is

used, and a jump is made to the corresponding address in

the vector table. This is an unusual occurrence, and may be

the result of an error. It can legitimately result from a change

in the enable bits or pending flags prior to the execution of

the VIS instruction, such as executing a single cycle instruc-

tion which clears an enable flag at the same time that the

pending flag is set. It can also result, however, from inadvert-

ent execution of the VIS command outside of the context of

an interrupt.

VIS INSTRUCTION

The general interrupt service routine, which starts at address

00FF Hex, must be capable of handling all types of inter-

rupts. The VIS instruction, together with an interrupt vector

table, directs the device to the specific interrupt handling rou-

tine based on the cause of the interrupt.

VIS is a single-byte instruction, typically used at the very be-

ginning of the general interrupt service routine at address

00FF Hex, or shortly after that point, just after the code used

for context switching. The VIS instruction determines which

enabled and pending interrupt has the highest priority, and

causes an indirect jump to the address corresponding to that

interrupt source. The jump addresses (vectors) for all pos-

sible interrupts sources are stored in a vector table.

The default VIS interrupt vector can be useful for applica-

tions in which time critical interrupts can occur during the

servicing of another interrupt. Rather than restoring the pro-

gram context (A, B, X, etc.) and executing the RETI instruc-

tion, an interrupt service routine can be terminated by return-

ing to the VIS instruction. In this case, interrupts will be

serviced in turn until no further interrupts are pending and

the default VIS routine is started. After testing the GIE bit to

ensure that execution is not erroneous, the routine should

restore the program context and execute the RETI to return

to the interrupted program.

The vector table may be as long as 32 bytes (maximum of 16

vectors) and resides at the top of the 256-byte block contain-

ing the VIS instruction. However, if the VIS instruction is at

the very top of a 256-byte block (such as at 00FF Hex), the

vector table resides at the top of the next 256-byte block.

Thus, if the VIS instruction is located somewhere between

00FF and 01DF Hex (the usual case), the vector table is lo-

cated between addresses 01E0 and 01FF Hex. If the VIS in-

struction is located between 01FF and 02DF Hex, then the

vector table is located between addresses 02E0 and 02FF

Hex, and so on.

This technique can save up to fifty instruction cycles (t_c), or

more, (50µs at 10 MHz oscillator) of latency for pending in-

terrupts with a penalty of fewer than ten instruction cycles if

no further interrupts are pending.

To ensure reliable operation, the user should always use the

VIS instruction to determine the source of an interrupt. Al-

though it is possible to poll the pending bits to detect the

source of an interrupt, this practice is not recommended. The

use of polling allows the standard arbitration ranking to be al-

tered, but the reliability of the interrupt system is compro-

mised. The polling routine must individually test the enable

and pending bits of each maskable interrupt. If a Software

Trap interrupt should occur, it will be serviced last, even

though it should have the highest priority. Under certain con-

ditions, a Software Trap could be triggered but not serviced,

resulting in an inadvertent “locking out” of all maskable inter-

rupts by the Software Trap pending flag. Problems such as

this can be avoided by using VIS instruction.

Each vector is 15 bits long and points to the beginning of a

specific interrupt service routine somewhere in the 32 kbyte

memory space. Each vector occupies two bytes of the vector

table, with the higher-order byte at the lower address. The

vectors are arranged in order of interrupt priority. The vector

of the maskable interrupt with the lowest rank is located to

0yE0 (higher-order byte) and 0yE1 (lower-order byte). The

next priority interrupt is located at 0yE2 and 0yE3, and so

forth in increasing rank. The Software Trap has the highest

rank and its vector is always located at 0yFE and 0yFF. The

number of interrupts which can become active defines the

size of the table.

Table 3 shows the types of interrupts, the interrupt arbitration

ranking, and the locations of the corresponding vectors in

the vector table.

The vector table should be filled by the user with the memory

locations of the specific interrupt service routines. For ex-

ample, if the Software Trap routine is located at 0310 Hex,

then the vector location 0yFE and -0yFF should contain the

data 03 and 10 Hex, respectively. When a Software Trap in-

terrupt occurs and the VIS instruction is executed, the pro-

gram jumps to the address specified in the vector table.

21

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Interrupts (Continued)

TABLE 3. Interrupt Vector Table

Description

Arbitration

Ranking

Vector Address

Hi-Low Byte

0yFE–0yFF

0yFC–0yFD

0yFA–0yFB

0yF8–0yF9

0yF6–0yF7

0yF4–0yF5

0yF2–0yF3

0yF0–0yF1

0yEE–0yEF

0yEC–0yED

0yEA–0yEB

0yE8–0yE9

0yE6–0yE7

0yE4–0yE5

0yE2–0yE3

0yE0–0yE1

Source

Software

(1) Highest

INTR Instruction

for Future Use

Pin G0 Edge

Underflow

Reserved

External

(2)

(3)

(4)

(5)

(6)

Timer T0

Timer T1

T1A/Underflow

T1B

Timer T1

MICROWIRE/PLUS

Reserved

Timer T2

BUSY Goes Low

for Future Use

for UART

(7)

(8)

T2A/Underflow

T2B

Timer T2

Reserved

Port L/Wakeup

Default

for Future Use

Port L Edge

(9)

(10) Lowest

VIS Instr. Execution without

Any Interrupts

Note 11: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad-

dress of a block. In this case, the table must be in the next block.

VIS Execution

vector of the active interrupt with the highest arbitration rank-

ing. This vector is read from program memory and placed

into the PC which is now pointed to the 1st instruction of the

service routine of the active interrupt with the highest arbitra-

tion ranking.

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc...) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FA is generated and so forth. If the only active inter-

rupt is software trap, than E0 is generated. This number re-

places the lower byte of the PC. The upper byte of the PC re-

mains unchanged. The new PC is therefore pointing to the

Figure 14 illustrates the different steps performed by the VIS

instruction. Figure 15 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

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Interrupts (Continued)

DS101134-41

FIGURE 14. VIS Operation

DS101134-40

FIGURE 15. VIS Flowchart

23

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Interrupts (Continued)

Programming Example: External Interrupt

PSW

CNTRL

RBIT

SBIT

JP

=00EF

=00EE

0,PORTGC

0,PORTGD

IEDG, CNTRL

EXEN, PSW

GIE, PSW

WAIT

; G0 pin configured Hi-Z

; Ext interrupt polarity; falling edge

; Enable the external interrupt

; Set the GIE bit

WAIT:

; Wait for external interrupt

.

.=0FF

VIS

; The interrupt causes a

; branch to address 0FF

; The VIS causes a branch to

;interrupt vector table

.

.=01FA

.ADDRW SERVICE

; Vector table (within 256 byte

; of VIS inst.) containing the ext

; interrupt service routine

.

INT_EXIT:

SERVICE:

RETI

.

RBIT

EXPND, PSW

; Interrupt Service Routine

; Reset ext interrupt pend. bit

.

JP

INT_EXIT

; Return, set the GIE bit

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24

flag; upon return to the first Software Trap routine, the

STPND flag will have the wrong state. This will allow

maskable interrupts to be acknowledged during the servicing

of the first Software Trap. To avoid problems such as this, the

user program should contain the Software Trap routine to

perform a recovery procedure rather than a return to normal

execution.

Interrupts (Continued)

NON-MASKABLE INTERRUPT

Pending Flag

There is a pending flag bit associated with the non-maskable

interrupt, called STPND. This pending flag is not memory-

mapped and cannot be accessed directly by the software.

Under normal conditions, the STPND flag is reset by a

RPND instruction in the Software Trap service routine. If a

programming error or hardware condition (brownout, power

supply glitch, etc.) sets the STPND flag without providing a

way for it to be cleared, all other interrupts will be locked out.

To alleviate this condition, the user can use extra RPND in-

structions in the main program and in the WATCHDOG ser-

vice routine (if present). There is no harm in executing extra

RPND instructions in these parts of the program.

The pending flag is reset to zero when a device Reset oc-

curs. When the non-maskable interrupt occurs, the associ-

ated pending bit is set to 1. The interrupt service routine

should contain an RPND instruction to reset the pending flag

to zero. The RPND instruction always resets the STPND

flag.

Software Trap

The Software Trap is a special kind of non-maskable inter-

rupt which occurs when the INTR instruction (used to ac-

knowledge interrupts) is fetched from program memory and

placed in the instruction register. This can happen in a vari-

ety of ways, usually because of an error condition. Some ex-

amples of causes are listed below.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

If the program counter incorrectly points to a memory loca-

tion beyond the available program memory space, the non-

existent or unused memory location returns zeroes which is

interpreted as the INTR instruction.

If the stack is popped beyond the allowed limit (address 06F

Hex), a 7FFF will be loaded into the PC, if this last location in

program memory is unprogrammed or unavailable, a Soft-

ware Trap will be triggered.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

A Software Trap can be triggered by a temporary hardware

condition such as a brownout or power supply glitch.

The Software Trap has the highest priority of all interrupts.

When a Software Trap occurs, the STPND bit is set. The GIE

bit is not affected and the pending bit (not accessible by the

user) is used to inhibit other interrupts and to direct the pro-

gram to the ST service routine with the VIS instruction. Noth-

ing can interrupt a Software Trap service routine except for

another Software Trap. The STPND can be reset only by the

RPND instruction or a chip Reset.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

The Software Trap indicates an unusual or unknown error

condition. Generally, returning to normal execution at the

point where the Software Trap occurred cannot be done re-

liably. Therefore, the Software Trap service routine should

reinitialize the stack pointer and perform a recovery proce-

dure that restarts the software at some known point, similar

to a device Reset, but not necessarily performing all the

same functions as a device Reset. The routine must also ex-

ecute the RPND instruction to reset the STPND flag. Other-

wise, all other interrupts will be locked out. To the extent pos-

sible, the interrupt routine should record or indicate the

context of the device so that the cause of the Software Trap

can be determined.

INTERRUPT SUMMARY

The device uses the following types of interrupts, listed be-

low in order of priority:

1. The Software Trap non-maskable interrupt, triggered by

the INTR (00 opcode) instruction. The Software Trap is

acknowledged immediately. This interrupt service rou-

tine can be interrupted only by another Software Trap.

The Software Trap should end with two RPND instruc-

tions followed by a restart procedure.

2. Maskable interrupts, triggered by an on-chip peripheral

block or an external device connected to the device. Un-

der ordinary conditions, a maskable interrupt will not in-

If the user wishes to return to normal execution from the

point at which the Software Trap was triggered, the user

must first execute RPND, followed by RETSK rather than

RETI or RET. This is because the return address stored on

the stack is the address of the INTR instruction that triggered

the interrupt. The program must skip that instruction in order

to proceed with the next one. Otherwise, an infinite loop of

Software Traps and returns will occur.

terrupt any other interrupt routine in progress.

maskable interrupt routine in progress can be inter-

rupted by the non-maskable interrupt request.

maskable interrupt routine should end with an RETI in-

struction or, prior to restoring context, should return to

execute the VIS instruction. This is particularly useful

when exiting long interrupt service routiness if the time

between interrupts is short. In this case the RETI instruc-

tion would only be executed when the default VIS rou-

tine is reached.

A

Programming a return to normal execution requires careful

consideration. If the Software Trap routine is interrupted by

another Software Trap, the RPND instruction in the service

routine for the second Software Trap will reset the STPND

25

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WATCHDOG

WATCHDOG Operation

The device contains a WATCHDOG and clock monitor. The

WATCHDOG is designed to detect the user program getting

stuck in infinite loops resulting in loss of program control or

“runaway” programs. The Clock Monitor is used to detect the

absence of a clock or a very slow clock below a specified

rate on the CKI pin.

The WATCHDOG and Clock Monitor are disabled during re-

set. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR reg-

ister involves two irrevocable choices: (i) the selection of the

WATCHDOG service window (ii) enabling or disabling of the

Clock Monitor. Hence, the first write to WDSVR Register in-

volves selecting or deselecting the Clock Monitor, select the

WATCHDOG service window and match the WATCHDOG

key data. Subsequent writes to the WDSVR register will

compare the value being written by the user to the WATCH-

DOG service window value and the key data (bits 7 through

1) in the WDSVR Register. Table 6 shows the sequence of

events that can occur.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 4 shows the WDSVR register.

TABLE 4. WATCHDOG Service Register (WDSVR)

Window

Select

Clock

Key Data

Monitor

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The WATCH-

DOG may not be serviced more than once in every lower

limit of the service window. The user may service the

WATCHDOG as many times as wished in the time period be-

tween the lower and upper limits of the service window. The

first write to the WDSVR Register is also counted as a

WATCHDOG service.

X

7

X

6

0

5

1

4

1

3

0

2

0

1

Y

0

The lower limit of the service window is fixed at 2048 instruc-

tion cycles. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 5 shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the port G. WDOUT is active

low. The WDOUT pin is in the high impedance state in the in-

active state. Upon triggering the WATCHDOG, the logic will

pull the WDOUT (G1) pin low for an additional 16 t_c–32 t_c

cycles after the signal level on WDOUT pin goes below the

lower Schmitt trigger threshold. After this delay, the device

will stop forcing the WDOUT output low.

TABLE 5. WATCHDOG Service Window Select

WDSVR WDSVR

Clock

Service Window

(Lower-Upper Limits)

2048–8k t_CCycles

Bit 7

Bit 6

Monitor

0

1

x

0

1

0

1

x

0

1

The WATCHDOG service window will restart when the WD-

OUT pin goes high. It is recommended that the user tie the

WDOUT pin back to V_CCthrough a resistor in order to pull

WDOUT high.

2048–16k t_CCycles

2048–32k t_CCycles

2048–64k t_CCycles

Clock Monitor Disabled

Clock Monitor Enabled

A WATCHDOG service while the WDOUT signal is active will

be ignored. The state of the WDOUT pin is not guaranteed

on reset, but if it powers up low then the WATCHDOG will

time out and WDOUT will enter high impedance state.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error. The Clock Monitor error will continue

until the clock frequency has reached the minimum specified

value, after which the G1 output will enter the high imped-

ance TRI-STATE mode following 16 t_c–32 t_cclock cycles.

The Clock Monitor generates a continual Clock Monitor error

if the oscillator fails to start, or fails to reach the minimum

specified frequency. The specification for the Clock Monitor

is as follows:

Clock Monitor

The Clock Monitor aboard the device can be selected or de-

selected under program control. The Clock Monitor is guar-

anteed not to reject the clock if the instruction cycle clock (1/

t_c) is greater or equal to 10 kHz. This equates to a clock input

rate on CKI of greater or equal to 100 kHz.

>

1/t_c10 kHz—No clock rejection.

<

1/t_c10 Hz—Guaranteed clock rejection.

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26

WATCHDOG Operation (Continued)

TABLE 6. WATCHDOG Service Actions

Key

Window

Data

Clock

Monitor

Match

Action

Data

Match

Valid Service: Restart Service Window

Error: Generate WATCHDOG Output

Don’t Care

Mismatch

Don’t Care

Mismatch

Don’t Care

Mismatch

WATCHDOG AND CLOCK MONITOR SUMMARY

•

Following RESET, the initial WATCHDOG service (where

the service window and the CLOCK MONITOR enable/

disable must be selected) may be programmed anywhere

within the maximum service window (65,536 instruction

cycles) initialized by RESET. Note that this initial WATCH-

DOG service may be programmed within the initial 2048

instruction cycles without causing a WATCHDOG error.

The following salient points regarding the WATCHDOG and

CLOCK MONITOR should be noted:

•

Both the WATCHDOG and Clock Monitor detector circuits

are inhibited during RESET.

•

Following RESET, the WATCHDOG and CLOCK MONI-

TOR are both enabled, with the WATCHDOG having the

maximum service window selected.

Detection of Illegal Conditions

The device can detect various illegal conditions resulting

from coding errors, transient noise, power supply voltage

drops, runaway programs, etc.

•

The WATCHDOG service window and Clock Monitor

enable/disable option can only be changed once, during

the initial WATCHDOG service following RESET.

The initial WATCHDOG service must match the key data

value in the WATCHDOG Service register WDSVR in or-

der to avoid a WATCHDOG error.

Reading of undefined ROM gets zeros. The opcode for soft-

ware interrupt is zero. If the program fetches instructions

from undefined ROM, this will force a software interrupt, thus

signaling that an illegal condition has occurred.

Subsequent WATCHDOG services must match all three

data fields in WDSVR in order to avoid WATCHDOG er-

rors.

The subroutine stack grows down for each call (jump to sub-

routine), interrupt, or PUSH, and grows up for each return or

POP. The stack pointer is initialized to RAM location 06F Hex

during reset. Consequently, if there are more returns than

calls, the stack pointer will point to addresses 070 and 071

Hex (which are undefined RAM). Undefined RAM from ad-

dresses 070 to 07F Hex is read as all 1’s, which in turn will

cause the program to return to address 7FFF Hex. This is an

undefined ROM location and the instruction fetched (all 0’s)

from this location will generate a software interrupt signaling

an illegal condition.

The correct key data value cannot be read from the

WATCHDOG Service register WDSVR. Any attempt to

read this key data value of 01100 from WDSVR will read

as key data value of all 0’s.

•

The WATCHDOG detector circuit is inhibited during both

the HALT and IDLE modes.

The Clock Monitor detector circuit is active during both

the HALT and IDLE modes. Consequently, the device in-

advertently entering the HALT mode will be detected as a

Clock Monitor error (provided that the Clock Monitor en-

able option has been selected by the program).

Thus, the chip can detect the following illegal conditions:

1. Executing from undefined ROM

•

With the single-pin R/C oscillator mask option selected

and the CLKDLY bit reset, the WATCHDOG service win-

dow will resume following HALT mode from where it left

off before entering the HALT mode.

2. Over “POP”ing the stack by having more returns than

calls.

When the software interrupt occurs, the user can re-initialize

the stack pointer and do a recovery procedure before restart-

ing (this recovery program is probably similar to that follow-

ing reset, but might not contain the same program initializa-

tion procedures).

With the crystal oscillator mask option selected, or with

the single-pin R/C oscillator mask option selected and the

CLKDLY bit set, the WATCHDOG service window will be

set to its selected value from WDSVR following HALT.

Consequently, the WATCHDOG should not be serviced

for at least 2048 instruction cycles following HALT, but

must be serviced within the selected window to avoid a

WATCHDOG error.

MICROWIRE/PLUS

MICROWIRE/PLUS is a serial synchronous communications

interface. The MICROWIRE/PLUS capability enables the de-

vice to interface with any of National Semiconductor’s MI-

CROWIRE peripherals (i.e. A/D converters, display drivers,

E²PROMs etc.) and with other microcontrollers which sup-

port the MICROWIRE interface. It consists of an 8-bit serial

shift register (SIO) with serial data input (SI), serial data out-

put (SO) and serial shift clock (SK). Figure 16 shows a block

diagram of the MICROWIRE/PLUS logic.

•

The IDLE timer T0 is not initialized with RESET.

The user can sync in to the IDLE counter cycle with an

IDLE counter (T0) interrupt or by monitoring the T0PND

flag. The T0PND flag is set whenever the thirteenth bit of

the IDLE counter toggles (every 4096 instruction cycles).

The user is responsible for resetting the T0PND flag.

•

A hardware WATCHDOG service occurs just as the de-

vice exits the IDLE mode. Consequently, the WATCH-

DOG should not be serviced for at least 2048 instruction

cycles following IDLE, but must be serviced within the se-

lected window to avoid a WATCHDOG error.

27

www.national.com

TABLE 7. MICROWIRE/PLUS

Master Mode Clock Selection

MICROWIRE/PLUS (Continued)

SL1

0

SL0

SK

0

1

x

2 x t_c

4 x t_c

8 x t_c

0

1

Where t_cis the instruction cycle clock

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave. Figure 17 shows how

two COP888CF microcontrollers and several peripherals

may be interconnected using the MICROWIRE/PLUS ar-

rangements.

DS101134-20

FIGURE 16. MICROWIRE/PLUS Block Diagram

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS ar-

rangement with the internal clock source is called the Master

mode of operation. Similarly, operating the MICROWIRE/

PLUS arrangement with an external shift clock is called the

Slave mode of operation.

Warning:

The SIO register should only be loaded when the SK clock is

low. Loading the SIO register while the SK clock is high will

result in undefined data in the SIO register. SK clock is nor-

mally low when not shifting.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the mas-

ter mode the SK clock rate is selected by the two bits, SL0

and SL1, in the CNTRL register. Table 7 details the different

clock rates that may be selected.

Setting the BUSY flag when the input SK clock is high in the

MICROWIRE/PLUS slave mode may cause the current SK

clock for the SIO shift register to be narrow. For safety, the

BUSY flag should only be set when the input SK clock is low.

MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE

Master always initiates all data exchanges. The MSEL bit in

the CNTRL register must be set to enable the SO and SK

functions onto the G Port. The SO and SK pins must also be

selected as outputs by setting appropriate bits in the Port G

configuration register. Table 8 summarizes the bit settings

required for Master mode of operation.

DS101134-21

FIGURE 17. MICROWIRE/PLUS Application

www.national.com

28

MICROWIRE/PLUS (Continued)

Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space

MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and re-

setting the appropriate bit in the Port G configuration regis-

ter. Table 8 summarizes the settings required to enter the

Slave mode of operation.

Address

00 to 6F

Contents

On-Chip RAM bytes

70 to BF

C0

Unused RAM Address Space

Timer T2 Lower Byte

C1

Timer T2 Upper Byte

C2

Timer T2 Autoload Register T2RA Lower Byte

Timer T2 Autoload Register T2RA Upper Byte

Timer T2 Autoload Register T2RB Lower Byte

Timer T2 Autoload Register T2RB Upper Byte

Timer T2 Control Register

C3

C4

TABLE 8. MICROWIRE/PLUS Mode Settings

This table assumes that the control flag MSEL is set.

C5

C6

G4 (SO)

Config. Bit

1

G5 (SK)

Config. Bit

1

G4

Fun.

SO

G5

Fun.

Int.

Operation

C7

WATCHDOG Service Register (Reg:WDSVR)

MIWU Edge Select Register (Reg:WKEDG)

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

A/D Converter Control Register (Reg:ENAD)

A/D Converter Result Register (Reg: ADRSLT)

Reserved

C8

MICROWIRE/PLUS

Master

C9

SK

CA

0

1

0

1

0

TRI-

STATE

SO

Int.

MICROWIRE/PLUS

Master

CB

SK

CC

Ext. MICROWIRE/PLUS

SK Slave

Ext. MICROWIRE/PLUS

SK Slave

CD to CF

D0

Port L Data Register

TRI-

D1

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

STATE

D2

The user must set the BUSY flag immediately upon entering

the Slave mode. This will ensure that all data bits sent by the

Master will be shifted properly. After eight clock pulses the

BUSY flag will be cleared and the sequence may be re-

peated.

D3

D4

Port G Data Register

D5

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Port C Data Register

D6

D7

Alternate SK Phase Operation

D8

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK is normally low. In the normal mode

data is shifted in on the rising edge of the SK clock and the

data is shifted out on the falling edge of the SK clock. The

SIO register is shifted on each falling edge of the SK clock in

the normal mode. In the alternate SK phase mode the SIO

register is shifted on the rising edge of the SK clock.

D9

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

DA

DB

DC

Port D Data Register

DD to DF

E0 to E5

E6

Reserved for Port D

Reserved

Timer T1 Autoload Register T1RB Lower Byte

Timer T1 Autoload Register T1RB Upper Byte

ICNTRL Register

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configura-

tion bit. The SKSEL flag will power up in the reset condition,

selecting the normal SK signal.

E7

E8

E9

MICROWIRE Shift Register

Timer T1 Lower Byte

EA

EB

Timer T1 Upper Byte

EC

Timer T1 Autoload Register T1RA Lower Byte

Timer T1 Autoload Register T1RA Upper Byte

CNTRL Control Register

ED

EE

EF

PSW Register

F0 to FB

FC

On-Chip RAM Mapped as Registers

X Register

FD

SP Register

FE

B Register

FF

Reserved

Note: Reading memory locations 70-7F Hex will return all ones. Reading

other unused memory locations will return undefined data.

29

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TRANSFER OF CONTROL ADDRESSING MODES

Relative

Addressing Modes

The device has ten addressing modes, six for operand ad-

dressing and four for transfer of control.

This mode is used for the JP instruction, with the instruction

field being added to the program counter to get the new pro-

gram location. JP has a range from −31 to +32 to allow a

1-byte relative jump (JP + 1 is implemented by a NOP in-

struction). There are no “pages” when using JP, since all 15

bits of PC are used.

OPERAND ADDRESSING MODES

Register Indirect

This is the “normal” addressing mode. The operand is the

data memory addressed by the B pointer or X pointer.

Register Indirect (with auto post increment or

decrement of pointer)

Absolute

This mode is used with the JMP and JSR instructions, with

the instruction field of 12 bits replacing the lower 12 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory segment.

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

pointer or X pointer. This is a register indirect mode that au-

tomatically post increments or decrements the B or X regis-

ter after executing the instruction.

Absolute Long

Direct

This mode is used with the JMPL and JSRL instructions, with

the instruction field of 15 bits replacing the entire 15 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory space.

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

Immediate

The instruction contains an 8-bit immediate field as the oper-

and.

Indirect

This mode is used with the JID instruction. The contents of

the accumulator are used as a partial address (lower 8 bits of

PC) for accessing a location in the program memory. The

contents of this program memory location serve as a partial

address (lower 8 bits of PC) for the jump to the next instruc-

tion.

Short Immediate

This addressing mode is used with the Load B Immediate in-

struction. The instruction contains a 4-bit immediate field as

the operand.

Indirect

This addressing mode is used with the LAID instruction. The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

Note: The VIS is a special case of the Indirect Transfer of Control addressing

mode, where the double byte vector associated with the interrupt is

transferred from adjacent addresses in the program memory into the

program counter (PC) in order to jump to the associated interrupt ser-

vice routine.

Instruction Set

Register and Symbol Definition

Registers

Symbols

Registers

A

8-Bit Accumulator Register

8-Bit Address Register

Reg

Register Memory: Addresses F0 to FF

(Includes B, X and SP)

B

Bit

←

↔

Bit Number (0 to 7)

Loaded with

X

8-Bit Address Register

SP

PC

PU

PL

C

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

Exchanged with

Lower 8 Bits of PC

1-Bit of PSW Register for Carry

1-Bit of PSW Register for Half Carry

HC

GIE

1-Bit of PSW Register for Global Interrupt

Enable

VU

VL

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

Symbols

[B]

Memory Indirectly Addressed by B Register

Memory Indirectly Addressed by X Register

Direct Addressed Memory

[X]

MD

Mem

Meml

Direct Addressed Memory or [B]

Direct Addressed Memory or [B] or Immediate

Data

Imm

8-Bit Immediate Data

www.national.com

30

Instruction Set (Continued)

INSTRUCTION SET

←

ADD

ADC

A,Meml

ADD

A

A + Meml

←

Carry

ADD with Carry

A + Meml + C, C

←

HC

Half Carry

←

Carry

SUBC

A,Meml

Subtract with Carry

A

A Meml + C, C

←

HC

Half Carry

←

AND

ANDSZ

OR

A,Meml

A,Imm

A,Meml

MD,Imm

A,Meml

#

Logical AND

A

A and Meml

Logical AND Immed., Skip if Zero

Logical OR

Skip next if (A and Imm) = 0

←

A

A or Meml

XOR

IFEQ

IFNE

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

RPND

X

Logical EXclusive OR

IF EQual

A xor Meml

Compare MD and Imm, Do next if MD = Imm

Compare A and Meml, Do next if A = Meml

IF EQual

≠

Compare A and Meml, Do next if A Meml

IF Not Equal

>

IF Greater Than

Compare A and Meml, Do next if A Meml

≠

If B Not Equal

Do next if lower 4 bits of B Imm

←

Reg− 1, Skip if Reg = 0

Reg

Decrement Reg., Skip if Zero

Set BIT

Reg

#

,Mem

1 to bit, Mem (bit = 0 to 7 immediate)

0 to bit, Mem

Reset BIT

IF BIT

If bit in A or Mem is true do next instruction

Reset Software Interrupt Pending Flag

Reset PeNDing Flag

EXchange A with Memory

EXchange A with Memory [X]

LoaD A with Memory

LoaD A with Memory [X]

LoaD B with Immed.

LoaD Memory Immed

LoaD Register Memory Immed.

EXchange A with Memory [B]

EXchange A with Memory [X]

LoaD A with Memory [B]

LoaD A with Memory [X]

LoaD Memory [B] Immed.

CLeaR A

↔

←

A,Mem

A,[X]

A

B

Mem

[X]

X

LD

A,Meml

A,[X]

Meml

[X]

LD

B,Imm

Imm

←

LD

Mem,Imm

Reg,Imm

Mem

Reg

Imm

←

LD

Imm

↔

←

±

X

A, [B

A, [X

]

A

[B], (B

[X], (X

B

±

1)

↔

X

A

1)

←

B

±

1)

LD

A, [B ]

A

[B], (B

[X], (X

←

X 1)

±

LD

A, [X ]

←

B 1)

±

LD

[B ],Imm

[B] Imm, (B

←

CLR

INC

A

C

0

←

INCrement A

A + 1

A − 1

←

→

←

DEC

LAID

DCOR

RRC

RLC

SWAP

SC

DECrementA

Load A InDirect from ROM

Decimal CORrect A

Rotate A Right thru C

Rotate A Left thru C

SWAP nibbles of A

Set C

ROM (PU,A)

A

BCD correction of A (follows ADC, SUBC)

→

←

→

A0 C

A7

…

←

C

A0

↔

A7…A4

A3…A0

←

C

1, HC

0, HC

1

0

RC

Reset C

IFC

IF C

IF C is true, do next instruction

IFNC

POP

PUSH

VIS

IF Not C

If C is not true, do next instruction

←

A

POP the stack into A

PUSH A onto the stack

Vector to Interrupt Service Routine

Jump absolute Long

Jump absolute

SP

SP + 1, A

[SP]

←

SP − 1

←

[SP]

A, SP

←

PU

PC

[VU], PL

[VL]

←

JMPL

JMP

JP

Addr.

Disp.

ii (ii = 15 bits, 0 to 32k)

←

PC9…0

i (i = 12 bits)

←

PC

Jump relative short

PC + r (r is −31 to +32, except 1)

31

www.national.com

Instruction Set (Continued)

←

ii

JSRL

JSR

Addr.

Addr

Jump SubRoutine Long

Jump SubRoutine

Jump InDirect

[SP]

PL, [SP−1]

PU,SP−2, PC

←

PU,SP−2, PC9…0

i

←

ROM (PU,A)

JID

PL

←

[SP−1]

RET

RETurn from subroutine

RETurn and SKip

RETurn from Interrupt

Generate an Interrupt

No OPeration

SP + 2, PL [SP], PU

← ←

SP + 2, PL [SP],PU [SP−1]

RETSK

RETI

INTR

NOP

←

SP + 2, PL [SP],PU [SP−1],GIE 1

←

PU, SP−2, PC 0FF

[SP]

PL, [SP−1]

←

PC

PC + 1

www.national.com

32

Instruction Execution Time

Most instructions are single byte (with immediate addressing

Instructions Using A & C

mode instructions taking two bytes).

CLRA

INCA

DECA

LAID

1/1

1/3

1/1

1/3

2/2

Most single byte instructions take one cycle time to execute.

Skipped instructions require x number of cycles to be

skipped, where x equals the number of bytes in the skipped

instruction opcode.

See the BYTES and CYCLES per INSTRUCTION table for

details.

DCOR

RRCA

RLCA

SWAPA

SC

Bytes and Cycles per Instruction

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

RC

Arithmetic and Logic Instructions

IFC

[B]

1/1

Direct

3/4

Immed.

2/2

IFNC

ADD

ADC

SUBC

AND

OR

PUSHA

POPA

ANDSZ

3/4

2/2

3/4

2/2

3/4

2/2

3/4

2/2

Transfer of Control Instructions

XOR

IFEQ

IFNE

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

3/4

2/2

JMPL

JMP

JP

3/4

2/3

1/3

3/5

2/5

1/3

1/5

1/7

1/1

3/4

2/2

3/4

2/2

3/4

2/2

JSRL

JSR

1/3

3/4

JID

1/1

VIS

RET

RETSK

RETI

INTR

NOP

RPND

1/1

Memory Transfer Instructions

Register

Indirect

Direct Immed.

Register Indirect

Auto Incr. & Decr.

[B]

[X]

1/3

[B+, B−]

1/2

[X+, X−]

1/3

X A, (Note 12)

LD A, (Note 12)

LD B, Imm

1/1

2/3

2/2

1/1

2/2

1/2

1/3

<

(IF B 16)

>

(IF B 15)

LD B, Imm

LD Mem, Imm

LD Reg, Imm

IFEQ MD, Imm

2/2

3/3

2/3

3/3

2/2

Note 12: Memory location addressed by B or X or directly.

33

www.national.com

Instruction Execution Time (Continued)

N i b b l e L o w e r

www.national.com

34

cludes BCLIDE (Byte Craft Limited Integrated Develop-

ment Environment) for Win32, editor, optimizing C Cross-

Compiler, macro cross assembler, BC-Linker, and

MetaLink tools support. (DOS/SUN versions available;

Compiler is installable under WCOP8 IDE; Compatible

with DriveWay COP8).

Development Tools Support

OVERVIEW

National is engaged with an international community of inde-

pendent 3rd party vendors who provide hardware and soft-

ware development tool support. Through National’s interac-

tion and guidance, these tools cooperate to form a choice of

solutions that fits each developer’s needs.

•

EWCOP8-KS: Very Low cost ANSI C-Compiler and Em-

bedded Workbench from IAR (Kickstart version:

COP8Sx/Fx only with 2k code limit; No FP). A fully inte-

grated Win32 IDE, ANSI C-Compiler, macro assembler,

editor, linker, Liberian, C-Spy simulator/debugger, PLUS

MetaLink EPU/DM emulator support.

This section provides a summary of the tool and develop-

ment kits currently available. Up-to-date information, selec-

tion guides, free tools, demos, updates, and purchase infor-

mation can be obtained at our web site at:

www.national.com/cop8.

EWCOP8-AS: Moderately priced COP8 Assembler and

Embedded Workbench from IAR (no code limit). A fully in-

tegrated Win32 IDE, macro assembler, editor, linker, li-

brarian, and C-Spy high-level simulator/debugger with

I/O and interrupts support. (Upgradeable with optional

C-Compiler and/or MetaLink Debugger/Emulator sup-

port).

SUMMARY OF TOOLS

COP8 Evaluation Tools

•

COP8–NSEVAL: Free Software Evaluation package for

Windows. A fully integrated evaluation environment for

COP8, including versions of WCOP8 IDE (Integrated De-

velopment Environment), COP8-NSASM, COP8-MLSIM,

•

EWCOP8-BL: Moderately priced ANSI C-Compiler and

Embedded Workbench from IAR (Baseline version: All

COP8 devices; 4k code limit; no FP). A fully integrated

Win32 IDE, ANSI C-Compiler, macro assembler, editor,

linker, librarian, and C-Spy high-level simulator/debugger.

(Upgradeable; CWCOP8-M MetaLink tools interface sup-

port optional).

™

COP8C, DriveWay COP8, Manuals, and other COP8

information.

•

COP8–MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

COP8–EPU: Very Low cost COP8 Evaluation & Pro-

gramming Unit. Windows based evaluation and

hardware-simulation tool, with COP8 device programmer

and erasable samples. Includes COP8-NSDEV, Drive-

way COP8 Demo, MetaLink Debugger, I/O cables and

power supply.

•

EWCOP8: Full featured ANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, and C-Spy high-level

simulator/debugger. (CWCOP8-M MetaLink tools inter-

face support optional).

•

COP8–EVAL-ICUxx: Very Low cost evaluation and de-

sign test board for COP8ACC and COP8SGx Families,

from ICU. Real-time environment with add-on A/D, D/A,

and EEPROM. Includes software routines and reference

designs.

EWCOP8-M: Full featured ANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, C-Spy high-level

simulator/debugger, PLUS MetaLink debugger/hardware

interface (CWCOP8-M).

Manuals, Applications Notes, Literature: Available free

from our web site at: www.national.com/cop8.

COP8 Productivity Enhancement Tools

COP8 Integrated Software/Hardware Design Develop-

ment Kits

•

WCOP8 IDE: Very Low cost IDE (Integrated Develop-

ment Environment) from KKD. Supports COP8C, COP8-

NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink

debugger under a common Windows Project Manage-

ment environment. Code development, debug, and emu-

lation tools can be launched from the project window

framework.

•

COP8-EPU: Very Low cost Evaluation & Programming

Unit. Windows based development and hardware-

simulation tool for COPSx/xG families, with COP8 device

programmer and samples. Includes COP8-NSDEV,

Driveway COP8 Demo, MetaLink Debugger, cables and

power supply.

•

DriveWay-COP8: Low cost COP8 Peripherals Code

Generation tool from Aisys Corporation. Automatically

generates tested and documented C or Assembly source

code modules containing I/O drivers and interrupt han-

dlers for each on-chip peripheral. Application specific

code can be inserted for customization using the inte-

grated editor. (Compatible with COP8-NSASM, COP8C,

and WCOP8 IDE.)

•

COP8-DM: Moderate cost Debug Module from MetaLink.

A Windows based, real-time in-circuit emulation tool with

COP8 device programmer. Includes COP8-NSDEV,

DriveWay COP8 Demo, MetaLink Debugger, power sup-

ply, emulation cables and adapters.

COP8 Development Languages and Environments

•

COP8-NSASM: Free COP8 Assembler v5 for Win32.

Macro assembler, linker, and librarian for COP8 software

development. Supports all COP8 devices. (DOS/Win16

v4.10.2 available with limited support). (Compatible with

WCOP8 IDE, COP8C, and DriveWay COP8).

•

COP8-UTILS: Free set of COP8 assembly code ex-

amples, device drivers, and utilities to speed up code de-

velopment.

COP8-MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

•

COP8-NSDEV: Very low cost Software Development

Package for Windows. An integrated development envi-

ronment for COP8, including WCOP8 IDE, COP8-

NSASM, COP8-MLSIM.

COP8C: Moderately priced C Cross-Compiler and Code

Development System from Byte Craft (no code limit). In-

35

www.national.com

COP8 Device Programmer Support

Development Tools Support

•

MetaLink’s EPU and Debug Module include development

device programming capability for COP8 devices.

(Continued)

COP8 Real-Time Emulation Tools

•

Third-party programmers and automatic handling equip-

ment cover needs from engineering prototype and pilot

production, to full production environments.

•

COP8-DM: MetaLink Debug Module. A moderately

priced real-time in-circuit emulation tool, with COP8 de-

vice programmer. Includes COP8-NSDEV, DriveWay

COP8 Demo, MetaLink Debugger, power supply, emula-

tion cables and adapters.

•

Factory programming available for high-volume require-

ments.

•

IM-COP8: MetaLink iceMASTER^®. A full featured, real-

time in-circuit emulator for COP8 devices. Includes Met-

aLink Windows Debugger, and power supply. Package-

specific probes and surface mount adaptors are ordered

separately.

TOOLS ORDERING NUMBERS FOR THE COP87L88CF FAMILY DEVICES

Vendor

Tools

Order Number

COP8-NSEVAL

Cost

Notes

National COP8-NSEVAL

COP8-NSASM

COP8-MLSIM

COP8-NSDEV

COP8-EPU

Free Web site download

COP8-NSASM

Free Included in EPU and DM. Web site download

COP8-MLSIM

COP8-NSDEV

VL

Included in EPU and DM. Order CD from website

Not available for this device

Contact MetaLink

COP8-DM

Development

Devices

COP87L84CF

COP87L88CF

VL

16k OTP devices. No windowed devices

IM-COP8

MetaLink COP8-EPU

COP8-DM

Contact MetaLink

Not available for this device

DM4-COP8-888CF (10

MHz), plus PS-10, plus

DM-COP8/xxx (ie. 28D)

M

Included p/s (PS-10), target cable of choice (DIP or

PLCC; i.e. DM-COP8/28D), 16/20/28/40 DIP/SO and

44 PLCC programming sockets. Add target adapter (if

needed)

DM Target

Adapters

MHW-CONV39

L

DM target converters for 28SO

IM-COP8

IM-COP8-AD-464 (-220)

(10 MHz maximum)

H

Base unit 10 MHz; -220 = 220V; add probe card

(required) and target adapter (if needed); included

software and manuals

IM Probe Card

PC-884CF28DW-AD-10

PC-888CF40DW-AD-10

PC-888CF44PW-AD-10

MHW-SOIC28

M

L

10 MHz 28 DIP probe card; 2.5V to 6.0V

10 MHz 40 DIP probe card; 2.5V to 6.0V

10 MHz 44 PLCC probe card; 2.5V to 6.0V

28 pin SOIC adapter for probe card

IM Probe Target

Adapter

ICU

KKD

IAR

COP8-EVAL

WCOP8-IDE

EWCOP8-xx

COP8C

Not available for this device

WCOP8-IDE

VL

Included in EPU and DM

See summary above

COP8C

L - H Included all software and manuals

Byte

Craft

M

Included all software and manuals

Aisys

DriveWay COP8

Contact vendors

L

Included all software and manuals

OTP Programmers

L - H For approved programmer listings and vendor

information, go to our OTP support page at:

www.national.com/cop8

<

Cost: Free; VL = $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k

www.national.com

36

Development Tools Support (Continued)

WHERE TO GET TOOLS

Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.

Vendor

Home Office

U.S.A.: Santa Clara, CA

1-408-327-8820

Electronic Sites

Other Main Offices

Distributors

Aisys

www.aisysinc.com

@

info aisysinc.com

fax: 1-408-327-8830

U.S.A.

Byte Craft

IAR

www.bytecraft.com

Distributors

@

1-519-888-6911

info bytecraft.com

fax: 1-519-746-6751

Sweden: Uppsala

+46 18 16 78 00

fax: +46 18 16 78 38

www.iar.se

U.S.A.: San Francisco

1-415-765-5500

@

info iar.se

@

info iar.com

fax: 1-415-765-5503

U.K.: London

@

info iarsys.co.uk

@

info iar.de

+44 171 924 33 34

fax: +44 171 924 53 41

Germany: Munich

+49 89 470 6022

fax: +49 89 470 956

Switzeland: Hoehe

+41 34 497 28 20

fax: +41 34 497 28 21

ICU

Sweden: Polygonvaegen

+46 8 630 11 20

www.icu.se

@

support icu.se

@

fax: +46 8 630 11 70

Denmark:

support icu.ch

KKD

www.kkd.dk

MetaLink

U.S.A.: Chandler, AZ

1-800-638-2423

www.metaice.com

Germany: Kirchseeon

80-91-5696-0

@

sales metaice.com

@

fax: 1-602-926-1198

support metaice.com

fax: 80-91-2386

@

bbs: 1-602-962-0013

www.metalink.de

islanger metalink.de

Distributors Worldwide

National

U.S.A.: Santa Clara, CA

1-800-272-9959

www.national.com/cop8

Europe: +49 (0) 180 530 8585

fax: +49 (0) 180 530 8586

Distributors Worldwide

@

support nsc.com

@

fax: 1-800-737-7018

europe.support nsc.com

The following companies have approved COP8 program-

mers in a variety of configurations. Contact your local office

or distributor. You can link to their web sites and get the lat-

est listing of approved programmers from National’s COP8

OTP Support page at: www.national.com/cop8.

Customer Support

Complete product information and technical support is avail-

able from National’s customer response centers, and from

our on-line COP8 customer support sites.

Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys-

tems; ICE Technology; Lloyd Research; Logical Devices;

MQP; Needhams; Phyton; SMS; Stag Programmers; Sys-

tem General; Tribal Microsystems; Xeltek.

37

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

Molded SO Wide Body Package (M)

Order Number COP87L84CFM-XE

NS Package Number M28B

Molded Dual-In-Line Package (N)

Order Number COP87L84CFN-XE

NS Package Number N28B

www.national.com

38

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number COP87L88CFN-XE

NS Package Number N40A

Plastic Leaded Chip Carrier (V)

Order Number COP87L88CFV-XE

NS Package Number V44A

39

www.national.com

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	COP87L88CFN-XE
厂家：	ETC
描述：	IC-8-BIT MCU IC- 8-BIT MCU\n
文件：	总40页 (文件大小：549K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

COP87L88CFN-XE [ETC]

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