ADC12451CMJ [NSC]
Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold; 动态测试的自校准12位加符号位A / D转换器采样和保持
| 型号： | ADC12451CMJ |
| 厂家： | 
National Semiconductor |
| 描述： | Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| 文件： | 总18页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1994
ADC12451 Dynamically-Tested Self-Calibrating
12-Bit Plus Sign A/D Converter with Sample-and-Hold
Y
Telecommunications
General Description
The ADC12451 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter whose dynamic
specifications (S/N, THD, etc.) are tested and guaranteed.
On request, the ADC12451 goes through a self-calibration
cycle that adjusts linearity, zero and full-scale errors. The
ADC12451 also has the ability to go through an Auto-Zero
cycle that corrects the zero error during every conversion.
Y
High Resolution Process Control
Y
Instrumentation
Features
Y
Self-calibration provides excellent temperature stability
Y
Y
Y
Internal sample-and-hold
8-bit mP/DSP interface
a
Bipolar input range with a single 5V reference
The analog input to the ADC12451 is tracked and held by
the internal circuitry, so an external sample-and-hold is not
required. The ADC12451 has a S/H control input which di-
rectly controls the track-and-hold state of the A/D. A unipo-
Key Specifications
Y
Resolution
12 bits plus sign
7.7 ms (max)
83 kHz (max)
73.5 dB (min)
a
lar analog input voltage range (0V to
a
5V) or a bipolar
g
Y
Conversion Time
b
range ( 5V to 5V) can be accommodated with 5V sup-
plies.
Y
Sampling Rate
Y
Bipolar Signal/Noise
The 13-bit data result is available on the eight outputs of the
ADC12451 in two bytes, high-byte first and sign extended.
The digital inputs and outputs are compatible with TTL or
CMOS logic levels.
Y
b
Total Harmonic Distortion
78.0 dB (max)
100 ns
Y
Aperture Time
Y
Aperture Jitter
100 ps
rms
Y
g
Zero Error
2 LSB (max)
Y
g
Positive Full-Scale Error
@
g
1.5 LSB (max)
Applications
Y
Y
Power Consumption
5V
113 mW (max)
Digital Signal Processing
Y
Audio
Simplified Block Diagram
Connection Diagram
Dual-In-Line Package
TL/H/11025–2
Top View
Ordering Information
Industrial
Package
s
s
b
(
40 C
T
85 C)
§
ADC12451CIJ
§
A
J24A
Military
s
Package
s
b
(
55 C
§
T
125 C)
§
A
TL/H/11025–1
ADC12451CMJ,
ADC12451CMJ/883
J24A
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/H/11025
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Ratings (Notes 1 & 2)
s
s
T
Temperature Range
ADC12451CIJ
ADC12451CMJ,
ADC12451CMJ/883
T
40 C
§
T
A
MIN
s
A
MAX
85 C
§
s
b
a
T
s
s
a
b
55 C
§
T
125 C
§
e
e
AV
A
Supply Voltage (V
CC
DV
)
CC
6.5V
6.5V
CC
Negative Supply Voltage (Vb
DV
and AV
Voltage
CC
b
CC
(Notes 6 & 7)
)
4.5V to 5.5V
b
a
Voltage at Logic Control Inputs
Voltage at Analog Inputs
0.3V to (V
0.3V)
CC
Negative Supply Voltage (Vb
)
b
b
4.5V to 5.5V
(V , V
IN REF
)
(Vb 0.3V) to (V
0.3V)
0.3V
Reference Voltage
, Notes 6 & 7)
REF
b
a
CC
a
50 mV
(V
3.5V to AV
CC
AV -DV (Note 7)
CC CC
g
Input Current at any Pin (Note 3)
Package Input Current (Note 3)
5 mA
g
20 mA
Power Dissipation at 25 C (Note 4)
§
Storage Temperature Range
ESD Susceptability (Note 5)
875 mW
b
a
65 C to 150 C
§
§
2000V
Soldering Information
J Package (10 Seconds)
300 C
§
Converter Electrical Characteristics
CC
b
e
e
e a
e b
3.5 MHz unless otherwise specified. Boldface limits apply for T
e a
5.0V, using S/H input for
The following specifications apply for V
DV
AV
5.0V, V
5.0V, V
REF
CC
CC
e
25 C. (Notes 6, 7 and 8)
e
e
T T
J
conversion control, and f
CLK
to T ; all
MAX
A
MIN
e
e
other limits T
T
J
§
A
Typical Limit
(Note 9) (Note 10, 19)
Units
(Limit)
Symbol
Parameter
Conditions
STATIC CHARACTERISTICS
Positive Integral Linearity Error
g
g
After Auto-Cal, (Notes 11 & 12)
After Auto-Cal, (Notes 11 & 12)
After Auto-Cal (Notes 11 & 12)
(/2
(/2
LSB
LSB
Negative Integral Linearity Error
Positive or Negative Differential Linearity
Zero Error (Notes 12 & 13)
12
Bits
e
e
g
g
g
AZ
‘‘0’’, f
CLK
1.75 MHz
1.75 MHz
1.75 MHz
1
1
1
LSB
g
g
2/ 3.0
After Auto-Cal Only
LSB(max)
LSB
e
e
e
Positive Full-Scale Error (Note 12)
Negative Full-Scale Error (Note 12)
Analog Input Voltage
AZ
‘‘0’’, f
CLK
g
g
1.5/ 2.5 LSB(max)
Auto-Cal Only
e
AZ
‘‘0’’, f
CLK
LSB
g
g
1.5/ 3.0 LSB(max)
Auto-Cal Only
Vb
0.05
0.05
V(min)
V(max)
b
V
IN
a
V
CC
e
e
e
5V 5%,
g
g
g
g
Power Supply Sensitivity Zero Error (Note 14) AV
V
DV
CC
4.75V, V
(/8
(/8
(/8
LSB
LSB
LSB
pF
CC
b
e b
g
5V 5%
REF
Full-Scale Error
Linearity Error
C
C
V
REF
Input Capacitance
80
REF
Analog Input Capacitance
65
pF
IN
DYNAMIC CHARACTERISTICS
Bipolar Effective Bits (Note 17)
e
e
g
f
f
f
f
f
f
f
1 kHz, V
IN
4.85V
12.6
12.6
11.8
11.8
78
Bits
Bits(min)
Bits
IN
e
e
e
e
e
e
e
g
20.67 kHz, V
IN
4.85V
11.9
11.1
IN
IN
IN
IN
IN
IN
e
4.85 V
Unipolar Effective Bits (Note 17)
1 kHz, V
IN
p-p
e
20.67 kHz, V
IN
4.85 V
p-p
Bits(min)
dB
e
g
4.85V
S/N
Bipolar Signal to Noise Ratio (Note 17)
1 kHz, V
IN
e
g
10 kHz, V
IN
4.85V
78
dB
e
g
20.67 kHz, V
IN
4.85V
78
73.5
dB(min)
2
Converter Electrical Characteristics (Continued)
b
e
e
e a
e b
e a
5.0V, using S/H input for
REF
The following specifications apply for V
DV
CC
AV
CC
5.0V, V
5.0V, V
CC
e
25 C. (Notes 6, 7 and 8)
e
e
T T
J
conversion control, and f
CLK
3.5 MHz unless otherwise specified. Boldface limits apply for T
to T ; all
MAX
A
MIN
e
e
other limits T
T
J
§
A
Typical
Limit
Units
(Note 9) (Note 10, 19) (Limit)
Symbol
Parameter
Conditions
DYNAMIC CHARACTERISTICS (Continued)
e
e
e
e
e
e
e
e
e
e
e
e
e
e
4.85 V
p-p
S/N
Unipolar Signal to Noise Ratio (Note 17)
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
1 kHz, V
IN
73
73
73
dB
dB
e
10 kHz, V
IN
4.85 V
p-p
e
20.67 kHz, V
IN
4.85 V
68.7
dB(min)
dB
p-p
e
b
g
THD
THD
Bipolar Total Harmonic Distortion (Note 17)
Unipolar Total Harmonic Distortion (Note 17)
1 kHz, V
IN
4.85V
82
80
82
80
88
84
80
90
86
82
e
b
b
b
b
b
b
b
b
b
b
g
20.67 kHz, V
IN
4.85V
78.0
73.1
dB(max)
dB
e
1 kHz, V
IN
4.85 V
p-p
e
b
20.67 kHz, V
IN
4.85 V
dB(max)
dB
p-p
e
g
4.85V
Bipolar Peak Harmonic or Spurious Noise
(Note 17)
1 kHz, V
IN
e
g
g
10 kHz, V
4.85V
4.85V
dB
IN
IN
e
20 kHz, V
dB
e
Unipolar Peak Harmonic or Spurious Noise
(Note 17)
1 kHz, V
IN
4.85 V
p-p
dB
e
10 kHz, V
20 kHz, V
4.85 V
4.85 V
dB
IN
IN
p-p
p-p
e
dB
e
e
e
19.375 kHz,
g
20 kHz
Bipolar Two Tone Intermodulation Distortion
(Note 17)
V
4.85V, f
IN1
dB(max)
IN
b
b
78
78
f
IN2
e
e
e
19.375 kHz,
Unipolar Two Tone Intermodulation Distortion
(Note 17)
V
IN
4.85 V , f
p-p IN1
20 kHz
dB(max)
f
IN2
b
e
e
g
3 dB Bipolar Full Power Bandwidth
V
4.85V, (Note 17)
25
20.67
20.67
kHz(min)
kHz(min)
ns
IN
IN
b
3 dB Unipolar Full Power Bandwidth
V
4.85 V , (Note 17)
p-p
32
Aperture Time
Aperture Jitter
100
100
ps
rms
3
Digital and DC Electrical Characteristics
5.0V, V
b
e
otherwise specified. Boldface limits apply for T
e a
e b
e a
; all other limits T
e
5.0V, and f
CLK
The following specifications apply for DV
CC
AV
5.0V, V
REF
3.5 MHz unless
e
T 25 C. (Notes 6 and 7)
J
CC
e
e
e
T
T
MIN
to T
§
A
J
MAX
A
Typical
(Note 9)
Limit
Units
Symbol
Parameter
Condition
(Note 10, 19)
(Limit)
e
e
V
V
Logical ‘‘1’’ Input Voltage for
All Inputs except CLK IN
V
V
5.25V
4.75V
IN(1)
IN(0)
IN(1)
CC
2.0
V(min)
V(max)
Logical ‘‘0’’ Input Voltage for
All Inputs except CLK IN
CC
0.8
1
e
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
V
V
5V
0.005
mA(max)
mA(max)
IN
e
b
b
1
0V
0.005
2.8
IN(0)
IN
a
V
V
V
V
CLK IN Positive-Going
Threshold Voltage
T
2.7
2.3
0.4
V(min)
V(max)
V(min)
b
CLK IN Negative-Going
Threshold Voltage
T
2.1
0.7
CLK IN Hysteresis
b
H
a
b
[
]
V
(min)
V
T
(max)
T
e
4.75V:
e b
e b
Logical ‘‘1’’ Output Voltage
V
OUT(1)
CC
OUT
OUT
I
I
360 mA
10 mA
2.4
4.5
V(min)
V(min)
e
e
V
I
Logical ‘‘0’’ Output Voltage
V
4.75V,
1.6 mA
OUT(0)
CC
0.4
V(max)
I
OUT
e
OUT
b
b
3
TRI-STATE Output Leakage
É
Current
V
0V
5V
0V
5V
0.01
mA(max)
mA(max)
mA(min)
mA(min)
mA(max)
mA(max)
mA(max)
OUT
e
e
e
V
0.01
3
OUT
OUT
OUT
b
b
I
I
Output Source Current
Output Sink Current
V
20
6.0
SOURCE
SINK
V
20
8.0
e
e
e
DI
DV Supply Current
CC
CS
CS
CS
‘‘1’’
‘‘1’’
‘‘1’’
1
2.5
10
10
CC
AI
AV Supply Current
CC
2.8
2.8
CC
Ib
Vb Supply Current
AC Electrical Characteristics
The following specifications apply for DV
CC
b
e
e a
e b
e
e
t 20 ns unless otherwise specified.
f
AV
CC
5.0V, V
5.0V, t
r
e
e
e
e
T
J
Boldface limits apply for T
T
T
MIN
to T
; all other limits T
MAX
25 C. (Notes 6 and 7)
§
A
J
A
Typical
(Note 9)
Limit
Units
Symbol
Parameter
Conditions
(Note 10, 19)
(Limit)
f
Clock Frequency
MHz
CLK
0.5
6.0
MHz(min)
MHz(max)
3.5
Clock Duty Cycle
50
%
40
60
%(min)
%(max)
a
)
CLK
t
t
Conversion Time using WR
to start a Conversion
27(1/f
)
)
27(1/f
250 ns
250 ns
(max)
ms(max)
ms(max)
(max)
C
CLK
e
e
e
‘‘1’’
f
f
3.5 MHz, AZ
7.7
7.95
CLK
e
1.75 MHz, AZ
‘‘0’’
15.4
15.65
CLK
e
a
)
Conversion Time using S/H
to start a Conversion
AZ
‘‘1’’
34(1/f
CLK
34(1/f
C
CLK
e
e
‘‘1’’
f
3.5 MHz, AZ
9.7
9.95
ms(max)
CLK
4
AC Electrical Characteristics (Continued)
b
e
e a
; all other limits T
e b
e
§
e
t
f
The following specifications apply for DV
e
AV
5.0V, V
5.0V, t
20 ns unless otherwise specified.
e
T 25 C. (Notes 6 and 7)
J
CC
CC
r
e
e
Boldface limits apply for T
T
J
T
to T
A
MIN
MAX
A
Typical
(Note 9)
Limit
Units
Symbol
Parameter
Acquisition Time
Conditions
(Note 10, 19)
(Limit)
e
50X
t
A
R
SOURCE
3.5
3.5
ms(min)
(Note 15)
t
t
Internal Acquisition Time
IA
ZA
7(1/f
)
7(1/f
(max)
CLK
CLK)
(when using WR Control Only)
a
a
250 ns
Auto Zero Time
33(1/f
)
33(1/f
)
(max)
ms(max)
ns(max)
ns(max)
(max)
CLK
CLK
Acquisition Time
e
f
1.75 MHz
18.8
19.05
350
CLK
t
t
Delay from Hold Command
to Falling Edge of EOC
Using WR Control
Using S/H Control
200
100
D(EOC)L
CAL
150
Calibration Time
1399 (1/f
399
)
1399 (1/f
)
CLK
CLK
e
f
3.5 MHz
400
ms(max)
ns(min)
ns(min)
CLK
t
t
t
Calibration Pulse Width
(Note 16)
60
200
W(CAL)L
W(WR)L
ACC
minimum WR Pulse Width
60
200
e
maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)
C
100 pF
L
50
30
95
70
ns(max)
ns(max)
e
e
t , t
0H 1H
TRI-STATE Control (Delay
from Rising Edge of RD
to Hi-Z State)
R
1 kX,
L
C
100 pF
L
t
t
maximum Delay from Falling Edge
of RD or WR to Reset of INT
PD(INT)
100
30
175
60
ns(max)
ns(min)
Delay between Successive RD Pulses
RR
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
b
k
l
(AV or DV ), the current at that pin should be limited to
CC CC
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
V
or V
IN
IN
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.
a
Note 4: The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation
output). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex. when any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T (maximum junction
1 TTL Load on each digital
JMax
temperature), i (package junction to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature
JA
A
e
b
e
150 C, and the typical thermal
JMax
is P
DMax
(T
T
A
)/i or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
§
JMax
JA
resistance (i ) of the ADC12451 with CMJ, and CIJ suffixes when board mounted is 51 C/W.
§
JA
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than
are minimum (4.75 V ) and Vb is maximum ( 4.75 V ), the analog input full-scale voltage must be
s
b
g
50 mV. This means that if AV and DV
CC CC
4.8 V
DC
.
D
C
D
C
TL/H/11025–4
5
Electrical Characteristics (Continued)
Note 7: A diode exists between AV
and DV
as shown below.
CC
CC
TL/H/11025–5
be connected together to a power supply with separate bypass filters at each V pin.
CC
To guarantee accuracy, it is required that the AV
and DV
CC
3.5 MHz. At higher or lower clock frequencies accuracy may degrade, see the typical performance characteristic curves.
25 C and represent most likely parametric norm.
CC
e
Note 8: Accuracy is guaranteed at f
CLK
e
Note 9: Typicals are at T
§
J
Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See Figures 1b and 1c).
Note 12: The ADC12451’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
g
result in a repeatability uncertainty of 0.20 LSB.
Note 13: If T changes then an Auto-Zero or Auto-Cal cycle will have to be re-started, see the typical performance characteristic curves.
A
Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15: When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
end of the interval of t , therefore making t end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR. If the falling edge of the
A
A
clock is synchronous to the rising edge of WR then t will end exactly 6.5 clock periods after the rising edge of WR. This does not occur when S/H control is used.
A
Note 16: The CAL line must be high before a conversion is started.
Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18: The ADC12451 reference ladder is composed solely of capacitors.
Note 19: A military RETS electrical test specification is available on request. At time of printing, the ADC12451CMJ/883 RETS specification complies fully with the
boldface limits in this column.
TL/H/11025–6
FIGURE 1a. Transfer Characteristic
6
Electrical Characteristics (Continued)
TL/H/11025–7
FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles
TL/H/11025–8
FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Cal Cycle
Typical Performance Characteristics
Zero Error Change vs
Ambient Temperature
Zero Error vs V
Linearity Error vs V
REF
REF
TL/H/11025–9
7
Typical Performance Characteristics (Continued)
Bipolar Signal-to-
a
Noise Distortion Ratio vs
Input Source Impedance
Linearity Error vs
Clock Frequency
Full Scale Error Change vs
Ambient Temperature
s
e
ut
se
t
TL/H/11025–10
8
Typical Performance Characteristics (Continued)
Unipolar Spectral Response
with 10 kHz Sine Wave Input
Unipolar Spectral Response
with 20 kHz Sine Wave Input
Unipolar Spectral Response
with 40 kHz Sine Wave Input
TL/H/11025–11
Test Circuits
TL/H/11025–13
TL/H/11025–12
TL/H/11025–15
TL/H/11025–14
FIGURE 2. TRI-STATE Test Circuits and Waveforms
9
Timing Diagrams
Auto-Cal Cycle
TL/H/11025–16
e
e
0)
Using WR Control to Start a Conversion with Auto-Zero (CAL
1, AZ
TL/H/11025–17
10
Timing Diagrams (Continued)
e
Using WR Control to Start a Conversion without Auto-Zero (CAL 1, AZ
1)
TL/H/11025–18
e
e
1)
Using S/H Control to Start a Conversion without Auto-Zero (AZ
1, CAL
TL/H/11025–19
11
1.0 Pin Descriptions
DV
CC
AV
CC
(24),
(4)
EOC (22)
INT (21)
The End-of-Conversion control output. This
output is low during a conversion or a calibra-
tion cycle.
The digital and analog positive power supply
pins. The digital and analog power supply
a
voltage range of the ADC12451 is 4.5V to
a
5.5V. To guarantee accuracy, it is required
that the AV and DV be connected to-
gether to the same power supply with sepa-
The Interrupt control output. This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches. Reading the re-
sult or starting a conversion or calibration cy-
cle will reset this output high.
CC CC
rate bypass capacitors (10 mF tantalum in
parallel with a 0.1 mF ceramic) at each V
pin.
CC
V
b (5)
The analog negative supply voltage pin. Vb
DB0/DB8 - The TRI-STATE output pins. Twelve bit plus
sign output data access is accomplished using
b
b
has a range of 4.5V to 5.5V and needs
bypass capacitors of 10 mF tantalum in paral-
lel with a 0.1 mF ceramic.
DB7/DB12
two successive RDs of one byte each, high
(13–20)
byte first (DB8–DB12). The data format used
is two’s complement sign bit extended with
DB12 the sign bit, DB11 the MSB and DB0 the
LSB.
DGND (12), The digital and analog ground pins. AGND
and DGND must be connected together ex-
ternally to guarantee accuracy.
AGND (3)
V
V
(2)
The reference input voltage pin. To maintain
accuracy the voltage at this pin should not
REF
2.0 Functional Description
The ADC12451 is a 12-bit plus sign A/D converter with the
capability of doing Auto-Zero or Auto-Calibration routines to
minimize zero, full-scale and linearity errors. It is a succes-
exceed the AV
CC
50 mV or go below 3.5 V
or DV
a
by more than
.
CC
DC
(1)
The analog input voltage pin. To guarantee
accuracy the voltage at this pin should not
IN
sive-approximation A/D converter consisting of
a DAC,
comparator and a successive-approximation register (SAR).
Auto-Zero is an internal calibration sequence that corrects
for the A/D’s zero error caused by the comparator’s offset
voltage. Auto-Cal is a calibration cycle that not only corrects
zero error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies. Auto-Cal minimizes the errors
of the ADC12451 without the need of trimming during its
fabrication. An Auto-Cal cycle can restore the accuracy of
the ADC12451 at any time, which ensures accuracy over
temperature and time.
exceed V by more than 50 mV or go below
CC
Vb by more than 50 mV.
CS (10)
RD (23)
WR (7)
The Chip Select control input. This input is
active low and enables the WR, RD and S/H
functions.
The Read control input. With both CS and RD
low the TRI-STATE output buffers are en-
abled and the INT output is reset high.
The Write control input. The conversion is
started on the rising edge of the WR pulse
when CS is low. When this control line is
used the end of the analog input voltage ac-
quisition window is internally controlled by the
ADC12451.
2.1 DIGITAL INTERFACE
On power up, a calibration sequence should be initiated by
pulsing CAL low with CS and S/H high. To acknowledge the
CAL signal, EOC goes low after the falling edge of CAL, and
remains low during the calibration cycle of 1399 clock peri-
ods. During the calibration sequence, first the comparator’s
offset is determined, then the capacitive DAC’s mismatch
error is found. Correction factors for these errors are then
stored in internal RAM.
S/H (11)
The sample and hold control input. This con-
trol input can also be used to start a conver-
sion. With CS low the falling edge of S/H
starts the analog input acquisition window.
The rising edge of S/H ends the acquisition
window and starts a conversion.
A conversion is initiated by taking CS and WR low. If AZ is
low an Auto-Zero cycle, which takes approximately 26 clock
periods, is inserted before the analog input is sampled and
the actual conversion is started. AZ must remain low during
the complete conversion sequence. After Auto-Zero the ac-
quisition opens and the analog input is sampled for appprox-
imately 7 clock periods. If AZ is high, the Auto-Zero cycle is
not inserted after the rising edge of WR. In this case the
acquisition window opens when the ADC12451 completes a
conversion, signaled by the rising edge of EOC. At the end
of the acquisition window EOC goes low, signaling that the
analog input is no longer being sampled and that the A/D
successive approximation conversion has started.
CLKIN (8)
CAL (9)
The external clock input pin. The typical clock
frequency range is 500 kHz to 6.0 MHz.
The Auto-Calibration control input. When
CAL is low the ADC12451 is reset and a cali-
bration cycle is initiated. During the calibra-
tion cycle the values of the comparator offset
voltage and the mismatch errors in the ca-
pacitor reference ladder are determined and
stored in RAM. These values are used to cor-
rect the errors during a normal cycle of A/D
conversion.
AZ (6)
The Auto-Zero control input. With the AZ pin
held low during a conversion, the ADC12451
goes into an auto-zero cycle before the actu-
al A/D conversion is started. This Auto-Zero
cycle corrects for the comparator offset volt-
age. The total conversion time (t ) is in-
C
creased by 26 clock periods when Auto-Zero
is used.
12
2.0 Functional Description (Continued)
A conversion sequence can also be controlled by the S/H
and CS inputs. Taking CS and S/H low starts the acquisition
window for the analog input voltage. The rising edge of S/H
immediately puts the A/D in the hold mode and starts the
conversion. Using S/H will simplify synchronizing the end of
the acquisition window to other signals, which may be nec-
essary in a DSP environment.
the operation of the ADC12451. Care should be taken not to
inadvertently be in this mode, since DB2, DB3, DB5, and
DB6 become active outputs, which may cause data bus
contention.
2.2 RESETTING THE A/D
The ADC12451 is reset whenever a new conversion is start-
ed by taking CS and WR or S/H low. If this is done when the
analog input is being sampled or when EOC is low, the
Auto-Cal correction factors may be corrupted, therefore re-
quiring an Auto-Cal cycle before the next conversion. When
During a conversion, the sampled input voltage is succes-
sively compared to the output of the DAC. First, the ac-
quired input voltage is compared to analog ground to deter-
mine its polarity. The sign bit is set low for positive input
voltages and high for negative. Next the MSB of the DAC is
set high with the rest of the bits low. If the input voltage is
greater than the output of the DAC, then the MSB is left
high; otherwise it is set low. The next bit is set high, making
the output of the DAC three quarters or one quarter of full
scale. A comparison is done and if the input is greater than
the new DAC value this bit remains high; if the input is less
than the new DAC value the bit is set low. This process
continues until each bit has been tested. The result is then
stored in the output latch of the ADC12451. Next INT goes
low, and EOC goes high to signal the end of the conversion.
e
using WR or S/H without Auto-Zero (AZ
1) to start a
conversion, a new conversion can be restarted only after
EOC has gone high signaling the end of the current conver-
e
version can be restarted during the first 26 clock periods
sion. When using WR with Auto-Zero (AZ
0) a new con-
after the rising edge of WR (t ) or after EOC has returned
Z
high without corrupting the Auto-Cal correction factors.
The Calibration Cycle cannot be reset once started. On
power-up the ADC12451 automatically goes through a Cali-
bration Cycle that takes typically 1399 clock cycles. For rea-
sons that will be discussed in Section 3.8, a new calibration
cycle needs to be started after the completion of the auto-
matic one.
The result can now be read by taking CS and RD low to
enable the DB0/DB8–DB7/DB12 output buffers. The high
byte of data is relayed first on the data bus outputs as
shown below:
3.0 Analog Considerations
3.1 REFERENCE VOLTAGE
DB0/ DB1/ DB2/ DB3/ DB4/
DB8 DB9 DB10 DB11 DB12
DB5/
DB12
DB6/
DB12
DB7/
DB12
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
Bit 8 Bit 9 Bit 10 MSB Sign Bit Sign Bit Sign Bit Sign Bit
between V and AGND), over which 4095 positive output
IN
codes and 4096 negative output codes exist. The A-to-D
can be used in either ratiometric or absolute reference ap-
Taking CS and RD low a second time will relay the low byte
of data on the data bus outputs as shown below:
DB0/ DB1/ DB2/ DB3/ DB4/ DB5/ DB6/ DB7/
plications. The voltage source driving V
must have a
REF
DB8
DB9
DB10 DB11 DB12 DB12 DB12 DB12
Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
very low output impedance and very low noise. The circuit in
Figure 4a is an example of a very stable reference that is
appropriate for use with the ADC12451. The simple refer-
ence circuit of Figure 4b may be used when the application
does not require a low full-scale error.
LSB
Bit 1
The table in Figure 3 summarizes the effect of the digital
control inputs on the function of the ADC12451. The Test
Mode, where RD and S/H are high and CS and CAL are
low, is used during manufacture to thoroughly check out
Digital Control Inputs
A/D Function
CS
WR
S/H
RD
CAL
AZ
ß
ß
ß
ß
ß
1
ß
1
1
ß
1
1
1
1
1
1
1
1
0
0
X
X
Start Conversion without Auto-Zero
Start Conversion synchronous with rising edge of S/H without Auto-Zero
Read Conversion Result without Auto-Zero
Start Conversion with Auto-Zero
1
ß
1
1
ß
1
1
1
1
ß
X
1
Read Conversion Result with Auto-Zero
X
1
ß
0
Start Calibration Cycle
0
X
X
1
Test Mode (DB2, DB3, DB5, and DB6 become active)
FIGURE 3. Function of the A/D Control Inputs
13
3.0 Analog Considerations (Continued)
TL/H/11025–21
Errors without any trims:
b
a
40 C to 85 C
25 C
§
0.075%
0.024%
§
§
g
g
g
0.2%
Full Scale
Zero
g
0.024%
TL/H/11025–20
g
g
(/2 LSB
FIGURE 4b. Simple Reference Circuit
Linearity
(/2 LSB
FIGURE 4a. Low Drift Extremely Stable Reference Circuit
In a ratiometric system, the analog input voltage is propor-
tional to the voltage used for the A/D reference. When this
this method the acquisition window is internally controlled
by the ADC12451 and lasts for approximately 7 clock peri-
ods. Since the acquisition window needs to be at least
3.5 ms at all times, when using Auto-Zero the maximum
clock frequency is limited to 2 MHz. The zero error with the
Auto-Zero cycle is production tested at a clock frequency of
1.75 MHz. This accommodates easy switching between a
voltage is the system power supply, the V
REF
pin can be
tied to V . This technique relaxes the stability requirement
CC
of the system reference as the analog input and A/D refer-
ence move together maintaining the same output code for a
given input condition.
e
conversion with the Auto-Zero cycle (f
e
1.75 MHz) and
3.5 MHz) as shown in Figure 5.
CLK
For absolute accuracy, where the analog input varies be-
tween very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will re-
quire an initial adjustment to null out full-scale errors.
without (f
CLK
3.2 ACQUISITION WINDOW
As shown in the timing diagrams there are three different
methods of starting a conversion, each of which affects the
acquisition window and timing.
With Auto-Zero high a conversion can be started with the
WR or S/H controls. In either method of starting a conver-
sion the rising edge of EOC signals the actual beginning of
the acquisition window. At this time a voltage spike may be
noticed on the analog input of the ADC12451 whose ampli-
tude is dependent on the input voltage and the source re-
sistance. The timing diagrams for these two methods of
starting a conversion do not show the acquisition window
TL/H/11025–22
FIGURE 5. Switching between a Conversion with and
without Auto-Zero when Using WR Control
3.3 INPUT CURRENT
Because the input network of the ADC12451 is made up of
a switch and a network of capacitors a charging current will
flow into or out of (depending on the input voltage polarity)
starting at this time because the acquisition time (t ) must
A
of the analog input pin (V ) on the start of the analog input
IN
start after the conversion result high and low bytes have
been read. This is necessary since activating and deactivat-
ing the digital outputs (DB0/DB7–DB8/DB12) causes cur-
sampling period. The peak value of this current will depend
on the actual input voltage applied and the source resist-
ance.
rent fluctuations in the ADC12451’s internal DV
lines.
CC
This generates digital noise which couples into the capaci-
tive ladder that stores the analog input voltage. Therefore,
the time interval between the rising edge of EOC and the
second read is inappropriate for analog input voltage acqui-
sition.
3.4 NOISE
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to this input can cause er-
rors. Input filtering can be used to reduce the effects of
these noise sources.
When WR is used to start a conversion with AZ low the
Auto-Zero cycle is inserted before the acquisition window. In
14
3.0 Analog Considerations (Continued)
3.5 INPUT BYPASS CAPACITORS
change. Since Auto-Zero cannot be activated with S/H con-
version method it may be necessary to do a calibration cy-
cle more than once.
An external capacitor can be used to filter out any noise due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result.
3.9 THE AUTO-ZERO CYCLE
3.6 INPUT SOURCE RESISTANCE
To correct for any change in the zero (offset) error of the
A/D, the auto-zero cycle can be used. It may be necessary
to do an auto-zero cycle whenever the ambient temperature
changes significantly. (See the curve titled ‘‘Zero Error
Change vs Ambient Temperature’’ in the Typical Perform-
ance Characteristics.) A change in the ambient temperature
The analog input can be modeled as shown in Figure 6.
External R will lengthen the time period necessary for the
S
voltage on C
REF
input voltage. With t
to settle to within (/2 LSB of the analog
s
e
3.5 ms, R
1 kX will allow a 5V
A
S
analog input voltage to settle properly.
will cause the V
of the sampled data comparator to
change, which may cause the zero error of the A/D to be
OS
3.7 POWER SUPPLIES
Noise spikes on the V
and Vb supply lines can cause
g
greater than 1 LSB. An auto-zero cycle will typically main-
tain the zero error to 1 LSB or less.
CC
g
conversion errors as the comparator will respond to this
noise. The A/D is especially sensitive during the Auto-Zero
or -Cal procedures to any power supply spikes. Low induc-
tance tantalum capacitors of 10 mF or greater paralleled
with 0.1 mF ceramic capacitors are recommended for supply
bypassing. Separate bypass capacitors should be placed
4.0 Dynamic Performance
Many applications require the A/D converter to digitize ac
signals, but the standard dc integral and differential nonlin-
earity specifications will not accurately predict the A/D con-
verter’s performance with ac input signals. The important
specifications for ac applications reflect the converter’s abil-
ity to digitize ac signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise (S/N), signal-to-
close to the DV , AV
CC
voltage source is available in the system,
and Vb pins. If an unregulated
CC
a
separate
(and
LM340LAZ-5.0 voltage regulator for the A-to-D’s V
other analog circuitry) will greatly reduce digital noise on the
supply line.
CC
a
a
noise distortion ratio (S/(N D)), effective bits, full power
bandwidth, aperture time and aperture jitter are quantitative
measures of the A/D converter’s capability.
3.8 THE CALIBRATION CYCLE
On power up the ADC12451 goes through an Auto-Cal cy-
cle which cannot be interrupted. Since the power supply,
reference, and clock will not be stable at power up, this first
calibration cycle will not result in an accurate calibration of
the A/D. A new calibration cycle needs to be started after
the power supplies, reference, and clock have been given
enough time to stabilize. During the calibration cycle, cor-
rection values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits. Full-
An A/D converter’s ac performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave-
form is applied to the A/D converter’s input, and the trans-
a
form is then performed on the digitized waveform. S/(N D)
and S/N are calculated from the resulting FFT data, and a
spectral plot may also be obtained. Typical values for S/N
are shown in the table of Electrical Characteristics, and
a
spectral plots of S/(N D) are included in the typical per-
formance curves.
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can
a
be seen in the S/(N D) versus frequency curves. These
curves will also give an indication of the full power band-
g
scale error typically changes 0.2 LSB over temperature
and linearity error changes even less; therefore it should be
necessary to go through the calibration cycle only once af-
ter power up if Auto-Zero is used to correct the zero error
a
width (the frequency at which the S/(N D) or S/N drops
3 dB).
TL/H/11025–23
FIGURE 6. Analog Input Equivalent Circuit
15
4.0 Dynamic Performance (Continued)
Effective number of bits can also be useful in describing the
A/D’s noise performance. An ideal A/D converter will have
some amount of quantization noise, determined by its reso-
lution, which will yield an optimum S/N ratio given by the
following equation:
Two sample/hold specifications, aperture time and aperture
jitter, are included in the Dynamic Characteristics table
since the ADC12451 has the ability to track and hold the
analog input voltage. Aperture time is the delay for the A/D
to respond to the hold command. In the case of the
ADC12451, the hold command is internally generated.
When the Auto-Zero function is not being used, the hold
command occurs at the end of the acquisition window, or
seven clock periods after the rising edge of the WR. The
delay between the internally generated hold command and
the time that the ADC12451 actually holds the input signal is
the aperture time. For the ADC12451, this time is typically
100 ns. Aperture jitter is the change in the aperture time
from sample to sample. Aperture jitter is useful in determin-
ing the maximum slew rate of the input signal for a given
accuracy. For example, an ADC12451 with 100 ps of aper-
ture jitter operating with a 5V reference can have an effec-
tive gain variation of about 1 LSB with an input signal whose
slew rate is 12 V/ms.
e
c
a
n 1.8) dB
S/N
(6.02
where n is the A/D’s resolution in bits.
The effective bits of a real A/D converter, therefore, can be
found by:
b
S/N(dB) 1.8
e
n(effective)
6.02
g
As an example, an ADC12451 with a 5V, 10 kHz sine
wave input signal will typically have a S/N of 78 dB, which is
equivalent to 12.6 effective bits.
5.0 Typical Applications
Power Supply Bypassing
TL/H/11025–24
Protecting the Analog Inputs
TL/H/11025–25
Note: External protection diodes should be able to withstand the op amp current limit.
16
17
Physical Dimensions inches (millimeters)
Order Number ADC12451CMJ, ADC12451CMJ/883 or ADC12451CIJ
NS Package Number J24A
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