ADC124S021 [NSC]
4 Channel, 200 kSPS, 12-Bit A/D Converter; 4通道， 200 kSPS时， 12位A / D转换器
| 型号： | ADC124S021 |
| 厂家： | 
National Semiconductor |
| 描述： | 4 Channel, 200 kSPS, 12-Bit A/D Converter |
| 文件： | 总19页 (文件大小：905K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2005
ADC124S021
4 Channel, 200 kSPS, 12-Bit A/D Converter
General Description
Features
n Specified over a range of sample rates.
n Four input channels
The ADC124S021 is a low-power, four-channel CMOS 12-bit
analog-to-digital converter with a high-speed serial interface.
Unlike the conventional practice of specifying performance
at a single sample rate only, the ADC124S021 is fully speci-
fied over a sample rate range of 50 kSPS to 200 kSPS. The
converter is based on a successive-approximation register
architecture with an internal track-and-hold circuit. It can be
configured to accept up to four input signals at inputs IN1
through IN4.
n Variable power management
n Single power supply with 2.7V - 5.25V range
Key Specifications
n DNL
n INL
+0.4 / −0.2 LSB (typ)
0.35 LSB (typ)
n SNR
72.0 dB (typ)
The output serial data is straight binary, and is compatible
n Power Consumption
— 3V Supply
— 5V Supply
™
™
with several standards, such as SPI , QSPI , MICROW-
IRE, and many common DSP serial interfaces.
2.2 mW (typ)
7.9 mW (typ)
The ADC124S021 operates with a single supply that can
range from +2.7V to +5.25V. Normal power consumption
using a +3V or +5V supply is 2.2 mW and 7.9 mW, respec-
tively. The power-down feature reduces the power consump-
tion to just 0.14 µW using a +3V supply, or 0.32 µW using a
+5V supply.
Applications
n Portable Systems
n Remote Data Aquisitions
n Instrumentation and Control Systems
The ADC124S021 is packaged in a 10-lead MSOP package.
Operation over the industrial temperature range of −40˚C to
+85˚C is guaranteed.
Pin-Compatible Alternatives by Resolution and Speed
All devices are fully pin and function compatible.
Resolution
Specified for Sample Rate Range of:
200 to 500 kSPS
50 to 200 kSPS
ADC124S021
ADC104S021
ADC084S021
500 kSPS to 1 MSPS
ADC124S101
12-bit
10-bit
8-bit
ADC124S051
ADC104S051
ADC104S101
ADC084S051
ADC084S101
Connection Diagram
20124305
TRI-STATE® is a trademark of National Semiconductor Corporation
™
™
QSPI and SPI are trademarks of Motorola, Inc.
© 2005 National Semiconductor Corporation
DS201243
www.national.com
Ordering Information
Order Code
Temperature Range
Description
10-Lead MSOP Package
10-Lead MSOP Package, Tape & Reel
Evaluation Board
Top Mark
X21C
ADC124S021CIMM
ADC124S021CIMMX
ADC124S021EVAL
−40˚C to +85˚C
−40˚C to +85˚C
X21C
Block Diagram
20124307
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
4-7
Symbol
Description
IN1 to IN4
Analog inputs. These signals can range from 0V to VA.
DIGITAL I/O
Digital clock input. This clock directly controls the conversion
and readout processes.
10
9
SCLK
DOUT
DIN
Digital data output. The output samples are clocked out of this
pin on falling edges of the SCLK pin.
Digital data input. The ADC124S021’s Control Register is
loaded through this pin on rising edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process
begins. Conversions continue as long as CS is held low.
8
1
CS
POWER SUPPLY
Positive supply pin. This pin should be connected to a quiet
+2.7V to +5.25V source and bypassed to GND with a 1 µF
capacitor and a 0.1 µF monolithic capacitor located within 1
cm of the power pin.
2
3
VA
GND
The ground return for the analog supply and signals.
www.national.com
2
Absolute Maximum Ratings (Notes 1, 2)
Operating Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature Range
−40˚C ≤ TA ≤ +85˚C
VA Supply Voltage
+2.7V to +5.25V
−0.3V to VA
Digital Input Pins Voltage Range
Clock Frequency
Supply Voltage VA
−0.3V to 6.5V
−0.3V to VA +0.3V
10 mA
0.8 MHz to 3.2 MHz
0V to VA
Voltage on Any Pin to GND
Input Current at Any Pin (Note 3)
Package Input Current(Note 3)
Power Consumption at TA = 25˚C
ESD Susceptibility (Note 5)
Human Body Model
Analog Input Voltage
20 mA
Package Thermal Resistance
See (Note 4)
Package
θJA
10-lead MSOP
190˚C / W
2500V
250V
Machine Model
Soldering process must comply with National Semiconduc-
tor’s Reflow Temperature Profile specifications. Refer to
www.national.com/packaging. (Note 6)
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
ADC124S021 Converter Electrical Characteristics (Note 9)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 kSPS to 200
kSPS, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Limits
(Note 7)
Symbol
Parameter
Conditions
Typical
Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12
Bits
+0.35
−0.35
+0.4
+0.8
−1.1
+1.1
−0.8
1.3
LSB (max)
LSB (min)
LSB (max)
LSB (min)
LSB (max)
INL
Integral Non-Linearity
DNL
Differential Non-Linearity
−0.2
VOFF
OEM
FSE
Offset Error
+0.37
Channel to Channel Offset Error
0.1
0.52
0.1
1.0
1.5
1.0
LSB (max)
LSB (max)
LSB (max)
Match
Full-Scale Error
Channel to Channel Full-Scale Error
Match
FSEM
DYNAMIC CONVERTER CHARACTERISTICS
VA = +2.7 to 5.25V
SINAD
SNR
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
72
72
69.2
70.6
−75
dB (min)
dB (min)
dB (max)
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
fIN = 39.9 kHz, −0.02 dBFS
VA = +2.7 to 5.25V
VA = +5.25V
THD
Total Harmonic Distortion
−84
SFDR
ENOB
Spurious-Free Dynamic Range
Effective Number of Bits
86
76
dB (min)
Bits (min)
dB
11.7
−86
11.2
Channel-to-Channel Crosstalk
fIN = 39.9 kHz
Intermodulation Distortion, Second
Order Terms
VA = +5.25V
−87
−88
dB
dB
fa = 40.161 kHz, fb = 41.015 kHz
VA = +5.25V
IMD
Intermodulation Distortion, Third
Order Terms
fa = 40.161 kHz, fb = 41.015 kHz
VA = +5V
11
8
MHz
MHz
FPBW
-3 dB Full Power Bandwidth
VA = +3V
3
www.national.com
ADC124S021 Converter Electrical Characteristics (Note 9) (Continued)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 kSPS to 200
kSPS, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Limits
(Note 7)
Symbol
Parameter
Conditions
Typical
Units
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
0 to VA
0.02
33
V
µA (max)
pF
IDCL
DC Leakage Current
1
Track Mode
Hold Mode
CINA
Input Capacitance
3
pF
DIGITAL INPUT CHARACTERISTICS
VA = +5.25V
VA = +3.6V
2.4
2.1
0.8
10
4
V (min)
V (min)
VIH
Input High Voltage
VIL
Input Low Voltage
Input Current
V (max)
µA (max)
pF (max)
IIN
VIN = 0V or VA
0.02
2
CIND
Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA
ISOURCE = 1 mA
ISINK = 200 µA
ISINK = 1 mA
VA − 0.03
VA − 0.1
0.02
VA − 0.5
0.4
V (min)
VOH
VOL
Output High Voltage
V
V (max)
V
Output Low Voltage
0.1
IOZH
IOZL
COUT
,
TRI-STATE® Leakage Current
0.01
2
1
4
µA (max)
pF (max)
TRI-STATE® Output Capacitance
Output Coding
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
2.7
V (min)
VA
Supply Voltage
5.25
V (max)
VA = +5.25V
1.5
0.62
60
2.1
1.0
mA (max)
fSAMPLE = 200 kSPS, fIN = 39.9 kHz
VA = +3.6V,
Supply Current, Normal Mode
(Operational, CS low)
mA (max)
fSAMPLE = 200 kSPS, fIN = 39.9 kHz
VA = +5.25V
IA
nA
nA
fSAMPLE = 0 kSPS
VA = +3.6V,
Supply Current, Shutdown (CS high)
38
fSAMPLE = 0 kSPS
VA = +5.25V
7.9
2.2
11.0
3.6
mW (max)
mW (max)
µW
Power Consumption, Normal Mode
(Operational, CS low)
VA = +3.6V,
PD
VA = +5.25V
0.32
0.14
Power Consumption, Shutdown (CS
high)
VA = +3.6V,
µW
AC ELECTRICAL CHARACTERISTICS
0.8
3.2
50
200
13
30
70
3
MHz (min)
MHz (max)
kSPS (min)
kSPS (max)
SCLK cycles
% (min)
fSCLK
Maximum Clock Frequency
(Note 8)
(Note 8)
fS
Sample Rate
tCONV
DC
Conversion Time
SCLK Duty Cycle
fSCLK = 3.2 MHz
50
% (max)
tACQ
Track/Hold Acquisition Time
Throughput Time
Full-Scale Step Input
SCLK cycles
SCLK cycles
Acquisition Time + Conversion Time
16
www.national.com
4
ADC124S021 Timing Specifications
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 kSPS to 200
kSPS, CL = 35 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Limits
(Note 7)
Symbol
tCSU
Parameter
Conditions
VA = +3.0V
Typical
Units
−3.5
−0.5
+4.5
+1.5
+4
Setup Time SCLK High to CS Falling Edge
Hold time SCLK Low to CS Falling Edge
Delay from CS Until DOUT active
(Note 10)
(Note 10)
10
ns (min)
ns (min)
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
tCLH
10
30
30
ns
tEN
(max)
+2
+14.5
+13
+3
ns
tACC
Data Access Time after SCLK Falling Edge
(max)
tSU
tH
Data Setup Time Prior to SCLK Rising Edge
Data Valid SCLK Hold Time
10
ns (min)
ns (min)
+3
10
0.5 x
tSCLK
0.5 x
tSCLK
1.8
0.3 x
tSCLK
0.3 x
tSCLK
tCH
tCL
SCLK High Pulse Width
SCLK Low Pulse Width
ns (min)
ns (min)
VA = +3.0V
VA = +5.0V
VA = +3.0V
VA = +5.0V
Output Falling
Output Rising
1.3
ns
tDIS
CS Rising Edge to DOUT High-Impedance
20
(max)
1.0
1.0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
<
>
V ), the current at that pin should be limited to 10 mA. The 20
Note 3: When the input voltage at any pin exceeds the power supply (that is, V
GND or V
IN
IN
A
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the V pin. The current into the V pin is limited by the Analog Supply Voltage specification.
A
A
Note 4: The absolute maximum junction temperature (T max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T max, the
J
J
junction-to-ambient thermal resistance (θ ), and the ambient temperature (T ), and can be calculated using the formula P MAX = (T max − T )/θ . The values
JA
A
D
J
A
JA
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under
Operating Ratings.
Note 9: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 10: Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t
and t
.
CLH
CSU
5
www.national.com
Timing Diagrams
20124351
ADC124S021 Operational Timing Diagram
20124308
Timing Test Circuit
20124306
ADC124S021 Serial Timing Diagram
20124350
SCLK and CS Timing Parameters
www.national.com
6
order intermodulation products to the sum of the power in
both of the original frequencies. IMD is usually expressed in
dB.
Specification Definitions
ACQUISITION TIME is the time required to acquire the input
voltage. That is, it is time required for the hold capacitor to
charge up to the input voltage.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC124S021 is guaranteed
not to have any missing codes.
APERTURE DELAY is the time between the fourth falling
SCLK edge of a conversion and the time when the input
signal is acquired or held for conversion.
OFFSET ERROR is the deviation of the first code transition
(000...000) to (000...001) from the ideal (i.e. GND + 0.5
LSB).
CONVERSION TIME is the time required, after the input
voltage is acquired, for the ADC to convert the input voltage
to a digital word.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
CROSSTALK is the coupling of energy from one channel
into the other channel, or the amount of signal energy from
one analog input that appears at the measured analog input.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral compo-
nents below half the clock frequency, including harmonics
but excluding d.c.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital
waveform is high to the total time of one period. The speci-
fication here refers to the SCLK.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal where a spurious signal
is any signal present in the output spectrum that is not
present at the input, excluding d.c.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD − 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first five
harmonic components at the output to the rms level of the
input signal frequency as seen at the output. THD is calcu-
lated as
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition
(111...110) to (111...111) from the ideal (VREF − 1.5 LSB),
after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (1⁄
2
LSB below the first code transition)
through positive full scale (1⁄
2
LSB above the last code
where Af1 is the RMS power of the input frequency at the
output and Af2 through Af6 are the RMS power in the first 5
harmonic frequencies.
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
THROUGHPUT TIME is the minimum time required between
the start of two successive conversion. It is the acquisition
time plus the conversion time. In the case of the
ADC124S021, this is 16 SCLK periods.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
7
www.national.com
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 50 kSPS to 200 kSPS, fSCLK = 0.8
MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.
DNL - VA = 3.0V
DNL - VA = 5.0V
DNL vs. Supply
INL - VA = 3.0V
INL - VA = 5.0V
INL vs. Supply
20124320
20124362
20124322
20124321
20124363
20124323
www.national.com
8
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 50 kSPS to 200 kSPS, fSCLK = 0.8 MHz
to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. (Continued)
DNL vs. Clock Frequency
DNL vs. Clock Duty Cycle
DNL vs. Temperature
INL vs. Clock Frequency
INL vs. Clock Duty Cycle
INL vs. Temperature
20124324
20124326
20124328
20124325
20124327
20124329
9
www.national.com
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 50 kSPS to 200 kSPS, fSCLK = 0.8 MHz
to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. (Continued)
SNR vs. Supply
THD vs. Supply
20124330
20124331
20124332
20124335
20124336
20124337
SNR vs. Clock Frequency
THD vs. Clock Frequency
SNR vs. Clock Duty Cycle
THD vs. Clock Duty Cycle
www.national.com
10
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 50 kSPS to 200 kSPS, fSCLK = 0.8 MHz
to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. (Continued)
SNR vs. Input Frequency
SNR vs. Temperature
SFDR vs. Supply
THD vs. Input Frequency
THD vs. Temperature
SINAD vs. Supply
20124333
20124334
20124340
20124338
20124339
20124345
11
www.national.com
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 50 kSPS to 200 kSPS, fSCLK = 0.8 MHz
to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. (Continued)
SFDR vs. Clock Frequency
SFDR vs. Clock Duty Cycle
SFDR vs. Input Frequency
SINAD vs. Clock Frequency
SINAD vs. Clock Duty Cycle
SINAD vs. Input Frequency
20124341
20124342
20124343
20124346
20124347
20124348
www.national.com
12
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 50 kSPS to 200 kSPS, fSCLK = 0.8 MHz
to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. (Continued)
SFDR vs. Temperature
SINAD vs. Temperature
ENOB vs. Clock Frequency
ENOB vs. Input Frequency
20124344
20124352
20124354
20124349
20124353
20124355
ENOB vs. Supply
ENOB vs. Clock Duty Cycle
13
www.national.com
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 50 kSPS to 200 kSPS, fSCLK = 0.8 MHz
to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated. (Continued)
ENOB vs. Temperature
Spectral Response - 3V, 200 ksps
20124356
20124359
Spectral Response - 5V, 200 ksps
Power Consumption vs. Throughput
20124360
20124361
www.national.com
14
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add fixed amounts of charge to the sampling capaci-
tor until the comparator is balanced. When the comparator is
balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The
ADC124S021 is in this state for the fourth through sixteenth
SCLK cycles after CS is brought low.
Applications Information
1.0 ADC124S021 OPERATION
The ADC124S021 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution
digital-to-analog converter. Simplified schematics of the
ADC124S021 in both track and hold modes are shown in
Figures 1, 2, respectively. In Figure 1, the ADC124S021 is in
track mode: switch SW1 connects the sampling capacitor to
one of four analog input channels through the multiplexer,
and SW2 balances the comparator inputs. The
ADC124S021 is in this state for the first three SCLK cycles
after CS is brought low.
The time when CS is low is considered a serial frame. Each
of these frames should contain an integer multiple of 16
SCLK cycles, during which time a conversion is performed
and clocked out at the DOUT pin and data is clocked into the
DIN pin to indicate the multiplexer address for the next
conversion.
Figure 2 shows the ADC124S021 in hold mode: switch SW1
connects the sampling capacitor to ground, maintaining the
20124309
FIGURE 1. ADC124S021 in Track Mode
20124310
FIGURE 2. ADC124S021 in Hold Mode
2.0 USING THE ADC124S021
During the first 3 cycles of SCLK, the ADC is in the track
mode, acquiring the input voltage. For the next 13 SCLK
cycles the conversion is accomplished and the data is
clocked out, MSB first, starting on the 5th clock. If there is
more than one conversion in a frame, the ADC will re-enter
the track mode on the falling edge of SCLK after the N*16th
rising edge of SCLK, and re-enter the hold/convert mode on
the N*16+4th falling edge of SCLK, where "N" is an integer.
An ADC124S021 timing diagram and a serial interface timing
diagram for the ADC124S021 are shown in the Timing Dia-
grams section. CS is chip select, which initiates conversions
and frames the serial data transfers. SCLK (serial clock)
controls both the conversion process and the timing of serial
data. DOUT is the serial data output pin, where a conversion
result is sent as a serial data stream, MSB first. Data to be
written to the ADC124S021’s Control Register is placed on
DIN, the serial data input pin. New data is written to DIN with
each conversion.
When CS is brought high, SCLK is internally gated off. If
SCLK is stopped in the low state while CS is high, the
subsequent fall of CS will generate a falling edge of the
internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of
SCLK. If SCLK is stopped with SCLK high, the ADC enters
the track mode on the first falling edge of SCLK after the
falling edge of CS.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. Each frame must contain an integer
multiple of 16 rising SCLK edges. The ADC output data
(DOUT) is in a high impedance state when CS is high and is
active when CS is low. Thus, CS acts as an output enable.
Additionally, the device goes into a power down state when
CS is high, and also between continuous conversion cycles.
During each conversion, data is clocked into the DIN pin on
the first 8 rising edges of SCLK after the fall of CS. For each
15
www.national.com
There are no power-up delays or dummy conversions re-
quired with the ADC124S021. The ADC is able to sample
and convert an input to full conversion immediately following
power up. The first conversion result after power-up will be
that of IN1.
Applications Information (Continued)
conversion, it is necessary to clock in the data indicating the
input that is selected for the conversion after the current one.
See Tables 1, 2 and 3.
If CS and SCLK go low simultaneously, it is the following
rising edge of SCLK that is considered the first rising edge
for clocking data into DIN.
TABLE 1. Control Register Bits
Bit 4 Bit 3
ADD1 ADD0
Bit 7 (MSB)
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
DONTC
DONTC
ADD2
DONTC
DONTC
DONTC
TABLE 2. Control Register Bit Descriptions
Description
Bit #:
Symbol:
DONTC
ADD2
7 - 6, 2 - 0
Don’t care. The value of these bits do not affect device operation.
These three bits determine which input channel will be sampled and
5
4
3
converted in the next track/hold cycle. The mapping between codes and
ADD1
channels is shown in Table 3.
ADD0
TABLE 3. Input Channel Selection
ADD2
ADD1
ADD0
Input Channel
x
x
x
x
0
0
1
1
0
1
0
1
IN1 (Default)
IN2
IN3
IN4
www.national.com
16
LSB values. The LSB width for the ADC124S021 is VA/4096.
The ideal transfer characteristic is shown in Figure 3. The
transition from an output code of 0000 0000 0000 to a code
of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192.
Other code transitions occur at steps of one LSB.
Applications Information (Continued)
3.0 ADC124S021 TRANSFER FUNCTION
The output format of the ADC124S021 is straight binary.
Code transitions occur midway between successive integer
20124311
FIGURE 3. Ideal Transfer Characteristic
4.0 TYPICAL APPLICATION CIRCUIT
will degrade device noise performance. To keep noise off the
supply, use a dedicated linear regulator for this device, or
provide sufficient decoupling from other circuitry to keep
noise off the ADC124S021 supply pin. Because of the
ADC124S021’s low power requirements, it is also possible to
use a precision reference as a power supply to maximize
performance. The four-wire interface is also shown con-
nected to a microprocessor or DSP.
A typical application of the ADC124S021 is shown in Figure
4. Power is provided in this example by the National Semi-
conductor LP2950 low-dropout voltage regulator, available in
a variety of fixed and adjustable output voltages. The power
supply pin is bypassed with a capacitor network located
close to the ADC124S021. Because the reference for the
ADC124S021 is the supply voltage, any noise on the supply
20124313
FIGURE 4. Typical Application Circuit
17
www.national.com
The user may trade off throughput for power consumption by
simply performing fewer conversions per unit time. The
Power Consumption vs. Sample Rate curve in the Typical
Performance Curves section shows the typical power con-
sumption of the ADC124S021 versus throughput. To calcu-
late the power consumption, simply multiply the fraction of
time spent in the normal mode by the normal mode power
consumption , and add the fraction of time spent in shutdown
mode multiplied by the shutdown mode power dissipation.
Applications Information (Continued)
5.0 ANALOG INPUTS
An equivalent circuit for one of the ADC124S021’s input
channels is shown in Figure 5. Diodes D1 and D2 provide
ESD protection for the analog inputs. At no time should any
input go beyond (VA + 300 mV) or (GND − 300 mV), as these
ESD diodes will begin conducting, which could result in
erratic operation.
The capacitor C1 in Figure 5 has a typical value of 3 pF, and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch, and is
typically 500 ohms. Capacitor C2 is the ADC124S021 sam-
pling capacitor, and is typically 30 pF. The ADC124S021 will
deliver best performance when driven by a low-impedance
source to eliminate distortion caused by the charging of the
sampling capacitance. This is especially important when
using the ADC124S021 to sample AC signals. Also important
when sampling dynamic signals is a band-pass or low-pass
filter to reduce harmonics and noise, improving dynamic
performance.
7.1 Power Management
When the ADC124S021 is operated continuously in normal
mode, the maximum throughput is fSCLK/16. Throughput
may be traded for power consumption by running fSCLK at its
maximum 3.2 MHz and performing fewer conversions per
unit time, putting the ADC124S021 into shutdown mode
between conversions. A plot of typical power consumption
versus throughput is shown in the Typical Performance
Curves section. To calculate the power consumption for a
given throughput, multiply the fraction of time spent in the
normal mode by the normal mode power consumption and
add the fraction of time spent in shutdown mode multiplied
by the shutdown mode power consumption. Generally, the
user will put the part into normal mode and then put the part
back into shutdown mode. Note that the curve of power
consumption vs. throughput is nearly linear. This is because
the power consumption in the shutdown mode is so small
that it can be ignored for all practical purposes.
7.2 Power Supply Noise Considerations
The charging of any output load capacitance requires cur-
rent from the power supply, VA. The current pulses required
from the supply to charge the output capacitance will cause
voltage variations on the supply. If these variations are large
enough, they could degrade SNR and SINAD performance
of the ADC. Furthermore, discharging the output capaci-
tance when the digital output goes from a logic high to a logic
low will dump current into the die substrate, which is resis-
tive. Load discharge currents will cause "ground bounce"
noise in the substrate that will degrade noise performance if
that current is large enough. The larger is the output capaci-
tance, the more current flows through the die substrate and
the greater is the noise coupled into the analog channel,
degrading noise performance.
20124314
FIGURE 5. Equivalent Input Circuit
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC124S021’s digital output DOUT is limited by, and
cannot exceed, the supply voltage, VA. The digital input pins
are not prone to latch-up and, and although not recom-
mended, SCLK, CS and DIN may be asserted before VA
without any latchup risk.
7.0 POWER SUPPLY CONSIDERATIONS
To keep noise out of the power supply, keep the output load
capacitance as small as practical. If the load capacitance is
greater than 35 pF, use a 100 Ω series resistor at the ADC
output, located as close to the ADC output pin as practical.
This will limit the charge and discharge current of the output
capacitance and improve noise performance.
The ADC124S021 is fully powered-up whenever CS is low,
and fully powered-down whenever CS is high, with one
exception: the ADC124S021 automatically enters power-
down mode between the 16th falling edge of a conversion
and the 1st falling edge of the subsequent conversion (see
Timing Diagrams).
The ADC124S021 can perform multiple conversions back to
back; each conversion requires 16 SCLK cycles. The
ADC124S021 will perform conversions continuously as long
as CS is held low.
www.national.com
18
Physical Dimensions inches (millimeters) unless otherwise noted
10-Lead MSOP
Order Number ADC124S021CIMM, ADC124S021CIMMX
NS Package Number P0MUB10A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
相关型号：
©2020 ICPDF网 联系我们和版权申明