ADC1241CIJ [NSC]
Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter with Sample-and-Hold; 自校准12位加符号位MP-兼容A / D转换器采样和保持
| 型号： | ADC1241CIJ |
| 厂家： | 
National Semiconductor |
| 描述： | Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter with Sample-and-Hold |
| 文件： | 总14页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1994
ADC1241 Self-Calibrating 12-Bit Plus
Sign mP-Compatible A/D Converter
with Sample-and-Hold
General Description
The ADC1241 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter. On request, the
ADC1241 goes through a self-calibration cycle that adjusts
g
positive linearity and full-scale errors to less than (/2 LSB
each and zero error to less than 1 LSB. The ADC1241
Key Specifications
Y
Y
Y
Y
Y
Y
Resolution
12 Bits plus Sign
Conversion Time
Linearity Error
13.8ms (max)
g
g
(/2 LSB ( 0.0122%) (max)
g
g
Zero Error
1LSB (max)
1LSB (max)
g
Positive Full Scale Error
Power Consumption
also has the ability to go through an Auto-Zero cycle that
corrects the zero error during every conversion.
70mW (max)
The analog input to the ADC1241 is tracked and held by the
internal circuitry, and therefore does not require an external
sample-and-hold. A unipolar analog input voltage range (0V
Features
Y
Self-calibrating
Y
Internal sample-and-hold
a
b
a
to 5V) or a bipolar range ( 5V to 5V) can be accom-
Y
g
Bipolar input range with 5V supplies and single
g
modated with 5V supplies.
a
5V reference
The 13-bit word on the outputs of the ADC1241 gives a 2’s
complement representation of negative numbers. The digi-
tal inputs and outputs are compatible with TTL or CMOS
logic levels.
Y
Y
Y
No missing codes over temperature
TTL/MOS input/output compatible
Standard 28-pin DIP
Applications
Y
Digital Signal Processing
Y
High Resolution Process Control
Y
Instrumentation
TRI-STATE is a registered trademark of National Semiconductor Corporation.
É
Simplified Schematic
Connection Diagram
Dual-In-Line Package
TL/H/10554–2
Top View
Order Number ADC1241CMJ,
ADC1241CMJ/883, ADC1241BIJ or
ADC1241CIJ
See NS Package Number J28A
TL/H/10554–1
C
1995 National Semiconductor Corporation
TL/H/10554
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Ratings (Notes 1 & 2)
s
s
T
MAX
Temperature Range
ADC1241BIJ, ADC1241CIJ
T
40 C
T
A
MIN
s
s
a
b
b
a
125 C
T
A
85 C
§
ADC1241CMJ, ADC1241CMJ/883 55 C
§
s
s
T
A
§
§
e
e
AV
Supply Voltage (V
CC
DV
)
6.5V
6.5V
DV
and AV
Voltage
CC
CC
CC
CC
(Notes 6 & 7)
Negative Supply Voltage (Vb
Voltage at Logic Control Inputs
Voltage at Analog Input (V
)
4.5V to 5.5V
b
Negative Supply Voltage (Vb
)
b
b
4.5V to 5.5V
b
a
a
0.3V to (V
0.3V)
0.3V)
0.3V
CC
)
(Vb 0.3V) to (V
Reference Voltage
, Notes 6 & 7)
REF
b
IN
CC
a
50 mV
(V
3.5V to AV
CC
AV -DV (Note 7)
CC CC
g
Input Current at any Pin (Note 3)
Package Input Current (Note 3)
5 mA
g
20 mA
Power Dissipation at 25 C (Note 4)
§
Storage Temperature Range
875 mW
b
a
65 C to 150 C
§
§
2000V
ESD Susceptability (Note 5)
Soldering Information
J Package (10 sec)
300 C
§
Converter Electrical Characteristics
CC
b
e
unless otherwise specified. Boldface limits apply for T
e
e a
e b
e a
; all other limits T
e
CLK
§
The following specifications apply for V
DV
AV
CC
e
5.0V, V
T
5.0V, V
5.0V, and f
2.0 MHz
e
T 25 C. (Notes 6, 7
J
CC
REF
e
e
T
to T
A
J
MIN
MAX
A
and 8)
Typical
Limit
Units
(Note 9) (Notes 10, 18) (Limit)
Symbol
Parameter
Conditions
STATIC CHARACTERISTICS
g
Positive Integral
Linearity Error
ADC1241BIJ
After Auto-Cal
(Notes 11 & 12)
(2
LSB(max)
LSB max
LSB(max)
LSB(max)
g
g
g
ADC1241CMJ, CIJ
ADC1241BIJ
1
1
1
Negative Integral
Linearity Error
After Auto-Cal
(Notes 11 & 12)
ADC1241CMJ, CIJ
Differential Linearity
Zero Error
After Auto-Cal (Notes 11 & 12)
12
Bits(min)
After Auto-Zero or Auto-Cal
(Notes 12 & 13)
g
g
1
1
LSB(max)
g
Positive Full-Scale Error
Negative Full-Scale Error
After Auto-Cal (Note 12)
After Auto-Cal (Note 12)
(/2
LSB(max)
LSB(max)
pF
g
g
2
1 /
C
C
V
V
REF
Input Capacitance
80
65
REF
Analog Input Capacitance
Analog Input Voltage
pF
IN
Vb
0.05 V(min)
0.05 V(max)
b
a
IN
V
CC
e
e
e
5V 5%,
g
g
Power Supply
Sensitivity
Zero Error (Note 14) AV
V
DV
CC
4.75V, V
(/8
(/8
(/8
LSB
LSB
LSB
CC
b
e b
g
5V 5%
REF
g
g
Full-Scale Error
Linearity Error
DYNAMIC CHARACTERISTICS
a
a
e
e
1 kHz, V 4.85 V
IN p-p
S/(N D) Unipolar Signal-to-Noise Distortion
Ratio (Note 17)
f
f
f
f
72
dB
dB
IN
e
e
e
e
4.85 V
p-p
10 kHz, V
IN
72
76
IN
IN
IN
a
a
e
g
1 kHz, V
IN
S/(N D) Bipolar Signal-to-Noise Distortion
Ratio (Note 17)
4.85 V
p-p
dB
e
g
10 kHz, V
IN
4.85 V
p-p
76
dB
e
Unipolar Full Power Bandwidth (Note 17)
Bipolar Full Power Bandwidth (Note 17)
V
0V to 4.85V
32
kHz
kHz
ns
IN
IN
e
g
V
4.85 V
p-p
25
t
Ap
Aperture Time
Aperture Jitter
100
100
ps
rms
2
Digital and DC Electrical Characteristics
CC
b
e
unless otherwise specified. Boldface limits apply for T
e
e a
e b
e a
; all other limits T
e
2.0 MHz
CLK
The following specifications apply for V
DV
CC
AV
CC
e
5.0V, V
T
5.0V, V
5.0V, and f
REF
e
e
e
T 25 C.
J
T
to T
§
A
J
MIN
MAX
A
(Notes 6 and 7)
Typical
Limit
Units
Symbol
Parameter
Condition
(Note 9)
(Notes 10, 18)
(Limits)
e
V
Logical ‘‘1’’ Input Voltage for
All Inputs except CLK IN
V
V
5.25V
IN(1)
IN(0)
IN(1)
CC
2.0
V(min)
V(max)
e
V
Logical ‘‘0’’ Input Voltage for
All Inputs except CLK IN
4.75V
CC
0.8
1
e
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
V
V
5V
0V
0.005
mA(max)
mA(max)
IN
e
b
b
1
0.005
2.8
IN(0)
IN
a
V
V
V
V
CLK IN Positive-Going
Threshold Voltage
T
2.7
2.3
0.4
V(min)
V(max)
V(min)
b
CLK IN Negative-Going
Threshold Voltage
T
2.1
0.7
CLK IN Hysteresis
b
H
a
b
[
V
]
(min)
V
T
(max)
T
e
e b
e b
Logical ‘‘1’’ Output Voltage
V
4.75V:
OUT(1)
CC
OUT
OUT
I
I
360 mA
10 mA
2.4
4.5
V(min)
V(min)
e
e
V
I
Logical ‘‘0’’ Output Voltage
V
4.75V
1.6 mA
V(max)
OUT(0)
CC
0.4
I
OUT
e
OUT
b
b
3
TRI-STATE Output Leakage
É
Current
V
V
V
V
0V
5V
0V
5V
0.01
mA(max)
mA(max)
mA(min)
mA(min)
mA(max)
mA(max)
mA(max)
OUT
e
e
e
0.01
3
OUT
OUT
OUT
b
b
6.0
8.0
I
I
Output Source Current
Output Sink Current
20
SOURCE
SINK
20
e
e
e
e
DI
DV Supply Current
CC
f
f
f
2 MHz, CS
2 MHz, CS
2 MHz, CS
‘‘1’’
1
2
6
6
CC
CLK
CLK
CLK
e
e
AI
AV Supply Current
CC
‘‘1’’
‘‘1’’
2.8
2.8
CC
Ib
Vb Supply Current
3
AC Electrical Characteristics
The following specifications apply for DV
CC
b
e
e a
e b
e
e
t 20 ns unless otherwise specified.
f
AV
CC
5.0V, V
; all other limits T
5.0V, t
e
T
J
r
e
e
e
Boldface limits apply for T
T
T
MIN
to T
25 C. (Notes 6 and 7)
§
A
J
MAX
A
Typical
(Note 9)
Limit
Units
Symbol
Parameter
Clock Frequency
Conditions
(Notes 10, 18)
(Limits)
f
2.0
MHz
CLK
0.5
4.0
MHz(min)
MHZ(max)
Clock Duty Cycle
Conversion Time
50
%
40
60
%(min)
%(max)
a
)
CLK
t
C
27(1/f
)
27(1/f
300 ns
(max)
CLK
e
f
2.0 MHz
13.5
ms
CLK
e
a
300 ns
t
t
Acquisition Time
(Note 15)
R
50X
7(1/f
)
7(1/f
)
(max)
A
SOURCE
CLK
3.5
CLK
e
e
e
f
f
f
2.0 MHz
2.0 MHz
2.0 MHz
ms
CLK
CLK
CLK
Auto Zero Time
26
13
26
1/f
(max)
CLK
Z
ms
t
Calibration Time
1396
698
60
1/f
CLK
CAL
706
200
200
ms (max)
ns(min)
ns(min)
t
t
t
Calibration Pulse Width
(Note 16)
W(CAL)L
W(WR)L
ACC
Minimum WR Pulse Width
Maximum Access Time
60
e
C
L
100 pF
(Delay from Falling Edge of
RD to Output Data Valid)
50
85
ns(max)
e
e
t
t
, t
0H 1H
TRI-STATE Control (Delay
from Rising Edge of RD
to Hi-Z State)
R
1 kX,
L
C
L
100 pF
30
90
ns(max)
ns(max)
Maximum Delay from Falling Edge of
RD or WR to Reset of INT
PD(INT)
100
175
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
b
k
l
(AV or DV ), the current at that pin should be limited to
CC CC
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
V
or V
IN
IN
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(maximum junction temperature), i (package
JA
JMAX
junction to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is P
e
b
(T
Jmax
JA
A
Dmax
e
Jmax
T
)/i or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
JA
ADC1241 with CMJ, BIJ, and CIJ suffixes when board mounted is 47 C/W.
125 C, and the typical thermal resistance (i ) of the
§
A
§
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than
50 mV.
TL/H/10554–3
are minimum (4.75 V ) and Vb is maximum ( 4.75 V ), full-scale must be
4.8 V
.
DC
s
b
This means that if AV
and DV
CC
CC
D
C
D
C
4
AC Electrical Characteristics (Continued)
Note 7: A diode exists between AV
and DV
as shown below.
CC
CC
TL/H/10554–4
be connected together to a power supply with separate bypass filters at each V pin.
CC
To guarantee accuracy, it is required that the AV
and DV
CC
CC
e
Note 8: Accuracy is guaranteed at f
2.0 MHz. At higher and lower clock frequencies accuracy may degrade. See curves in the Typical Performance
CLK
Characteristics Section.
e
Note 9: Typicals are at T
25 C and represent most likely parametric norm.
§
Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
J
Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See Figures 1b and 1c).
Note 12: The ADC1241’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
g
result in a repeatability uncertainty of 0.20 LSB.
Note 13: If T changes then an Auto-Zero or Auto-Cal cycle will have to be re-started, see the typical performance characteristic curves.
A
Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
e
A
Note 15: If the clock is asynchronous to the falling edge of WR an uncertainty of one clock period will exist in the interval of t , therefore making the minimum t
A
e
6 clock periods and the maximum t
periods.
7 clock periods. If the falling edge of the clock is synchronous to the rising edge of WR then t will be exactly 6.5 clock
A
A
Note 16: The CAL line must be high before any other conversion is started.
Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18: A military RETS electrical test specification is available on request. At time of printing, the ADC1241CMJ/883 RETS specification complies fully with the
boldface limits in this column.
TL/H/10554–5
FIGURE 1a. Transfer Characteristic
5
AC Electrical Characteristics (Continued)
TL/H/10554–6
FIGURE 1b. Simplified Error Curve vs Output Code Without Auto-Cal or Auto-Zero Cycles
TL/H/10554–7
FIGURE 1c. Simplified Error Curve vs Output Code After Auto-Cal Cycle
Typical Performance Characteristics
Zero Error Change vs
Ambient Temperature
Zero Error vs V
REF
TL/H/10554–8
6
Typical Performance Characteristics (Continued)
Linearity Error vs Clock
Frequency
Full Scale Error Change vs
Ambient Temperature
Linearity Error vs V
REF
s
e
put
se
put
TL/H/10554–21
7
Test Circuits
TL/H/10554–10
TL/H/10554–9
TL/H/10554–12
TL/H/10554–11
FIGURE 2. TRI-STATE Test Circuits and Waveforms
Timing Diagrams
e
e
e
e
e
X, X Don’t Care)
Auto-Cal Cycle (CS
1, WR
X, RD
X, AZ
TL/H/10554–13
8
Timing Diagrams (Continued)
e
e
0)
Normal Conversion with Auto-Zero (CAL
1, AZ
TL/H/10554–14
e
e
1)
Normal Conversion without Auto-Zero (CAL
1, AZ
TL/H/10554–15
9
1.0 Pin Descriptions
DV
CC
AV
(28),
(4)
DB0–DB12
(15–27)
The digital and analog positive power supply
pins. The digital and analog power supply
The TRI-STATE output pins. The output is in
two’s complement format with DB12 the sign
bit, DB11 the MSB and DB0 the LSB.
CC
a
voltage range of the ADC1241 is 4.5V to
a
5.5V. To guarantee accuracy, it is required
that the AV and DV be connected to-
gether to the same power supply with sepa-
CC CC
2.0 Functional Description
The ADC1241 is a 12-bit plus sign A/D converter with the
capability of doing Auto-Zero or Auto-Cal routines to mini-
mize zero, full-scale and linearity errors. It is a successive-
approximation A/D converter consisting of a DAC, compar-
ator and a successive-approximation register (SAR). Auto-
Zero is an internal calibration sequence that corrects for the
A/D’s zero error caused by the comparator’s offset voltage.
Auto-Cal is a calibration cycle that not only corrects zero
error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies. Auto-Cal minimizes the errors
of the ADC1241 without the need of trimming during its fab-
rication. An Auto-Cal cycle can restore the accuracy of the
ADC1241 at any time, which ensures its long term stability.
rate bypass filters (10 mF tantalum in parallel
with a 0.1 mF ceramic) at each V
pin.
CC
The analog negative supply voltage pin. Vb
Vb (5)
b
b
has a range of 4.5V to 5.5V and needs a
bypass filter of 10 mF tantalum in parallel with
a 0.1 mF ceramic.
DGND (14), The digital and analog ground pins. AGND
and DGND must be connected together ex-
ternally to guarantee accuracy.
AGND (3)
V
V
(2)
The reference input voltage pin. To maintain
accuracy the voltage at this pin should not
REF
exceed the AV or DV by more than
CC CC
50 mV or go below 3.5 VDC.
2.1 DIGITAL INTERFACE
(1)
The analog input voltage pin. To guarantee
accuracy the voltage at this pin should not
IN
On power up, a calibration sequence should be initiated by
pulsing CAL low with CS, RD, and WR high. To acknowl-
edge the CAL signal, EOC goes low after the falling edge of
CAL, and remains low during the calibration cycle of 1396
clock periods. During the calibration sequence, first the
comparator’s offset is determined, then the capacitive
DAC’s mismatch error is found. Correction factors for these
errors are then stored in internal RAM.
exceed V by more than 50 mV or go below
CC
Vb by more than 50 mV.
CS (10)
RD (11)
WR (7)
The Chip Select control input. This input is
active low and enables the WR and RD func-
tions.
The Read control input. With both CS and RD
low the TRI-STATE output buffers are en-
abled and the INT output is reset high.
A conversion is initiated by taking CS and WR low. The AZ
(Auto Zero) signal line should be tied high or low during the
conversion process. If AZ is low an auto zero cycle, which
takes approximately 26 clock periods, occurs before the ac-
tual conversion is started. The auto zero cycle determines
the correction factors for the comparator’s offset voltage. If
AZ is high, the auto zero cycle is skipped. Next the analog
input is sampled for 7 clock periods, and held in the capaci-
tive DAC’s ladder structure. The EOC then goes low, signal-
ing that the analog input is no longer being sampled and
that the A/D successive approximation conversion has
started.
The Write control input. The converison is
started on the rising edge of the WR pulse
when CS is low.
CLK (8)
CAL (9)
The external clock input pin. The clock fre-
quency range is 500 kHz to 4 MHz.
The Auto-Calibration control input. When
CAL is low the ADC1241 is reset and a cali-
bration cycle is initiated. During the calibra-
tion cycle the values of the comparator offset
voltage and the mismatch errors in the ca-
pacitor reference ladder are determined and
stored in RAM. These values are used to cor-
rect the errors during a normal cycle of A/D
conversion.
During a conversion, the sampled input voltage is succes-
sively compared to the output of the DAC. First, the ac-
quired input voltage is compared to analog ground to deter-
mine its polarity. The sign bit is set low for positive input
voltages and high for negative. Next the MSB of the DAC is
set high with the rest of the bits low. If the input voltage is
greater than the output of the DAC, then the MSB is left
high; otherwise it is set low. The next bit is set high, making
the output of the DAC three quarters or one quarter of full
scale. A comparison is done and if the input is greater than
the new DAC value this bit remains high; if the input is less
than the new DAC value the bit is set low. This process
continues until each bit has been tested. The result is then
stored in the output latch of the ADC1241. Next EOC goes
high, and INT goes low to signal the end of the conversion.
The result can now be read by taking CS and RD low to
enable the DB0–DB12 output buffers.
AZ (6)
The Auto-Zero control input. With the AZ pin
held low during a conversion, the ADC1241
goes into an auto-zero cycle before the actu-
al A/D conversion is started. This Auto-Zero
cycle corrects for the comparator offset volt-
age. The total conversion time (t ) is in-
C
creased by 26 clock periods when Auto-Zero
is used.
EOC (12)
INT (13)
The End-of-Conversion control output. This
output is low during a conversion or a calibra-
tion cycle.
The Interrupt control output. This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches. Reading the
result or starting a conversion or calibration
cycle will reset this output high.
10
2.0 Functional Description (Continued)
Digital Control Inputs
A/D Function
CS WR RD CAL AZ
ß
ß
ß
ß
1
ß
1
1
ß
1
1
1
1
1
0
0
X
X
Start Conversion without Auto-Zero
Read Conversion Result without Auto-Zero
Start Conversion with Auto-Zero
ß
1
1
ß
X
1
Read Conversion Result with Auto-Zero
Start Calibration Cycle
X
ß
0
0
X
1
Test Mode (DB2, DB3, DB5 and DB6 become active)
FIGURE 1. Function of the A/D Control Inputs
The table in Figure 1 summarizes the effect of the digital
control inputs on the function of the ADC1241. The Test
Mode, where RD is high and CS and CAL are low, is used by
the factory to thoroughly check out the operation of the
ADC1241. Care should be taken not to inadvertently be in
this mode, since DB2, DB3, DB5, and DB6 become active
outputs, which may cause data bus contention.
3.0 Analog Considerations
3.1 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
between V and AGND), over which 4095 positive output
IN
codes and 4096 negative output codes exist. The A-to-D
can be used in either ratiometric or absolute reference ap-
2.2 RESETTING THE A/D
plications. The voltage source driving V
must have a
REF
All internal logic can be reset, which will abort any conver-
sion in process. The A/D is reset whenever a new conver-
sion is started by taking CS and WR low. If this is done when
the analog input is being sampled or when EOC is low, the
Auto-Cal correction factors may be corrupted, therefore
making it necessary to do an Auto-Cal cycle before the next
conversion. This is true with or without Auto-Zero. The Cali-
bration Cycle cannot be reset once started. On power-up
the ADC1241 automatically goes through a Calibration Cy-
cle that takes typically 1396 clock cycles.
very low output impedance and very low noise. The circuit in
Figure 2 is an example of a very stable reference that is
appropriate for use with the ADC1241.
In a ratiometric system, the analog input voltage is propor-
tional to the voltage used for the A/D reference. When this
voltage is the system power supply, the V
REF
pin can be
tied to V . This technique relaxes the stability requirement
CC
of the system reference as the analog input and A/D refer-
ence move together maintaining the same output code for
given input condition.
TL/H/10554–17
*Tantalum
FIGURE 2. Low Drift Extremely Stable Reference Circuit
11
3.0 Analog Considerations (Continued)
TL/H/10554–18
FIGURE 3. Analog Input Equivalent Circuit
For absolute accuracy, where the analog input varies be-
tween very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will re-
quire an initial adjustment to null out full-scale errors.
ductance tantalum capacitors of 10 mF or greater paralleled
with 0.1 mF ceramic capacitors are recommended for supply
bypassing. Separate bypass capacitors whould be placed
close to the DV , AV
CC
voltage source is available in the system,
and Vb pins. If an unregulated
CC
a
separate
(and
LM340LAZ-5.0 voltage regulator for the A-to-D’s V
CC
3.2 INPUT CURRENT
other analog circuitry) will greatly reduce digital noise on the
supply line.
A charging current will flow into or out of (depending on the
input voltage polarity) of the analog input pin (V ) on the
IN
start of the analog input sampling period (t ). The peak val-
A
3.7 THE CALIBRATION CYCLE
ue of this current will depend on the actual input voltage
applied.
On power up the ADC1241 goes through an Auto-Cal cycle
which cannot be interrupted. Since the power supply, refer-
ence, and clock will not be stable at power up, this first
calibration cycle will not result in an accurate calibration of
the A/D. A new calibration cycle needs to be started after
the power supplies, reference, and clock have been given
enough time to stabilize. During the calibration cycle, cor-
rection values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall gain, offset,
and linearity errors down to the specified limits. It should be
necessary to go through the calibration cycle only once af-
ter power up.
3.3 INPUT BYPASS CAPACITORS
An external capacitor can be used to filter out any noise due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result.
3.4 INPUT SOURCE RESISTANCE
The analog input can be modeled as shown in Figure 3.
External R will lengthen the time period necessary for the
S
voltage on C
REF
to settle to within (/2 LSB of the analog
e
e
e
input voltage. With f
s
settle properly.
2 MHz t
7 clock periods
1 kX will allow a 5V analog input voltage to
CLK
A
3.5 ms, R
S
3.8 THE AUTO-ZERO CYCLE
3.5 NOISE
To correct for any change in the zero (offset) error of the
A/D, the auto-zero cycle can be used. It may be necessary
to do an auto-zero cycle whenever the ambient temperature
changes significantly. (See the curved titled ‘‘Zero Error
Change vs Ambient Temperature’’ in the Typical Perform-
ance Characteristics.) A change in the ambient temperature
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to this input can cause er-
rors. Input filtering can be used to reduce the effects of
these noise sources.
will cause the V
of the sampled data comparator to
3.6 POWER SUPPLIES
OS
change, which may cause the zero error of the A/D to be
Noise spikes on the V
and Vb supply lines can cause
CC
g
greater than 1 LSB. An auto-zero cycle will maintain the
conversion errors as the comparator will respond to this
noise. The A/D is especially sensitive during the auto-zero
or auto-cal procedures to any power supply spikes. Low in
g
zero error to 1 LSB or less.
12
4.0 Dynamic Performance
Power Supply Bypassing
Many applications require the A/D converter to digitize ac
signals, but the standard dc integral and differential nonlin-
earity specifications will not accurately predict the A/D con-
verter’s performance with ac input signals. The important
specifications for ac applications reflect the converter’s abil-
ity to digitize ac signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
a
characteristics such as signal-to-noise distortion ratio
(S/(N D)), effective bits, full power bandwidth, aperture
a
time and aperture jitter are quantitative measures of the
A/D converter’s capability.
An A/D converter’s ac performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave-
form is applied to the A/D converter’s input, and the trans-
a
form is then performed on the digitized waveform. S/(N D)
is calculated from the resulting FFT data, and a spectral plot
TL/H/10554–19
*Tantalum
a
may also be obtained. Typical values for S/(N D) are
shown in the table of Electrical Characteristics, and spectral
plots are included in the typical performance curves.
Protecting the Analog Inputs
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can
a
be seen in the S/(N D) versus frequency curves. These
curves will also give an indication of the full power band-
a
width (the frequency at which the S/(N D) drops 3 dB).
Two sample/hold specifications, aperture time and aperture
jitter, are included in the Dynamic Characteristics table
since the ADC1241 has the ability to track and hold the
analog input voltage. Aperture time is the delay for the A/D
to respond to the hold command. In the case of the
ADC1241, the hold command is internally generated. When
the Auto-Zero function is not being used, the hold command
occurs at the end of the acquisition window, or seven clock
periods after the rising edge of the WR. The delay between
the internally generated hold command and the time that
the ADC1241 actually holds the input signal is the aperture
time. For the ADC1241, this time is typically 100 ns. Aper-
ture jitter is the change in the aperture time from sample to
sample. Aperture jitter is useful in determining the maximum
slew rate of the input signal for a given accuracy. For exam-
ple, an ADC1241 with 100 ps of aperture jitter operating with
a 5V reference can have an effective gain variation of about
1 LSB with an input signal whose slew rate is 12 V/ms.
TL/H/10554–20
13
Physical Dimensions inches (millimeters)
Order Number ADC1241CMJ, ADC1241CMJ/883, ADC1241BIJ or ADC1241CIJ
NS Package Number J28A
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