ADC10064CMJ-QML [NSC]
IC,DATA ACQ SYSTEM,1-CHANNEL,10-BIT,DIP,24PIN,CERAMIC;
| 型号： | ADC10064CMJ-QML |
| 厂家： | 
National Semiconductor |
| 描述： | IC,DATA ACQ SYSTEM,1-CHANNEL,10-BIT,DIP,24PIN,CERAMIC 转换器 复用器 |
| 文件： | 总14页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
ADC10061/ADC10062/ADC10064
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Features
n Built-in sample-and-hold
*
Using an innovative, patented multistep conversion tech-
nique, the 10-bit ADC10061, ADC10062, and ADC10064
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
n Single +5V supply
n 1, 2, or 4-input multiplexer options
n No external clock required
n Speed adjust pin for faster conversions (ADC10062
and ADC10064). See ADC10662/4 for high speed
guaranteed performance.
The ADC10061, ADC10062, and ADC10064 perform
a
10-bit conversion in two lower-resolution “flashes”, thus
yielding a fast A/D without the cost, power dissipation, and
other problems associated with true flash approaches. The
ADC10061 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
Key Specifications
n Conversion time to 10 bits
n
600 ns typical,
900 ns max over temperature
800 kHz
The analog input voltage to the ADC10061, ADC10062, and
ADC10064 is sampled and held by an internal sampling cir-
cuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
n Sampling Rate
n Low power dissipation
n Total unadjusted error
n No missing codes over temperature
235 mW (max)
1.0 LSB (max)
±
The ADC10062 and ADC10064 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
Applications
n Digital signal processor front ends
n Instrumentation
For ease of interface to microprocessors, the ADC10061,
ADC10062, and ADC10064 have been designed to appear
as a memory location or I/O port without the need for exter-
nal interface logic.
n Disk drives
n Mobile telecommunications
*
U.S. Patent Number 4918449
Simplified Block Diagram
DS011020-1
*
ADC10061 Only
**
ADC10062 and ADC10064 Only
***
ADC10064 Only
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS011020
www.national.com
Ordering Information
Industrial (−40˚C ≤ TA ≤ +85˚C)
Package
ADC10061CIWM
ADC10062CIWM
ADC10064CIWM
M20B Small Outline
M24B Small Outline
M28B Small Outline
Connection Diagrams
DS011020-11
Top View
DS011020-12
Top View
DS011020-13
Top View
www.national.com
2
Pin Descriptions
DVCC, AVCC These are the digital and analog positive sup-
ply voltage inputs. They should always be con-
nected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor to
ground.
V
IN, VIN0
,
These are the analog input pins. The
ADC10061 has one input (VIN), the ADC10062
has two inputs (VIN0 and VIN1), and the
ADC10064 has four inputs (VIN0, VIN1, VIN2
and VIN3). The impedance of the source
should be less than 500Ω for best accuracy
and conversion speed. For accurate conver-
sions, no input pin (even one that is not se-
lected) should be driven more than 50 mV
above VCC or 50 mV below ground.
VIN1, VIN2
,
VIN3
INT
S/H
RD
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD.
GND, AGND, These are the power supply ground pins. The
DGND
ADC10061 has a single ground pin (GND),
and the ADC10062 and ADC10064 have
separate analog and digital ground pins
(AGND and DGND) for separate bypassing of
the analog and digital supplies. The ground
This is the Sample/Hold control input. When
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and ini-
tiates a new conversion.
pins should be connected to
a stable,
This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
noise-free system ground. For the devices
with two ground pins, both pins should be re-
turned to the same potential.
DB0–DB9
These are the TRI-STATE® output pins.
CS
This is the active low Chip Select control input.
When low, this pin enables the RD and S/H
pins.
SPEED ADJ (ADC10062 and ADC10064 only). This pin is
normally left unconnected, but by connecting a
resistor between this pin and ground, the con-
version time can be reduced. See the Typical
Performance Curves and the table of Electri-
cal Characteristics.
S0, S1
On the multiple-input devices (ADC10062 and
ADC10064), these pins select the analog input
that will be connected to the A/D during the
conversion. The input is selected based on the
state of S0 and S1 when S/H makes its
High-to-Low transition (See the Timing Dia-
grams). The ADC10064 includes both S0 and
S1. The ADC10062 includes just S0, and the
ADC10061 includes neither.
VREF−
VREF+
,
These are the reference voltage inputs. They
may be placed at any voltage between GND
and VCC, but VREF+ must be greater than
V
REF−. An input voltage equal to VREF− pro-
duces an output code of 0, and an input volt-
age equal to (VREF+ − 1 LSB) produces an out-
put code of 1023.
3
www.national.com
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
Junction Temperature
−65˚C to +150˚C
150˚C
Operating Ratings (Notes 1, 2)
Supply Voltage (V+ AVCC DVCC
Voltage at Any Input or Output
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
)
−0.3V to +6V
−0.3V to V+ + 0.3V
5 mA
=
=
Temperature Range
TMIN ≤ TA ≤ TMAX
ADC10061CIWM,
ADC10062CIWM,
ADC10064CIWM
−40˚C ≤ TA ≤ +85˚C
20 mA
Supply Voltage Range
4.5V to 5.5V
875 mW
ESD Susceptability (Note 5)
2000V
Soldering Information (Note 6)
Vapor Phase (60 Sec)
Infrared (15 Sec)
215˚C
220˚C
Converter Characteristics
The following specifications apply for V+ +5V, VREF(+) +5V, VREF(−) GND, and Speed Adjust pin unconnected unless
=
=
=
=
=
=
=
otherwise specified. Boldface limits apply for TA TJ TMin to TMax; all other limits TA TJ +25˚C.
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
Symbol
Parameter
Conditions
Resolution
10
Bits
=
±
±
±
±
±
Integral Linearity Error
Offset Error
RSA 18 kΩ
0.5
0.5
1.0/ 1.5
LSB (max)
LSB (max)
LSB (max)
LSB (max)
(max)
±
±
1
1
Full-Scale Error
=
±
Total Unadjusted Error
Missing Codes
All Suffixes, RSA 18 kΩ
1.5/ 2.0
0
V+ 5V 5%, VREF 4.5V
LSB
LSB (max)
=
=
=
=
±
±
±
1/16
Power Supply Sensitivity
V+ 5V 10%, VREF 4.5V
⁄
8
3
±
=
=
THD
SNR
Total Harmonic Distortion
Signal-to-Noise Ratio
fIN 10 kHz, 4.85 VP-P
0.06
0.08
%
%
fIN 160 kHz, 4.85 VP-P
=
fIN 10 kHz, 4.85 VP-P
61
60
dB
dB
=
fIN 160 kHz, 4.85 VP-P
=
=
Effective Number of Bits
fIN 10 kHz, 4.85 VP-P
9.6
9.4
Bits
Bits
fIN 160 kHz, 4.85 VP-P
RREF
Reference Resistance
Reference Resistance
VREF(+) Input Voltage
VREF(−) Input Voltage
VREF(+) Input Voltage
VREF(−) Input Voltage
Input Voltage
650
650
400
900
V+ + 0.05
GND − 0.05
VREF(−)
Ω (min)
Ω (max)
V (max)
V (min)
V (min)
V (max)
V (max)
V (min)
RREF
VREF(+)
VREF(−)
VREF(+)
VREF(−)
VIN
VREF(+)
V+ + 0.05
VIN
Input Voltage
GND − 0.05
+
+
+
=
=
=
=
OFF Channel Input Leakage Current
ON Channel Input Leakage Current
CS V , VIN
+
V
V
0.01
3
−3
µA (max)
µA (max)
±
CS V , VIN
1
DC Electrical Characteristics
The following specifications apply for V+ +5V, VREF(+) 5V VREF(−) GND, and Speed Adjust pin unconnected unless other-
=
=
=
=
=
=
=
wise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ +25˚C.
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
Symbol
Parameter
Conditions
VIN(1)
VIN(0)
IIN(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Logical “1” Output Voltage
V+ 5.5V
=
2.0
0.8
V (min)
V (max)
µA (max)
µA (max)
V+ 4.5V
=
=
VIN(1) 5V
0.005
3.0
IIN(0)
VIN(0) 0V
=
−0.005
−3.0
V+ 4.5V, IOUT −360 µA
2.4
4.25
V (min)
V (min)
=
=
VOUT(1)
V+ 4.5V, IOUT −10 µA
=
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4
DC Electrical Characteristics (Continued)
The following specifications apply for V+ +5V, VREF(+) 5V VREF(−) GND, and Speed Adjust pin unconnected unless other-
=
=
=
=
=
=
=
wise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ +25˚C.
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
Symbol
Parameter
Conditions
=
=
VOUT(0)
IOUT
Logical “0” Output Voltage
TRI-STATE® Output Current
V+ 4.5V, IOUT 1.6 mA
0.4
V (max)
=
=
VOUT 5V
VOUT 0V
0.1
−0.1
50
−50
µA (max)
µA (max)
=
=
=
=
=
=
= ∞
=
DICC
AICC
DVCC Supply Current
AVCC Supply Current
CS S/H RD 0, RSA
1.0
1.0
mA (max)
mA (max)
2
CS S/H RD 0, RSA 18 kΩ
=
=
=
=
=
= ∞
=
CS S/H RD 0, RSA
30
30
mA (max)
mA (max)
45
=
CS S/H RD 0, RSA 18 kΩ
AC Electrical Characteristics
The following specifications apply for V+ +5V, tr tf 20 ns, VREF(+) 5V, VREF(−) GND, and Speed Adjust pin uncon-
=
=
=
=
=
=
=
=
=
nected unless otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ +25˚C.
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
Symbol
Parameter
Conditions
= ∞
tCONV
Mode 1 Conversion Time from
Rising Edge of S/H to Falling Edge
of INT
RSA
600
375
750/900
ns(max)
ns
=
RSA 18k
= ∞
tCRD
tACC1
tACC2
tSH
Mode 2 Conversion Time
RSA
850
530
1400
60
ns(max)
ns
=
Mode 2, RSA 18k
=
Mode 1; CL 100 pF
Access Time (Delay from Falling
Edge of RD to Output Valid)
30
ns (max)
=
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode 2; CL 100 pF
900
tCRD + 50
250
ns (max)
ns (max)
ns (max)
Minimum Sample Time
(Figure 1); (Note 8)
= =
RL 1k, CL 10 pF
t
1H, t0H
tINTH
tP
TRI-STATE Control (Delay from
Rising Edge of RD to High-Z State)
30
25
60
=
CL 100 pF
Delay from Rising Edge of RD to
Rising Edge of INT
50
50
ns (max)
ns (max)
Delay from End of Conversion to
Next Conversion
tMS
Multiplexer Control Setup Time
Multiplexer Hold Time
10
10
35
5
75
40
ns (max)
ns (max)
pF (max)
pF (max)
pF (max)
tMH
CVIN
COUT
CIN
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
5
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditons.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
+
<
>
IN
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
GND or V
V ) the absolute value of current at that pin should be limited
IN
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T , θ and the ambient temperature, T . The maximum
JMAX JA
A
=
allowable power dissipation at any temperature is P
(T
JMAX
− T )/θ or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
D
A
JA
the maximum derated power dissipation will be reached only during fault conditions. For these devices, T
tables below:
for a board-mounted device can be found from the
JMAX
Device
θJA (˚C/W)
ADC10061CIWM
ADC10062CIWM
54
48
44
ADC10064CIWM
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at +25˚C and represent must likely parametric norm.
5
www.national.com
AC Electrical Characteristics (Continued)
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if t is shorter than the value specified. See curves of Accuracy vs t
.
SH
SH
Typical Performance Characteristics
Zero (Offset) Error
vs Reference Voltage
Linearity Error
vs Reference Voltage
Analog Supply Current
vs Temperature
DS011020-16
DS011020-17
DS011020-18
Digital Supply Current
vs Temperature
Conversion Time
vs Temperature
Conversion Time
vs Temperature
DS011020-19
DS011020-20
DS011020-21
Conversion Time
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
Conversion Time
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
Spectral Response
with100 kHz Sine
Wave Input
DS011020-22
DS011020-23
DS011020-24
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6
Typical Performance Characteristics (Continued)
Spectral Response with
100 kHz Sine Wave Input
Signal-to-Noise + THD Ratio
vs Signal Frequency
Linearity Change
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
DS011020-25
DS011020-26
DS011020-27
Linearity Change
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
Linearity Error Change
vs Sample Time
DS011020-29
DS011020-28
TRI-STATE Test Circuits and Waveforms
DS011020-6
DS011020-5
DS011020-8
DS011020-7
7
www.national.com
Timing Diagrams
DS011020-9
FIGURE 1. Mode 1. The conversion time (tCONV) is set by the internal timer.
DS011020-10
FIGURE 2. Mode 2 (RD Mode). The conversion time (tCRD) includes the
sampling time and is determined by the internal timer.
Functional Description
The ADC10061, ADC10062 and ADC10064 digitize an ana-
log input signal to 10 bits accuracy by performing two
lower-resolution “flash” conversions. The first flash conver-
sion provides the six most significant bits (MSBs) of data,
and the second flash conversion provides the four least sig-
nificant bits LSBs).
has a value 1/1024 the resistance of the whole resistor
string. These lower 16 resistors (the LSB Ladder ) therefore
have a voltage drop of 16/1024, or 1/64 of the total reference
voltage (VREF+ − VREF−) across them. The remainder of the
resistor string is made up of eight groups of eight resistors
connected in series. These comprise the MSB Ladder. Each
section of the MSB Ladder has 1
age across it, and each of the LSB resistors has 1/64 of the
⁄
8
of the total reference volt-
Figure 3 is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the bot-
tom of the string of resistors are 16 resistors, each of which
www.national.com
8
form the first flash conversion. Note that since the compara-
tors are connected to ladder voltages that extend beyond the
range indicated by the estimator circuit, errors in the estima-
tor as large as 1/16 of the reference voltage (64 LSBs) will
be corrected. This first flash conversion produces the six
most significant bits of data — four bits in the flash itself, and
2 bits in the estimator.
Functional Description (Continued)
total reference voltage across it. Tap points across these re-
sistors can be connected, in groups of sixteen, to the sixteen
comparators at the right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between VREF+ and VREF−. Six comparators com-
pare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input volt-
age. This estimate is then used to control the multiplexer that
connects the MSB Ladder to the sixteen comparators on the
right. Note that the comparators on the left needn’t be very
accurate; they simply provide an estimate of the input volt-
age. Only the sixteen comparators on the right and the six on
the left are necessary to perform the initial six-bit flash con-
version, instead of the 64 comparators that would be re-
quired using conventional half-flash methods.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash con-
version are reused for the second flash. Thus, the multistep
conversion technique used in the ADC10061, ADC10062,
and ADC10064 needs only a small fraction of the number of
comparators that would be required for a traditional flash
converter, and far fewer than would be used in a conven-
tional half-flash approach. This allows the ADC10061,
ADC10062, and ADC10064 to perform high-speed conver-
sions without excessive power drain.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB Lad-
der tap points will be connected to the sixteen comparators
on the right. For example, assume that the estimator deter-
mines that VIN is between 11/16 and 13/16 of VREF. The es-
timator decoder will instruct the comparator MUX to connect
the 16 comparators to the taps on the MSB ladder between
10/16 and 14/16 of VREF. The 16 comparators will then per-
DS011020-14
FIGURE 3. Block Diagram of the Multistep Converter Architecture
Applications Information
1.0 MODES OF OPERATION
have input multiplexers that are controlled by the logic levels
on pins S0 and S1 when S/H goes low. Table 1 is a truth table
showing how the input channnels are assigned.
The ADC10061, ADC10062, and ADC10064 have two basic
digital interface modes. Figure 1 and Figure 2 are timing dia-
grams for the two modes. The ADC10062 and ADC10064
9
www.national.com
however, that linearity and offset errors become larger when
lower reference voltages are used. See the Typical Perfor-
mance Curves for more information. For this reason, refer-
ence voltages less than 2V are not recommended.
Applications Information (Continued)
Mode 1
In this mode, the S/H pin controls the start of conversion. S/H
is pulled low for a minimum of 250 ns. This causes the com-
parators in the “coarse” flash converter to become active.
When S/H goes high, the result of the coarse conversion is
latched and the “fine” conversion begins. After 600 ns (typi-
cal), INT goes low, indicating that the conversion results are
latched and can be read by pulling RD low. Note that CS
must be low to enable S/H or RD. CS is internally “ANDed”
with S/H and RD; the input voltage is sampled when CS and
S/H are low, and data is read when CS and RD are low. INT
is reset high on the rising edge of RD.
In most applications, VREF− will simply be connected to
ground, but it is often useful to have an input span that is off-
set from ground. This situation is easily accommodated by
the reference configuration used in the ADC10061,
ADC10062, and ADC10064. VREF− can be connected to a
voltage other than ground as long as the voltage source con-
nected to this pin is capable of sinking the converter’s refer-
=
ence current (12.5 mA Max @ VREF 5V). If VREF− is con-
nected to a voltage other than ground, bypass it with multiple
capacitors.
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on ei-
ther reference input is a potential cause of conversion errors,
so each of these pins must be supplied with a clean, low
noise voltage source. Each reference pin should be by-
passed with a 10 µF tantalum and a 0.1 µF ceramic.
TABLE 1. Input Multiplexer Programming
ADC10064 (a)
S1
0
S0
0
Channel
VIN0
0
1
VIN1
3.0 THE ANALOG INPUT
1
0
VIN2
The ADC10061, ADC10062, and ADC10064 sample the
analog input voltage once every conversion cycle. When this
happens, the input is briefly connected to an impedance ap-
proximately equal to 600Ω in series with 35 pF.
Short-duration current spikes can therefore be observed at
the analog input during normal operation. These spikes are
normal and do not degrade the converter’s performance.
1
1
VIN3
ADC10062 (b)
S0
0
Channel
VIN0
VIN1
1
Large source impedances can slow the charging of the sam-
pling capacitors and degrade conversion accuracy. There-
fore, only signal sources with output impedances less than
500Ω should be used if rated accuracy is to be achieved at
the minimum sample time (250 ns maximum). If the sam-
pling time is increased, the source impedance can be larger.
If a signal source has a high output impedance, its output
should be buffered with an operational amplifier. The opera-
tional amplifier’s output should be well-behaved when driving
a switched 35 pF/600Ω load. Any ringing or voltage shifts at
the op amp’s output during the sampling period can result in
conversion errors.
Mode 2
In Mode 2, also called “RD mode”, the S/H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An inter-
nal timer then terminates the coarse conversion and begins
the fine conversion. 850 ns (typical) after S/H and RD are
pull low, INT goes low, indicating that the conversion is com-
pleted. Approximately 20 ns later the data appearing on the
TRI-STATE output pins will be valid. Note that data will ap-
pear on these pins throughout the conversion, but until INT
goes low the data at the output pins will be the result of the
previous conversion.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V+ + 50 mV. Do not
allow the signal source to drive the analog input pin more
than 300 mV higher than AVCC and DVCC, or more than
300 mV lower than GND. If an analog input pin is forced be-
yond these voltages, the current flowing through the pin
should be limited to 5 mA or less to avoid permanent dam-
age to the IC. The sum of all the overdrive currents into all
pins must be less than 20 mA. When the input signal is ex-
pected to extend more than 300 mV beyond the power sup-
ply limits, some sort of protection scheme should be used. A
simple network using diodes and resistors is shown in
Figure 4.
2.0 REFERENCE CONSIDERATIONS
The ADC10061, ADC10062, and ADC10064 each have two
reference inputs. These inputs, VREF+ and VREF−, are fully
differential and define the zero to full-scale range of the input
signal. The reference inputs can be connected to span the
entire supply voltage range (VREF− 0V, VREF+ VCC) for
ratiometric applications, or they can be connected to differ-
ent voltages (as long as they are between ground and VCC
when other input spans are required. Reducing the overall
VREF span to less than 5V increases the sensitivity of the
converter (e.g., if VREF 2V, then 1 LSB 1.953 mV). Note,
=
=
)
=
=
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10
Applications Information (Continued)
DS011020-15
FIGURE 4. Typical Connection. Note the multiple bypass capacitors on the reference and power supply pins. If VREF−
is not grounded, it should also be bypassed to analog ground using multiple capacitors (see 5.0 “Power Supply
Considerations”). AGND and DGND should be at the same potential. VIN0 is shown with an input protection network.
Pin 17 is normally left open, but optional “speedup” resistor RSA can be used to reduce the conversion time.
4.0 INHERENT SAMPLE-AND-HOLD
supplies. The devices with separate analog and digital
ground pins should have their ground pins connected to the
same potential, and all grounds should be “clean” and free of
noise.
Because the ADC10061, ADC10062, and ADC10064
sample the input signal once during each conversion, they
are capable of measuring relatively fast input signals without
the help of an external sample-hold. In a non-sampling
successive-approximation A/D converter, regardless of
In systems with multiple power supplies, careful attention to
power supply sequencing may be necessary to avoid over-
driving inputs. The A/D converter’s power supply pins should
be at the proper voltage before digital or analog signals are
applied to any of the other pins.
±
speed, the input signal must be stable to better than 1/2
LSB during each conversion cycle or significant errors will
result. Consequently, even for many relatively slow input sig-
nals, the signals must be externally sampled and held con-
stant during each conversion if a SAR with no internal
sample-and-hold is used.
6.0 LAYOUT AND GROUNDING
In order to ensure fast, accurate conversions from the
ADC10061, ADC10062, and ADC10064, it is necessary to
use appropriate circuit board layout techniques. The analog
ground return path should be low-impedance and free of
noise from other parts of the system. Noise from digital cir-
cuitry can be especially troublesome, so digital grounds
should always be separate from analog grounds. For best
performance, separate ground planes should be provided for
the digital and analog parts of the system.
Because they incorporate a direct sample/hold control input,
the ADC10061, ADC10062, and ADC10064 are suitable for
use in DSP-based systems. The S/H input allows synchroni-
zation of the A/D converter to the DSP system’s sampling
rate and to other ADC10061s, ADC10062s, and
ADC10064s.
The ADC10061, ADC10062, and ADC10064 can perform ac-
curate conversions of input signals with frequency compo-
nents from DC to over 160 kHz.
All bypass capacitors should be located as close to the con-
verter as possible and should connect to the converter and
to ground with short traces. The analog input should be iso-
lated from noisy signal traces to avoid having spurious sig-
nals couple to the input. Any external component (e.g., a fil-
ter capacitor) connected across the converter’s input should
be connected to a very clean ground return point. Grounding
the component at the wrong point will result in reduced con-
version accuracy.
5.0 POWER SUPPLY CONSIDERATIONS
The ADC10061, ADC10062, and ADC10064 are designed to
operate from a +5V (nominal) power supply. There are two
supply pins, AVCC and DVCC. These pins allow separate ex-
ternal bypass capacitors for the analog and digital portions of
the circuit. To guarantee accurate conversions, the two sup-
ply pins should be connected to the same voltage source,
and each should be bypassed with a 0.1 µF ceramic capaci-
tor in parallel with a 10 µF tantalum capacitor. Depending on
the circuit board layout and other system considerations,
more bypassing may be necessary.
7.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but conventional DC integral and differential nonlin-
earity specifications don’t accurately predict the A/D convert-
er’s performance with AC input signals. The important speci-
fications for AC applications reflect the converter’s ability to
The ADC10061 has a single ground pin, and the ADC10062
and ADC10064 each have separate analog and digital
ground pins for separate bypassing of the analog and digital
11
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(6.02n + 1.76) dB, where n is the resolution in bits of the A/D
converter. A real A/D converter will have some amount of
noise and distortion, and the effective bits can be found by:
Applications Information (Continued)
digitize AC signals without significant spectral errors and
without adding noise to the digitized signal. Dynamic charac-
teristics such as signal-to-noise ratio (SNR) and total har-
monic distortion (THD), are quantitative measures of this ca-
pability.
where S/(N + D) is the ratio of signal to noise and distortion,
which can vary with frequency.
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave-
form is applied to the A/D converter’s input, and the trans-
form is then performed on the digitized waveform. The re-
sulting spectral plot might look like the ones shown in the
typical performance curves. The large peak is the fundamen-
tal frequency, and the noise and distortion components (if
any are present) are visible above and below the fundamen-
tal frequency. Harmonic distortion components appear at
whole multiples of the input frequency. Their amplitudes are
combined as the square root of the sum of the squares and
compared to the fundamental amplitude to yield the THD
specification. Typical values for THD are given in the table of
Electrical Characteristics.
As an example, an ADC10061 with a 5 VP-P, 100 kHz sine
wave
input
signal
will
typically
have
a
signal-to-noise-plus-distortion ratio of 59.2 dB, which is
equivalent to 9.54 effective bits. As the input frequency in-
creases, noise and distortion gradually increase, yielding a
plot of effective bits or S/(N + D) as shown in the typical per-
formance curves.
8.0 SPEED ADJUST
In applications that require faster conversion times, the
Speed Adjust pin (pin 14 on the ADC10062, pin 17 on the
ADC10064) can significantly reduce the conversion time.
The speed adjust pin is connected to an on-chip current
source that determines the converter’s internal timing. By
connecting a resistor between the speed adjust pin and
ground as shown in Figure 4, the internal programming cur-
rent is increased, which reduces the conversion time. As an
example, an 18k resistor reduces the conversion time of a
typical part from 600 ns to 350 ns with no significant effect on
linearity. Using smaller resistors to further decrease the con-
version time is possible as well, although the linearity will be-
gin to degrade somewhat (see curves). Note that the resistor
value needed to obtain a given conversion time will vary from
part to part, so this technique will generally require some
“tweaking” to obtain satisfactory results.
Signal-to-noise ratio is the ratio of the amplitude at the fun-
damental frequency to the rms value at all other frequencies,
excluding any harmonic distortion components. Typical val-
ues are given in the Electrical Characteristics table. An alter-
native definition of signal-to-noise ratio includes the distor-
tion components along with the random noise to yield a
signal-to-noise-plus-distortion ratio, or S/(N + D).
The THD and noise performance of the A/D converter will
change with the frequency of the input signal, with more dis-
tortion and noise occurring at higher signal frequencies. One
way of describing the A/D’s performance as a function of sig-
nal frequency is to make a plot of “effective bits” versus fre-
quency. An ideal A/D converter with no linearity errors or
self-generated noise will have a signal-to-noise ratio equal to
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12
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC10061CIWM
NS Package Number M20B
Order Number ADC10062CIWM
NS Package Number M24B
13
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number ADC10064CIWM
NS Package Number M28B
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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Tel: 1-800-272-9959
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相关型号：
ADC10065CIMT/NOPB
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, TSSOP-28, Analog to Digital Converter
NSC
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