ADC10065CIMTX [NSC]
ADC10065 10-Bit 65 MSPS 3V A/D Converter; ADC10065 10位65 MSPS 3V A / D转换器
| 型号： | ADC10065CIMTX |
| 厂家： | 
National Semiconductor |
| 描述： | ADC10065 10-Bit 65 MSPS 3V A/D Converter |
| 文件： | 总19页 (文件大小：942K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2005
ADC10065
10-Bit 65 MSPS 3V A/D Converter
General Description
Features
n Single +3.0V operation
The ADC10065 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 10-bit
digital words at 65 Megasamples per second (MSPS). This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
provide a complete conversion solution, and to minimize
power consumption, while providing excellent dynamic per-
formance. A unique sample-and-hold stage yields a full-
power bandwidth of 400 MHz. Operating on a single 3.0V
power supply, this device consumes just 68.4 mW at
65 MSPS, including the reference current. The Standby
feature reduces power consumption to just 14 .1 mW.
n Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input
swing
n 400 MHz −3 dB input bandwidth
n Low power consumption
n Standby mode
n On-chip reference and sample-and-hold amplifier
n Offset binary or two’s complement data format
n Separate adjustable output driver supply to
accommodate 2.5V and 3.3V logic families
n 28-pin TSSOP package
The differential inputs provide a full scale selectable input
swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a
single-ended input. Full use of the differential input is recom-
mended for optimum performance. An internal +1.2V preci-
sion bandgap reference is used to set the ADC full-scale
range, and also allows the user to supply a buffered refer-
enced voltage for those applications requiring increased ac-
curacy. The output data format is 10-bit offset binary, or two’s
complement.
Key Specifications
n Resolution
10 Bits
65 MSPS
400 MHz
n Conversion Rate
n Full Power Bandwidth
n DNL
n SNR (fIN = 11 MHz)
n SFDR (fIN = 11 MHz)
n Data Latency
0.3 LSB (typ)
59.6 dB (typ)
−80 dB (typ)
6 Clock Cycles
+3.0V
This device is available in the 28-lead TSSOP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
n Supply Voltage
n Power Consumption, 65 MHz
68.4 mW
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Based Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
20077901
© 2005 National Semiconductor Corporation
DS200779
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Ordering Information
Industrial (−40˚C ≤ TA ≤ +85˚C)
NS Package
28 Pin TSSOP
ADC10065CIMT
ADC10065CIMTX
28 Pin TSSOP Tape & Reel
Block Diagram
20077902
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2
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
Inverting analog input signal. With a 1.2V reference the
full-scale input signal level is 1.0 VP-P. This pin may be tied to
VCOM (pin 4) for single-ended operation.
−
12
13
VIN
Non-inverting analog input signal. With a 1.2V reference the
+
VIN
full-scale input signal level is 1.0 VP-P
.
Reference input. This pin should be bypassed to VSSA with a
0.1 µF monolithic capacitor. VREF is 1.20V nominal. This pin
may be driven by a 1.20V external reference if desired.
6
VREF
7
4
8
VREFT
VCOM
VREFB
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to VSSA
These pins should not be loaded. VCOM may be used to set
.
the input common voltage VCM
.
DIGITAL I/O
Digital clock input. The range of frequencies for this input is
1
CLK
DF
20 MHz to 65 MHz. The input is sampled on the rising edge
of this input.
DF = “1” Two’s Complement
15
28
DF = “0” Offset Binary
This is the standby pin. When high, this pin sets the converter
into standby mode. When this pin is low, the converter is in
active mode.
STBY
IRS = “VDDA” 2.0 VP-P input range
IRS = “VSSA” 1.5 VP-P input range
IRS (Input Range
Select)
IRS = “Floating” 1.0 VP-P input range
If using both VIN+ and VIN- pins, (or differential mode), then
the peak-to-peak voltage refers to the differential voltage
(VIN+ - VIN-).
5
3
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No.
Symbol
Equivalent Circuit
Description
16–20,
23–27
Digital output data. D0 is the LSB and D9 is the MSB of the
binary output word.
D0–D9
ANALOG POWER
Positive analog supply pins. These pins should be connected
to a quiet 3.0V source and bypassed to analog ground with a
0.1 µF monolithic capacitor located within 1 cm of these pins.
A 4.7 µF capacitor should also be used in parallel.
Ground return for the analog supply.
2, 9, 10
VDDA
3, 11, 14
VSSA
DIGITAL POWER
Positive digital supply pins for the ADC10065’s output drivers.
This pin should be bypassed to digital ground with a 0.1 µF
monolithic capacitor located within 1 cm of this pin. A 4.7 µF
capacitor should also be used in parallel. The voltage on this
pin should never exceed the voltage on VDDA by more than
300 mV.
22
21
VDDIO
The ground return for the digital supply for the output drivers.
This pin should be connected to the digital ground, but not
near the analog ground.
VSSIO
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4
Absolute Maximum Ratings (Notes 1,
Operating Ratings
2)
Operating Temperature Range
VDDA (Supply Voltage)
VDDIO (Output Driver Supply
Voltage)
−40˚C ≤ TA ≤ +85˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+2.7V to +3.6V
+2.5V to VDDA
1.20V
VDDA, VDDIO
3.9V
−0.3V to VDDA or
VDDIO +0.3V
25 mA
VREF
Voltage on Any Pin to GND
|VSSA–VSSIO
|
≤ 100 mV
30 to 70 %
Clock Duty Cycle
Input Current on Any Pin
Package Input Current (Note 3)
Package Dissipation at T = 25˚C
ESD Susceptibility
NOTE: Absolute maximum ratings are limiting values, to be applied individu-
ally, and beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not necessarily im-
plied. Exposure to maximum ratings for extended periods may affect device
reliability.
50 mA
See (Note 4)
Human Body Model (Note 5)
Machine Model (Note 5)
Soldering Temperature
2500V
250V
Infrared, 10 sec. (Note 6)
Storage Temperature
235˚C
−65˚C to +150˚C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V,
VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (External Supply) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits
apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STATIC CONVERTER CHARACTERISTICS
No Missing Codes Guaranteed
10
Bits
FIN = 500 kHz, −0 dB Full
Scale
INL
Integral Non-Linearity (Note 12)
Differential Non-Linearity
Gain Error
−1.0
0.3
0.3
+1.1
+0.9
LSB
FIN = 500 kHz, −0 dB Full
Scale
DNL
−0.9
LSB
Positive Error
−1.5
−1.5
−1.4
+0.4
+0.03
0.2
+1.9
+1.9
+1.7
% FS
% FS
% FS
GE
OE
Negative Error
Offset Error (VIN+ = VIN−)
Under Range Output Code
Over Range Output Code
Full Power Bandwidth
0
1023
400
FPBW
MHz
REFERENCE AND INPUT CHARACTERISTICS
VCM
Common Mode Input Voltage
Output Voltage for use as an input
common mode voltage (Note 17)
Reference Voltage
0.5
1.5
V
VCOM
VREF
1.45
1.2
80
V
V
Reference Voltage Temperature
Coefficient
VREFTC
ppm/˚C
VIN Input Capacitance (each pin to
CIN
4
pF
VSSA
)
POWER SUPPLY CHARACTERISTICS
STBY = 1
4.7
22
6.0
29
mA
mA
mA
mA
mW
mW
IVDDA
IVDDIO
PWR
Analog Supply Current
Digital Supply Current
Power Consumption
STBY = 0
STBY = 1, fIN = 0 Hz
STBY 0, fIN = 0 Hz
STBY = 1
0
0.97
14.1
68.4
1.2
18.0
90
STBY = 0
5
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DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications
apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied)
fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C
Symbol
Parameter
Conditions
Min
2
Typ
Max
Units
CLK, DF, STBY, SENSE
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
V
V
0.8
+10
µA
µA
−10
D0–D9 OUTPUT CHARACTERISTICS
Logical “1” Output Voltage
IOUT = −0.5 mA
IOUT = 1.6 mA
VDDIO−0.2
V
V
Logical “0” Output Voltage
0.4
DYNAMIC CONVERTER CHARACTERISTICS
fIN = 11 MHz
fIN = 32 MHz
fIN = 11 MHz
fIN = 32 MHz
fIN = 11 MHz
fIN = 32 MHz
9.4, 9.3
9.3, 9.2
58.6, 58
58.5, 57.9
58.3, 57.6
58, 57.4
−75.6,
−69.7
9.6
9.5
Bits
Bits
dB
ENOB
SNR
Effective Number of Bits
Signal-to-Noise Ratio
59.6
59.3
59.4
59
dB
dB
SINAD
Signal-to-Noise Ratio + Distortion
dB
fIN = 11 MHz
fIN = 32 MHz
−90
−82
−74
−72
−74
−72
−80
−80
dBc
dBc
dBc
dBc
dB
2nd HD
3rd HD
THD
2nd Harmonic
3rd Harmonic
−72.7,
−68.9
−66.2,
−63
fIN = 11 MHz
fIN = 32 MHz
−65.4,
−63.3
−66.2,
−63
fIN = 11 MHz
fIN = 32 MHz
fIN = 11 MHz
fIN = 32 MHz
Total Harmonic Distortion (First 6
Harmonics)
−65.4,
−63.3
dB
−75.8,
−74.5
dBc
dBc
Spurious Free Dynamic Range
SFDR
(Excluding 2nd and 3rd Harmonic)
−74.4,
−73.3
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AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN
=
2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 65 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits ap-
ply for TA = TMIN to TMAX: all other limits TA = 25˚C
Typ
(Note
12)
Max
(Note
12)
Symbol
Parameter
Conditions
Min
(Note 12)
Units
CLK, DF, STBY, SENSE
fCLK
CLK2
tCH
tCL
tCONV
1
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
65
MHz (min)
f
20
MHz
ns
7.69
7.69
Clock Low Time
ns
Conversion Latency
6
5
6
Cycles
ns
T = 25˚C
2
3.4
Data Output Delay after a Rising
Clock Edge
tOD
1
ns
tAD
tAJ
Aperture Delay
Aperture Jitter
1
2
ns
ps (RMS)
Differential VIN step from
3V to 0V to get
Over Range Recovery Time
Standby Mode Exit Cycle
1
Clock Cycle
Cycles
accurate conversion
tSTBY
20
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = V
= V
= 0V, unless otherwise specified.
SSIO
SSA
<
>
V
DDA DDIO
Note 3: When the voltage at any pin exceeds the power supplies (V
V
or V
, V
), the current at that pin should be limited to 25 mA. The 50 mA
IN
SSA
IN
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T max, the
J
J
junction-to-ambient thermal resistance (θ ), and the ambient temperature (T ), and can be calculated using the formula P MAX = (T max − T )/θ . In the 28-pin
JA
A
D
J
A
JA
TSSOP, θ is 96˚C/W, so P MAX = 1,302 mW at 25˚C and 677 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of
JA
D
this device under normal operation will typically be about 68.6 mW. The values for maximum power dissipation listed above will be reached only when the ADC10065
is operated in a severe fault condition.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle. The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage
this device. However, input errors will be generated if the input goes above V
or V
and below V
or V
.
DDA
DDIO
SSA
SSIO
Note 7: VCOM is a typical value, measured at room temperature. It is not guaranteed by test.
20077907
Note 8: To guarantee accuracy, it is required that |V
–V
| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
DDA
DDIO
Note 9: With the test condition for 2 V
differential input, the 10-bit LSB is 1.95 mV.
P-P
Note 10: Typical figures are at T = T = 25˚C and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
A
J
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V = 0.4V for a falling edge, and V = 2.4V for a rising edge.
IL
IH
Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V.
Note 14: I is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
DDIO
V
, and the rate at which the outputs are switching (which is signal dependent). I = V x (C x f + C x f + C + f +....C x f ) where V is the output driver
DR
DR DR 0 0 1 1 2 2 11 11 DR
supply voltage, C is the total load capacitance on the output pin, and f is the average frequency at which the pin is toggling.
n
n
Note 15: Power consumption includes output driver power. (f = 0 MHz).
IN
−
+
.
Note 16: The input bandwidth is limited using a 10 pF capacitor between V
and V
IN
IN
Note 17: V
is a typical value, measured at room temperature, and is not guaranteed by test.
COM
7
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PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conver-
sion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 11⁄
below positive full scale.
2
LSB
COMMON MODE VOLTAGE (VCM) is the d.c. potential
present at both signal inputs to the ADC.
CONVERSION LATENCY See PIPELINE DELAY.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital
waveform is high to the total time of one period. The speci-
fication here refers to the ADC clock input signal.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral compo-
nents below half the clock frequency, including harmonics
but excluding dc.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and states that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dBc, of the rms total of the first six harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as:
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full-Scale Error − Negative Full-
Scale Error
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (1⁄
2
LSB below the first code transition)
through positive full scale (1⁄
2
LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
where f1 is the RMS power of the fundamental (output)
frequency and f2 through f6 are the RMS power in the first 6
harmonic frequencies.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC10065 is guaranteed
not to have any missing codes.
SECOND HARMONIC DISTORTION (2ND HARM) is the
difference expressed in dB, between the RMS power in the
input frequency at the output and the power in its 2nd
harmonic level at the output.
NEGATIVE FULL SCALE ERROR is the difference between
+
−
the input voltage (VIN − VIN ) just causing a transition from
negative full scale to the first code and its ideal value of
0.5 LSB.
THIRD HARMONIC DISTORTION (3RD HARM) is the dif-
ference, expressed in dB, between the RMS power in the
input frequency at the output and the power in its 3rd har-
monic level at the output.
OFFSET ERROR is the input voltage that will cause a tran-
sition from a code of 01 1111 1111 to a code of 10 0000 0000.
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
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Timing Diagram
20077909
FIGURE 1. Clock and Data Timing Diagram
Transfer Characteristics
20077910
FIGURE 2. Input vs. Output Transfer Characteristic
9
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Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz,
fIN = 11 MHz, 50% Duty Cycle.
DNL
DNL vs. fCLK
DNL vs. Temperature
INL vs. fCLK
20077912
20077915
20077916
20077917
DNL vs. Clock Duty Cycle (DC input)
20077913
INL
20077914
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Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz,
fIN = 11 MHz, 50% Duty Cycle. (Continued)
INL vs. Clock Duty Cycle
SNR vs. VDDIO
20077918
20077920
20077922
20077919
20077921
20077923
SNR vs. VDDA
SNR vs. fCLK
INL vs. Temperature
SNR vs. Clock Duty Cycle
11
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Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz,
fIN = 11 MHz, 50% Duty Cycle. (Continued)
SNR vs. Temperature
THD vs. VDDA
THD vs. fCLK
THD vs. IRS
20077924
20077926
20077928
20077925
20077927
20077929
THD vs. VDDIO
SNR vs. IRS
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Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz,
fIN = 11 MHz, 50% Duty Cycle. (Continued)
SINAD vs. VDDA
THD vs. Clock Duty Cycle
THD vs. Temperature
SINAD vs. VDDIO
20077930
20077932
20077934
20077931
20077933
20077935
SINAD vs. Clock Duty Cycle
SINAD vs. Temperature
13
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Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz,
fIN = 11 MHz, 50% Duty Cycle. (Continued)
SINAD vs. fCLK
SINAD vs. IRS
SFDR vs. VDDA
SFDR vs. VDDIO
SFDR vs. fCLK
SFDR vs. IRS
20077936
20077938
20077940
20077937
20077939
20077941
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Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 65 MHz,
fIN = 11 MHz, 50% Duty Cycle. (Continued)
@
Spectral Response 11 MHz Input
SFDR vs. Clock Duty Cycle
20077942
20077943
@
Spectral Response 32 MHz Input
SFDR vs. Temperature
20077944
20077945
Power Consumption vs. fCLK
20077946
15
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Functional Description
The ADC10065 uses a pipeline architecture and has error
correction circuitry to help ensure maximum performance.
Differential analog input signals are digitized to 10 bits. In
differential mode, each analog input signal should have a
peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depend-
ing on the state of the IRS pin (pin 5), and be centered
around VCM and be 180˚ out of phase with each other. If
single ended operation is desired, VIN- may be tied to the
VCOM pin (pin 4). A single ended input signal may then be
applied to VIN+, and should have an average value in the
range of VCM. The signal amplitude should be 2.0V, 1.5V or
1.0V peak-to-peak, depending on the state or the IRS pin
(pin 5).
20077948
FIGURE 4. Input Voltage Waveform for a 2VP-P Single
Ended Input
Applications Information
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 18Ω series resistors at each of the signal
inputs with a 25 pF capacitor across the inputs, as can be
seen in Figure 5. These components should be placed close
to the ADC because the input pins of the ADC is the most
sensitive part of the system and this is the last opportunity to
filter the input. The two 18Ω resistors and the 25 pF capaci-
tors form a low-pass filter with a -3 dB frequency of 177 Mhz.
1.0 ANALOG INPUTS
The ADC10065 has two analog signal inputs, VIN+ and VIN−.
These two pins form a differential input pair. There is one
common mode pin VCOM that may be used to set the com-
mon mode input voltage.
1.1 REFERENCE PINS
The ADC10065 is designed to operate with a 1.2V reference.
The voltages at VCOM, VREFT, and VREFB are derived from
the reference voltage. It is very important that all grounds
associated with the reference voltage and the input signal
make connection to the analog ground plane at a single point
to minimize the effects of noise currents in the ground path.
1.4 CLK PIN
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 20 MHz to 65 MHz with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚. The CLK signal also drives
an internal state machine. If the CLK is interrupted, or its
frequency is too low, the charge on internal capacitors can
dissipate to the point where the accuracy of the output data
will degrade. This is what limits the lowest sample rate to
20 MSPS. The duty cycle of the clock signal can affect the
performance of any A/D Converter. Because achieving a
precise duty cycle is difficult, the ADC10065 is designed to
maintain performance over a range of duty cycles. While it is
specified and performance is guaranteed with a 50% clock
duty cycle, performance is typically maintained over a clock
duty cycle range of 40% to 60%.
The three Reference Bypass Pins VREF, VREFT and VREFB
,
are made available for bypass purposes only. These pins
should each be bypassed to ground with a 0.1 µF capacitor.
DO NOT LOAD these pins.
1.2 VCOM PIN
This pin supplies a voltage for possible use to set the com-
mon mode input voltage. This pin may also be connected to
VIN-, so that VIN+ may be used as a single ended input. This
pin should be bypassed with at least a 0.1 uF capacitor.
1.3 SIGNAL INPUTS
The signal inputs are VIN+ and VIN−. The input signal ampli-
tude is defined as VIN+ − VIN− and is represented schemati-
cally in Figure 3:
1.5 STBY PIN
The STBY pin, when high, holds the ADC10065 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 15 mW.
The output data pins are undefined in this mode. Power
consumption during power-down is not affected by the clock
frequency, or by whether there is a clock signal present. The
data in the pipeline is corrupted while in the power down.
1.6 DF PIN
The DF pin, when high, forces the ADC10065 to output the
2’s complement data format. When DF is tied low, the output
format is offset binary.
20077947
FIGURE 3. Input Voltage Waveforms for a 2VP-P
differential Input
1.7 IRS PIN
The IRS (Input Range Select) pin defines the input signal
amplitude that will produce a full scale output. The table
below describes the function of the IRS pin.
A single ended input signal is shown in Figure 4.
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charging current spikes can cause on-chip ground noise and
couple into the analog circuitry, degrading dynamic perfor-
mance. Adequate bypassing, limiting output capacitance and
careful attention to the ground plane will reduce this prob-
lem. Additionally, bus capacitance beyond the specified
10 pF/pin will cause tOD to increase, making it difficult to
properly latch the ADC output data. The result could be an
apparent reduction in dynamic performance. To minimize
noise due to output switching, minimize the load currents at
the digital outputs. This can be done by connecting buffers
between the ADC outputs and any other circuitry. Only one
driven input should be ADC pins, will isolate the outputs from
trace and other circuit capacitances and limit the output
currents, which could otherwise result in performance deg-
radation.
Applications Information (Continued)
TABLE 1. IRS Pin Functions
IRS Pin
VDDA
Full-Scale Input
2.0VP-P
VSSA
1.5VP-P
Floating
1.0VP-P
1.8 OUTPUT PINS
The ADC10065 has 10 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the DF and STBY pins are low. While the tOD time provides
information about output timing, a simple way to capture a
valid output is to latch the data on the rising edge of the
conversion clock. Be very careful when driving a high ca-
pacitance bus. The more capacitance the output drivers
must charge for each conversion, the more instantaneous
digital current flows through VDDIO and VSSIO. These large
1.9 APPLICATION SCHEMATICS
The following figures show simple examples of using the
ADC10065. Figure 5 shows a typical differentially driven
input. Figure 6 shows a single ended application circuit.
20077949
FIGURE 5. A Simple Application Using a Differential Driving Source
17
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Applications Information (Continued)
20077950
FIGURE 6. A Simple Application Using a Single Ended Driving Source
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18
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead TSSOP Package
Ordering Number ADC10065CIMT
NS Package Number MTC28
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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