ADC08138CIWM [NSC]
8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function; 8位高速串行I / OA / D转换器与多路复用器选项，参考电压和采样/保持功能
| 型号： | ADC08138CIWM |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function |
| 文件： | 总21页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
ADC08131/ADC08134/ADC08138
8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold
Function
General Description
The ADC08131/ADC08134/ADC08138 are 8-bit successive
approximation A/D converters with serial I/O and config-
urable input multiplexers with up to 8 channels. The serial
I/O is configured to comply with the NSC MICROWIRE se-
rial data exchange standard for easy interface to the
Applications
n Digitizing automotive sensors
n Process control/monitoring
n Remote sensing in noisy environments
n Embedded diagnostics
™
™
COPS family of controllers, and can easily interface with
Features
standard shift registers or microprocessors.
n Serial digital data link requires few I/O pins
n Analog input track/hold function
n 4- or 8-channel input multiplexer options with address
logic
All three devices provide a 2.5V band-gap derived reference
with guaranteed performance over temperature.
A track/hold function allows the analog voltage at the positive
input to vary during the actual A/D conversion.
±
n On-chip 2.5V band-gap reference ( 2% over
The analog inputs can be configured to operate in various
temperature guaranteed)
combinations
of
single-ended,
differential,
or
n No zero or full scale adjustment required
n TTL/CMOS input/output compatible
n 0V to 5V analog input range with single 5V power
supply
pseudo-differential modes. In addition, input voltage spans
as small as 1V can be accommodated.
Key Specifications
n Resolution
8 Bits
8 µs (Max)
=
n Conversion time (fC 1 MHz)
n Power dissipation
n Single supply
n Total unadjusted error
20 mW (Max)
±
( 5%)
5 VDC
1
±
±
⁄2
LSB and 1 LSB
1
=
±
n Linearity Error (VREF 2.5V)
⁄2 LSB
n No missing codes (over temperature)
n On-board Reference
±
+2.5V 1.5% (Max)
Ordering Information
Industrial
Package
(−40˚C ≤ TA ≤ +85˚C)
ADC08131CIWM
ADC08134CIWM
ADC08138CIWM
M14B
M14B
M20B
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
COPS microcontrollers and MICROWIRE are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS010749
www.national.com
Connection Diagrams
ADC08138CIWM
Small Outline
Packages
DS010749-2
ADC08134CIWM
Small Outline
Packages
DS010749-3
ADC08131CIWM
Small Outline Package
DS010749-4
www.national.com
2
Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Soldering Information
N Package (10 sec.)
SO Package:
260˚C
215˚C
220˚C
Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)
Storage Temperature
−65˚C to +150˚C
Supply Voltage (VCC
)
6.5V
Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
−0.3V to VCC + 0.3V
Operating Ratings (Notes 2, 3)
±
5 mA
±
20 mA
Temperature Range
TMIN ≤ TA ≤ TMAX
−40˚C ≤ TA ≤ +85˚C
4.5 VDC to 6.3 VDC
=
Power Dissipation at TA 25˚C
(Note 5)
800 mW
1500V
Supply Voltage (VCC
)
ESD Susceptibility (Note 6)
Electrical Characteristics
=
=
=
The following specifications apply for VCC +5 VDC, VREF +2.5 VDC and fCLK 1 MHz unless otherwise specified. Bold-
=
=
=
=
face limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
CONVERTER AND MULTIPLEXER CHARACTERISTICS
=
±
±
±
Linearity Error
Full Scale Error
Zero Error
VREF +2.5 VDC
1
1
1
LSB (max)
LSB (max)
LSB (max)
=
VREF +2.5 VDC
=
VREF +2.5 VDC
=
VREF +5 VDC
±
Total Unadjusted Error
Differential Linearity
1
LSB (max)
(Note 10)
=
VREF +2.5 VDC
8
Bits (min)
kΩ
3.5
RREF
Reference Input Resistance
(Note 11)
(Note 12)
1.3
6.0
kΩ (min)
kΩ (max)
V (max)
V (min)
(VCC + 0.05)
VIN
Analog Input Voltage
(GND − 0.05)
1
=
±
DC Common-Mode Error
Power Supply Sensitivity
VREF 2.5 VDC
⁄
2
LSB (max)
=
±
VCC +5V 5%,
1
±
⁄
4
LSB (max)
µA (max)
µA (max)
µA (max)
µA (max)
=
VREF +2.5 VDC
=
On Channel 5V,
0.2
1
=
Off Channel 0V
On Channel Leakage Current
(Note 13)
=
On Channel 0V,
−0.2
−1
=
Off Channel 5V
=
On Channel 5V,
−0.2
−1
=
Off Channel 0V
Off Channel Leakage Current
(Note 13)
=
On Channel 0V,
0.2
1
=
Off Channel 5V
DIGITAL AND DC CHARACTERISTICS
=
VIN(1)
VIN(0)
IIN(1)
IIN(0)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
VCC 5.25V
2.0
0.8
1
V (min)
V (max)
µA (max)
µA (max)
=
VCC 4.75V
=
VIN 5.0V
=
VIN 0V
−1
=
VCC 4.75V:
=
VOUT(1)
Logical “1” Output Voltage
Logical “0” Output Voltage
IOUT −360 µA
2.4
4.5
0.4
V (min)
V (min)
V (max)
=
IOUT −10 µA
=
VCC 4.75V
VOUT(0)
=
IOUT 1.6 mA
=
VOUT 0V
−3.0
3.0
µA (max)
µA (max)
mA (min)
IOUT
TRI-STATE® Output Current
Output Source Current
=
VOUT 5V
=
ISOURCE
VOUT 0V
−6.5
3
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Electrical Characteristics (Continued)
=
=
=
The following specifications apply for VCC +5 VDC, VREF +2.5 VDC and fCLK 1 MHz unless otherwise specified. Bold-
=
=
=
=
face limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
DIGITAL AND DC CHARACTERISTICS
=
ISINK
Output Sink Current
Supply Current
VOUT VCC
8.0
mA (min)
=
ICC
ADC08134, ADC08138
ADC08131 (Note 16)
CS HIGH
3.0
6.0
mA (max)
mA (max)
Electrical Characteristics
=
=
The following specifications apply for VCC +5 VDC, and fCLK 1 MHz unless otherwise specified. Boldface limits apply for
=
=
=
=
TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Conditions
REFERENCE CHARACTERISTICS
2.5
±
V
REFOUT
Output Voltage
DC08134, ADC08138
2.5 1.5%
V
±
2%
∆VREF/∆T
Temperature Coefficient
40
ppm/˚C
Sourcing
(0 ≤ IL ≤ +4 mA)
ADC08134,
ADC08138
0.003
0.1
0.1
0.5
Sourcing
(0 ≤ IL ≤ +2 mA)
ADC08131
0.003
0.2
%/mA
(max)
∆VREF/∆IL
Load Regulation (Note 17)
Sinking
(−1 ≤ IL ≤ 0 mA)
ADC08134,
ADC08138
Sinking
(−1 ≤ IL ≤ 0 mA)
ADC08131
0.2
0.5
0.5
6
Line Regulation
4.75V ≤ VCC ≤ 5.25V
mV (max)
=
VREF 0V
ADC08134,
ADC08138
8
8
25
25
mA
(max)
ISC
Short Circuit Current
=
VREF 0V
ADC08131
→
V
CC: 0V
5V
TSU
Start-Up Time
20
ms
=
CL 100 µF
∆VREF/∆t
Long Term Stability
200
ppm/1 kHr
Electrical Characteristics
=
=
=
=
The following specifications apply for VCC +5 VDC, VREF +2.5 VDC and tr tf 20 ns unless otherwise specified. Boldface
=
=
=
=
limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
Symbol
fCLK
Parameter
Clock Frequency
Conditions
10
kHz (min)
MHz (max)
% (min)
1
Clock Duty Cycle
(Note 14)
40
60
% (max)
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4
Electrical Characteristics (Continued)
=
=
=
=
The following specifications apply for VCC +5 VDC, VREF +2.5 VDC and tr tf 20 ns unless otherwise specified. Boldface
=
=
=
=
limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
Symbol
TC
Parameter
Conditions
fCLK 1 MHz
Conversion Time (Not Including
MUX Addressing Time)
8
1/fCLK (max)
µs (max)
1/fCLK (max)
ns
=
8
1
tCA
Acquisition Time
⁄
2
tSELECT
CLK High while CS is High
CS Falling Edge or Data Input
Valid to CLK Rising Edge
50
tSET-UP
tHOLD
25
20
ns (min)
ns (min)
Data Input Valid after CLK Rising
Edge
=
CL 100 pF:
CLK Falling Edge to Output Data
Valid (Note 15)
t
t
pd1, tpd0
Data MSB First
Data LSB First
250
200
ns (max)
ns (max)
=
=
CL 10 pF, RL 10 kΩ
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS
Hi-Z
50
ns
1H, t0H
(see TRI-STATE Test Circuits)
=
=
CL 100 pF, RL 2 kΩ
180
ns (max)
pF
CIN
Capacitance of Logic Inputs
Capacitance of Logic Outputs
5
5
COUT
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-
fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character-
istics may degrade when the device is not operated under the listed test conditions.
=
=
Note 3: All voltages are measured with respect to AGND DGND 0 V , unless otherwise specified.
DC
<
>
AV ) the current at that pin should be limited to
CC
Note 4: When the input voltage (V ) at any pin exceeds the power supplies (V
IN IN
(AGND or DGND) or V
IN
5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ and the ambient temperature, T . The maximum
A
JMAX JA
=
allowable power dissipation at any temperature is P
(T
− T )/θ or the number given in the Absolute Maximum Ratings, whichever is lower. For these devices
JA
D
JMAX
A
=
T
125˚C. The typical thermal resistances (θ ) of these parts when board mounted for the ADC 08131 and the ADC08134 is 140˚C/W and 91˚C/W for the
JA
JMAX
ADC08138.
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Data Book section “Surface Mount” for other methods of soldering
surface mount devices.
=
Note 8: Typicals are at T
25˚C and represent the most likely parametric norm.
J
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
=
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with V
+5V only applies to the ADC08134 and
REF
ADC08138. See (Note 16).
Note 11: Cannot be tested for the ADC08131.
Note 12: For V
≥ V the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct for
IN(+)
IN(−)
analog input voltages one diode drop below ground or one diode drop greater than V supply. During testing at low V levels (e.g., 4.5V), high level analog inputs
CC CC
(e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification allows
50 mV forward bias of either diode; this means that as long as the analog V does not exceed the supply voltage by more than 50 mV, the output code will be correct.
IN
Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V to 5 V input voltage range will
DC DC
therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following two
cases are considered: one, with the selected channel tied high (5 V ) and the remaining seven off channels tied low (0 V ), total current flow through the off chan-
D
C
D
C
nels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two cases
considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits
the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow
for comparator response time.
Note 16: For the ADC08131 V
IN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the
REF
reference current (700 µA typical, 2 mA maximum).
Note 17: Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the ADC08131 has the
on-board reference as a permanent load.
5
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ADC08138 Simplified Block Diagram
DS010749-1
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6
Typical Converter Performance Characteristics
Linearity Error vs
Reference Voltage
Linearity Error vs
Temperature
Linearity Error vs
Clock Frequency
DS010749-27
DS010749-28
DS010749-29
Power Supply Current vs
Temperature (ADC08138,
ADC08134)
Output Current vs
Temperature
Power Supply Current
vs Clock Frequency
DS010749-31
DS010749-32
DS010749-30
Note: For ADC08131 add IREF
Typical Reference Performance Characteristics
Load Regulation
Line Regulation
(3 Typical Parts)
Output Drift
vs Temperature
(3 Typical Parts)
DS010749-34
DS010749-33
DS010749-35
7
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Typical Reference Performance Characteristics (Continued)
Available
Output Current
vs Supply Voltage
DS010749-36
TRI-STATE Test Circuits and Waveforms
t1H
t1H
DS010749-39
DS010749-37
t0H
t0H
DS010749-40
DS010749-38
Timing Diagrams
Data Input Timing
DS010749-9
*
To reset these devices, CLK and CS must be simultaneously high for a period of t
SELECT
or greater. Otherwise these devices are compatible with industry
standards ADC0831/4/8.
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8
Timing Diagrams (Continued)
Data Output Timing
ADC08131 Start Conversion Timing
ADC08131 Timing
DS010749-10
DS010749-11
DS010749-12
*LSB first output not available on ADC08131.
LSB information is maintained for remainder of clock periods until CS goes high.
ADC08134 Timing
DS010749-13
9
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Timing Diagrams (Continued)
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10
ADC08138 Functional Block Diagram
11
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Functional Description
MULTIPLEXER ADDRESSING
mode the polarity may also be selected. Channel 0 may be
selected as the positive input and channel 1 as the negative
input or vice versa. This programmability is best illustrated by
the MUX addressing codes shown in the following tables for
the various product options.
The design of these converters utilizes a comparator struc-
ture with built-in sample-and-hold which provides for a differ-
ential analog input to be converted by a successiveapproxi-
mation routine.
The MUX address is shifted into the converter via the DI line.
Because the ADC08131 contains only one differential input
channel with a fixed polarity assignment, it does not require
addressing.
The actual voltage converted is always the difference be-
tween an assigned “+” input terminal and a “−” input terminal.
The polarity of each input terminal of the pair indicates which
line the converter expects to be the most positive. If the as-
signed “+” input voltage is less than the “−” input voltage the
converter responds with an all zeros output code.
The common input line (COM) on the ADC08138 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the “−” input for any of the other input
channels. This voltage does not have to be analog ground; it
can be any reference potential which is common to all of the
inputs. This feature is most useful in single-supply applica-
tions where the analog circuity may be biased up to a poten-
tial other than ground and the output signals are all referred
to this potential.
A unique input multiplexing scheme has been utilized to pro-
vide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog in-
put and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flex-
ibility. One converter package can now handle ground refer-
enced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
TABLE 1. Multiplexer/Package Options
Part
Number of Analog Channels
Number of
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential.
Differential inputs are restricted to adjacent channel pairs.
For example, channel 0 and channel 1 may be selected as a
differential pair but channel 0 or 1 cannot act differentially
with any other channel. In addition to selecting differential
Number
Single-Ended
Differential
Package
Pins
ADC08131
ADC08134
ADC08138
1
4
8
1
2
4
8
14
20
TABLE 2. MUX Addressing: ADC08138
Single-Ended MUX Mode
MUX Address
Analog Single-Ended Channel #
START
SGL/
ODD/
SELECT
0
1
2
3
4
5
6
7
COM
DIF
1
SIGN
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
−
−
−
−
−
−
−
−
1
+
1
+
1
+
1
+
1
+
1
+
1
+
TABLE 3. MUX Addressing: ADC08138
Differential MUX Mode
MUX Address
Analog Differential Channel-Pair #
START
SGL/
ODD/
SELECT
0
1
2
3
DIF
0
SIGN
1
0
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
+
−
0
+
−
0
+
−
0
+
−
0
−
+
0
−
+
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12
Functional Description (Continued)
TABLE 3. MUX Addressing: ADC08138 (Continued)
Differential MUX Mode
MUX Address
Analog Differential Channel-Pair #
START
SGL/
DIF
0
ODD/
SIGN
1
SELECT
0
1
2
3
1
0
0
1
0
1
2
3
4
5
6
7
1
1
1
1
−
+
0
1
−
+
TABLE 4. MUX Addressing: ADC08134
Single-Ended MUX Mode
MUX Address
Channel #
START
SGL/
ODD/
SELECT
0
1
2
3
DIF
1
SIGN
1
0
1
0
1
1
1
1
1
0
0
1
1
+
1
+
1
+
1
+
COM is internally tied to AGND
Differential MUX Mode
MUX Address
Channel #
START
SGL/
ODD/
SELECT
0
+
−
1
−
+
2
3
DIF
0
SIGN
1
0
1
0
1
1
1
1
1
0
0
1
1
0
+
−
−
+
0
0
Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illus-
trates the input flexibility which can be achieved.
The start bit is the first logic “1” that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX as-
signment word.
3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been as-
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above VCC (typically 5V) with-
out degrading conversion accuracy.
signed and a conversion is about to begin. An interval of
1
⁄ clock period is automatically inserted to allow for sam-
2
pling the analog input. The SARS line goes high at the
end of this time to signal that a conversion is now in
progress and the DI line is disabled (it no longer accepts
data).
THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system im-
provements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.
4. The data out (DO) line now comes out of TRI-STATE
and provides a leading zero.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gener-
ated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conver-
sion being shifted out (with the MSB first) and can be
read by the processor immediately.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conver-
sion. The converter is now waiting for a start bit and its
MUX assignment word.
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this 1
⁄ clock cycle later.
2
2. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
13
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is an exception in that its data is only output in MSB first
format.
Functional Description (Continued)
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers the data can be provided in an LSB first format
[this makes use of the shift enable (SE) control line]. On
the ADC08138 the SE line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE is forced low the data is clocked out LSB first. On de-
vices which do not include the SE control line, the data,
LSB first, is automatically shifted out the DO line after
the MSB first data stream. The DO line then goes low
and stays low until CS is returned high. The ADC08131
8. All internal registers are cleared when the CS line is high
and the tSELECT requirement is met. See Data Input Tim-
ing under Timing Diagrams. If another conversion is de-
sired CS must make a high to low transition followed by
address information.
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only “looked-at”
during the MUX addressing interval while the DO line is
still in a high impedance state.
8 Single-Ended
4 Differential
DS010749-43
DS010749-41
Mixed Mode
8 Psuedo-Differential
DS010749-42
DS010749-44
FIGURE 1. Analog Input Multiplexer Options for the ADC08138
REFERENCE CONSIDERATIONS
temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
can be tied directly to VREFIN for an analog input span of 0V
to 2.5V. This output can also be used to bias external circuits
and can therefore be used as the reference in ratiometric ap-
plications. Bypassing VREFOUT with a 100 µF capacitor is
recommended.
The VREFIN pin on these converters is the top of a resistor
divider string and capacitor array used for the successive ap-
proximation conversion. The voltage applied to this refer-
ence input defines the voltage span of the analog input (the
difference between VIN(MAX) and VIN(MIN) over which the 256
possible output codes apply). The reference source must be
capable of driving the reference input resistance, which can
be as low as 1.3 kΩ.
For the ADC08131, the output of the on-board reference is
internally tied to the reference input. Consequently, the ana-
log input span for this device is set at 0V to 2.5V. The pin
For absolute accuracy, where the analog input varies be-
tween specific voltage limits, the reference input must be bi-
ased with a stable voltage source. The ADC08134 and the
ADC08138 provide the output of a 2.5V band-gap reference
at VREFOUT. This voltage does not vary appreciably with
V
REFC is provided for bypassing purposes and biasing exter-
nal circuits as suggested above.
The maximum value of the reference is limited to the VCC
supply voltage. The minimum value, however, can be quite
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14
noise pickup, circuit layout and system error voltage sources
when operating with a reduced span due to the increased
sensitivity of the converter (1 LSB equals VREF/256).
Functional Description (Continued)
small (see Typical Performance Characteristics) to allow di-
rect conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
DS010749-18
DS010749-17
b) Absolute
a) Ratiometric
FIGURE 2. Reference Examples
THE ANALOG INPUTS
amp RC active low pass filter can provide both impedance
buffering and noise filtering should a high impedance signal
source be required.
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces-
sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accu-
racy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
OPTIONAL ADJUSTMENTS
Zero Error
The zero of the A/D does not require adjustment. If the mini-
mum analog input voltage value, VIN(MIN), is not ground a
zero offset can be done. The converter can be made to out-
put 0000 0000 digital code for this minimum input voltage by
biasing any VIN (−) input at this VIN(MIN) value. This utilizes
the differential mode operation of the A/D.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected “+” and “−” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+” in-
put and then the “−” input is 1
in the common-mode voltage during this short time interval
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the VIN (−) input and applying a small magnitude
positive voltage to the VIN (+) input. Zero error is the differ-
ence between the actual DC input voltage which is neces-
⁄
2
of a clock period. The change
can cause conversion errors. For
common-mode signal this error is:
a
sinusoidal
sary to just cause an output digital code transition from 0000
1
0000 to 0000 0001 and the ideal
⁄2
LSB value (1⁄
LSB
=
2
=
9.8mV for VREF 5.000VDC).
Full Scale
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value
A full-scale adjustment can be made by applying a differen-
tial input voltage which is 11⁄
LSB down from the desired
2
and fCLK is the A/D clock frequency.
analog full-scale voltage range and then adjusting the mag-
nitude of the VREFIN input for a digital output code which is
just changing from 1111 1110 to 1111 1111 (See figure en-
titled “Span Adjust; 0V ≤ VIN ≤ 3V”). This is possible only with
the ADC08134 and ADC08138. (The reference is internally
connected to VREFIN of the ADC08131).
For a 60Hz common-mode signal to generate a 1
⁄ LSB error
4
(≈5 mV) with the converter running at 250kHz, its peak value
would have to be 6.63V which would be larger than allowed
as it exceeds the maximum analog input limits.
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operating
near or at maximum speed bypass capacitors should not be
used if the source resistance is greater than 1kΩ. The
±
worst-case leakage current of 1µA over temperature will
create a 1mV input error with a 1kΩ source resistance. An op
15
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Functional Description (Continued)
Adjusting for an Arbitrary Analog Input
Voltage Range
where:
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
=
VMAX the high end of the analog input range
and
=
should be properly adjusted first. A VIN (+) voltage which
VMIN the low end (the offset zero) of the analog range.
1
equals this desired zero reference plus
LSB is calculated for the desired analog span, using 1 LSB
⁄ LSB (where the
2
(Both are ground referenced.)
=
The VREFIN (or VCC) voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the ad-
justment procedure.
analog span/256) is applied to selected “+” input and the
zero reference voltage at the corresponding “−” input should
then be adjusted to just obtain the 00HEX to 01HEX code tran-
sition.
The full-scale adjustment should be made [with the proper
V
IN (−) voltage applied] by forcing a voltage to the VIN (+) in-
put which is given by:
Applications
A “Stand-Alone” Hook-Up for ADC08138 Evaluation
DS010749-45
*Pinouts shown for ADC08138.
For all other products tie to pin functions as shown.
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16
Applications (Continued)
Low-Cost Remote Temperature Sensor
DS010749-46
Protecting the Input
DS010749-22
Diodes are 1N914
17
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Applications (Continued)
Operating with Ratiometric Transducers
DS010749-23
=
*V (−) 0.15 V
IN REF
15% of V ≤ V
REF XDR
≤ 85% of V
REF
Span Adjust; 0V ≤ VIN ≤ 3V
DS010749-24
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18
Applications (Continued)
Zero-Shift and Span Adjust: 2V ≤ VIN ≤ 5V
DS010749-25
19
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Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC08134CIWM
NS Package Number M14B
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20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number ADC08138CIWM
NS Package Number M20B
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