ADC081500_09 [NSC]
High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter; 高性能，低功耗， 8位， 1.5 GSPS A / D转换器
| 型号： | ADC081500_09 |
| 厂家： | 
National Semiconductor |
| 描述： | High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| 文件： | 总34页 (文件大小：1189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 21, 2009
ADC081500
High Performance, Low Power, 8-Bit, 1.5 GSPS A/D
Converter
General Description
Features
The ADC081500 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 8 bits res-
olution at sample rates up to 1.7 GSPS. Consuming a typical
1.2 W at 1.5 GSPS from a single 1.9 Volt supply, this device
is guaranteed to have no missing codes over the full operating
temperature range. The unique folding and interpolating ar-
chitecture, the fully differential comparator design, the inno-
vative design of the internal sample-and-hold amplifier and
the self-calibration scheme enable a very flat response of all
dynamic parameters beyond Nyquist, producing a high 7.3
ENOB with a 748 MHz input signal and a 1.5 GHz sample rate
while providing a 10-18 B.E.R. Output formatting is offset bi-
nary and the LVDS digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable output offset
voltage between 0.8V and 1.2V.
Internal Sample-and-Hold
■
■
■
■
■
■
■
■
Single +1.9V ±0.1V Operation
Choice of SDR or DDR output clocking
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock
Key Specifications
Resolution
Max Conversion Rate
Bit Error Rate
ENOB @ 748 MHz Input
8 Bits
1.5 GSPS (min)
10-18 (typ)
7.3 Bits (typ)
±0.15 LSB (typ)
■
■
■
The converter output has a 1:2 demultiplexer that feeds two
LVDS buses and reduces the output data rate on each bus to
one-half the sample rate.
■
DNL
■
Power Consumption
■
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40°C ≤ TA ≤ +85°C) temperature range.
Operating
Power Down Mode
1.2 W (typ)
3.5 mW (typ)
—
—
■
Applications
Direct RF Down Conversion
■
■
■
■
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
■
Block Diagram
20153153
© 2009 National Semiconductor Corporation
201531
www.national.com
Ordering Information
Industrial Temperature Range
NS Package
(-40°C < TA < +85°C)
ADC081500CIYB
ADC081500DEV
128-Pin Exposed Pad LQFP
Development Board
Pin Configuration
20153101
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
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2
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie
this pin high for normal differential DCLK and data
amplitude. Ground this pin for a reduced differential output
amplitude and reduced power consumption. See Section
1.1.6. When the extended control mode is enabled, this pin
functions as the SCLK input which clocks in the serial data.
See Section 1.3
OutV /
SCLK
3
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. (See Section 1.1.5.2).
When this pin is floating or connected to 1/2 the supply
voltage, DDR clocking is enabled. When the extended
control mode is enabled, this pin functions as the (SDATA)
input. See Section 1.2 for details on the extended control
mode.
OutEdge /
DDR /
SDATA
4
DCLK Reset. A positive pulse on this pin is used to reset
and synchronize the DCLK outputs of multiple converters.
See Section 1.5 for detailed description.
15
26
DCLK_RST
PD
Power Down Pin. A logic high on the PD pin puts the device
into the Power Down Mode.
Calibration Cycle Initiate. A minimum 80 input clock cycles
logic low followed by a minimum of 80 input clock cycles
high on this pin initiates the self calibration sequence. See
Section 2.4.2.
30
CAL
Full Scale Range Select and Extended Control Enable. In
non-extended control mode, a logic low on this pin sets the
full-scale differential input range to a reduced VIN input
level . A logic high on this pin sets the full-scale differential
input range to a higher VIN input level. See Converter
Electrical Characteristics. To enable the extended control
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to VA/2. See Section 1.2 for information on the
extended control mode.
14
FSR/ECE
Calibration Delay and Serial Interface Chip Select. With a
logic high or low on pin 14, this pin functions as Calibration
Delay and sets the number of input clock cycles after power
up before calibration begins (See Section 1.1.1). With pin
14 floating, this pin acts as the enable pin for the serial
interface input and the CalDly value becomes "0" (short
delay with no provision for a long power-up calibration
delay).
CalDly /
SCS
127
3
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Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal
is sampled on the falling edge of CLK+. See Section 2.3.
18
19
CLK+
CLK-
Analog signal inputs to the ADC. The differential full-scale
input range of this input is programmable using the FSR pin
14 in normal mode and the Input Full-Scale Voltage Adjust
register in the extended control mode. Refer to the VIN
specification in the Converter Electrical Characteristics for
the full-scale input range in the normal mode. Refer to ??
1.4 for the full-scale input range in the extended control
mode.
VIN+
VIN−
11
10
Common Mode Voltage. The voltage output at this pin is
required to be the common mode input voltage at VIN+ and
VIN− when d.c. coupling is used. This pin should be
grounded when a.c. coupling is used at the analog inputs.
This pin is capable of sourcing or sinking 100 μA. See
Section 2.2.
VCMO
7
ꢀ
31
ꢀ
VBG
Bandgap output voltage capable of 100 μA source/sink.
Calibration Running indication. This pin is at a logic high
when calibration is running.
126
CalRun
External bias resistor connection. Nominal value is 3.3 k-
Ohms (±0.1%) to ground. See Section 1.1.1.
REXT
32
Temperature Diode Positive (Anode) and Negative
(Cathode). These pins may be used for die temperature
measurements, however no specified accuracy is implied
or guaranteed. See Section 2.6.2.
34
35
Tdiode_P
Tdiode_N
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4
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
83
84
85
86
89
90
91
92
93
94
95
96
100
101
102
103
D7−
D7+
D6−
D6+
D5−
D5+
D4−
D4+
D3−
D3+
D2−
D2+
D1−
D1+
D0−
D0+
The LVDS Data Outputs that are not delayed in the output
demultiplexer. Compared with the Dd outputs, these
outputs represent the later time samples. These outputs
should always be terminated with a 100Ω differential
resistor.
104
105
106
107
111
112
113
114
115
116
117
118
122
123
124
125
Dd7−
Dd7+
Dd6−
Dd6+
Dd5−
Dd5+
Dd4−
Dd4+
Dd3−
Dd3+
Dd2−
Dd2+
Dd1−
Dd1+
Dd0
The LVDS Data Outputs that are delayed by one CLK cycle
in the output demultiplexer. Compared with the D outputs,
these outputs represent the earlier time sample. These
outputs should always be terminated with a 100Ω
differential resistor.
Dd0
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside
the range ±VIN/2 as programmed by the FSR pin in non-
extended control mode or the Input Full-Scale Voltage
Adjust register setting in the extended control mode).
79
80
OR+
OR-
Differential Clock outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input
clock rate in SDR mode and at 1/4 the input clock rate in
the DDR mode. The DCLK outputs are not active during a
calibration cycle. The DCLK outputs are not active during a
calibration cycle, therefore this is not recommended as a
system clock.
82
81
DCLK+
DCLK-
2, 5, 8, 13, 16, 17, 20,
25, 28, 33, 128
VA
Analog power supply pins. Bypass these pins to ground.
40, 51 ,62, 73, 88, 99,
110, 121
Output Driver power supply pins. Bypass these pins to DR
GND.
VDR
GND
1, 6, 9, 12, 21, 24, 27,
41
Ground return for VA.
5
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Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
42, 53, 64, 74, 87, 97,
108, 119
Ground return for VDR
.
DR GND
22, 23, 29, 36-39,
43-50, 52, 54-61, 63,
65-72, 75-78, 98, 109,
120
NC
No Connection. Make no connection to these pins.
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6
Absolute Maximum Ratings
(Notes 1, 2)
Operating Ratings (Notes 1, 2)
Ambient Temperature Range
−40°C ≤ TA ≤ +85°C
Supply Voltage (VA)
+1.8V to +2.0V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Driver Supply Voltage (VDR
)
+1.8V to VA
Analog Input Common Mode Voltage
VCMO ±50mV
Supply Voltage (VA, VDR
)
2.2V
VIN+, VIN- Voltage Range
(Maintaining Common Mode)
0V to 2.15V
(100% duty cycle)
0V to 2.5V
Supply Difference
VDR - VA
0V to 100 mV
(10% duty cycle)
Voltage on Any Input Pin
(Except VIN+, VIN-)
Ground Difference
(|GND - DR GND|)
CLK Pins Voltage Range
Differential CLK Amplitude
−0.15V to (VA +0.15V)
0V
0V to VA
Voltage on VIN+, VIN-
(Maintaining Common Mode)
Ground Difference
|GND - DR GND|
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
-0.15V to 2.5V
0.4VP-P to 2.0VP-P
0V to 100 mV
±25 mA
Package Thermal Resistance
θJC (Top of
θJ-PAD
±50 mA
Package
θJA
Package)
(Thermal Pad)
Power Dissipation at TA ≤ 85°C
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
2.0 W
128-Lead
Exposed Pad
LQFP
ꢀ
2500V
250V
26°C / W 10°C / W
2.8°C / W
Figure 13Soldering process must comply with National
Semiconductor’s Reflow Temperature Profile specifications.
Refer to www.national.com/packaging.Figure 13 (Note 5)
Soldering Temperature, Infrared,
10 seconds, (Note 5), (Applies
to standard plated package only)
235°C
Storage Temperature
−65°C to +150°C
Converter Electrical Characteristics
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN (a.c. coupled) Full Scale Range =
differential 870mVP-P, CL = 10 pF, Differential (a.c. coupled) sinewave input clock, fCLK = 1.5 GHz at 0.5VP-P with 50% duty cycle,
VBG = Floating, Normal Control Mode, Single Data Rate Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Notes 6, 7)
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
Parameter
Conditions
STATIC CONVERTER CHARACTERISTICS
DC Coupled, 1MHz Sine Wave Over
ranged
INL
Integral Non-Linearity (Best fit)
Differential Non-Linearity
±0.3
±0.9
±0.6
8
LSB (max)
LSB (max)
Bits
DC Coupled, 1MHz Sine Wave Over
ranged
DNL
±0.15
Resolution with No Missing
Codes
−1.5
1.0
LSB (min)
LSB (max)
VOFF
Offset Error
-0.45
VOFF_ADJ
PFSE
Input Offset Adjustment Range
Positive Full-Scale Error
Extended Control Mode
(Note 9)
±45
−0.6
−1.31
±20
mV
±25
±25
±15
mV (max)
mV (max)
%FS
NFSE
Negative Full-Scale Error
Full-Scale Adjustment Range
(Note 9)
FS_ADJ
Extended Control Mode
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
B.E.R.
Full Power Bandwidth
Bit Error Rate
1.7
10-18
±0.5
±1.0
7.4
GHz
Error/Sample
dBFS
d.c. to 500 MHz
Gain Flatness
d.c. to 1 GHz
dBFS
fIN = 373 MHz, VIN = FSR − 0.5 dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
fIN = 373 MHz, VIN = FSR − 0.5 dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
7.0
Bits (min)
Bits (min)
dB (min)
dB (min)
ENOB
SINAD
Effective Number of Bits
7.3
46.3
45.4
43.9
Signal-to-Noise Plus Distortion
Ratio
7
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Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
SNR
Parameter
Conditions
fIN = 373 MHz, VIN = FSR − 0.5 dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
fIN = 373 MHz, VIN = FSR − 0.5 dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
fIN = 373 MHz, VIN = FSR − 0.5 dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
fIN = 373 MHz, VIN = FSR − 0.5 dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
fIN = 373 MHz, VIN = FSR − 0.5 dB
fIN = 748 MHz, VIN = FSR − 0.5 dB
47
46.3
-54.5
-53
−60
-57
−62
-65
56
44.5
-47
dB (min)
dB (min)
dB (max)
dB (max)
dB
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
Spurious-Free dynamic Range
Intermodulation Distortion
2nd Harm
3rd Harm
SFDR
dB
dB
dB
48.5
dB (min)
dB (min)
53
fIN1 = 321 MHz, VIN = FSR − 7 dB
fIN2 = 326 MHz, VIN = FSR − 7 dB
IMD
-50
dB
(VIN+) − (VIN−) > + Full Scale
(VIN+) − (VIN−) < − Full Scale
255
0
Out of Range Output Code
(In addition to OR Output high)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
mVP-P (min)
mVP-P (max)
mVP-P (min)
mVP-P (max)
570
730
790
950
FSR pin 14 Low
650
Full Scale Analog Differential
Input Range
VIN
FSR pin 14 High
870
VCMO − 50
VCMO + 50
Analog Input Common Mode
Voltage
mV (min)
mV (max)
VCMI
CIN
VCMO
Differential
0.02
1.6
pF
pF
Analog Input Capacitance (Notes
10, 11)
Each input pin to ground
94
Ω (min)
Ω (max)
RIN
Differential Input Resistance
100
106
ANALOG OUTPUT CHARACTERISTICS
0.95
1.45
V (min)
V (max)
VCMO
ICMO = ±100 µA
Common Mode Output Voltage
1.26
118
Common Mode Output Voltage
Temperature Coefficient
TC VCMO
TA = −40°C to +85°C
ppm/°C
VA = 1.8V
VA = 2.0V
0.60
0.66
V
V
VCMO input threshold to set DC
Coupling mode
VCMO_LVL
Maximum VCMO load
Capacitance
CLOAD VCMO
80
pF
Bandgap Reference Output
Voltage
1.20
1.33
V (min)
V (max)
VBG
IBG = ±100 µA
1.26
28
TA = −40°C to +85°C,
IBG = ±100 µA
Bandgap Reference Voltage
Temperature Coefficient
TC VBG
ppm/°C
pF
Maximum Bandgap Reference
load Capacitance
CLOAD VBG
80
TEMPERATURE DIODE CHARACTERISTICS
192 µA vs. 12 µA,
TJ = 25°C
71.23
85.54
mV
mV
ΔVBE
Temperature Diode Voltage
192 µA vs. 12 µA,
TJ = 85°C
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8
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
Parameter
Conditions
CLOCK INPUT CHARACTERISTICS
VP-P (min)
VP-P (max)
0.4
2.0
Sine Wave Clock
0.6
0.6
VID
Differential Clock Input Level
Input Current
VP-P (min)
VP-P (max)
0.4
2.0
Square Wave Clock
II
VIN = 0 or VIN = VA
Differential
±1
0.02
1.5
µA
pF
pF
Input Capacitance
(Notes 10, 11)
CIN
Each input to ground
DIGITAL CONTROL PIN CHARACTERISTICS
VIH
VIL
0.85 x VA
0.15 x VA
Logic High Input Voltage
Logic Low Input Voltage
(Note 12)
(Note 12)
V (min)
V (max)
Input Capacitance
(Notes 11, 13)
CIN
Each input to ground
1.2
pF
DIGITAL OUTPUT CHARACTERISTICS
mVP-P (min)
mVP-P (max)
mVP-P (min)
mVP-P (max)
400
920
280
720
Measured differentially, OutV = VA, VBG
= Floating (Note 15)
710
VOD
LVDS Differential Output Voltage
Measured differentially, OutV = GND,
VBG = Floating (Note 15)
510
±1
Change in LVDS Output Swing
Between Logic Levels
Δ VO DIFF
mV
VOS
VOS
VBG = Floating
Output Offset Voltage
Output Offset Voltage
800
mV
mV
VBG = VA (Note 15)
1200
Output Offset Voltage Change
Between Logic Levels
Δ VOS
±1
mV
IOS
Output Short Circuit Current
Differential Output Impedance
CalRun High level output
CalRun Low level output
Output+ & Output- connected to 0.8V
±4
mA
Ohms
V
ZO
100
1.65
0.15
VOH
VOL
IOH = -400uA (Note 12)
IOH = 400uA (Note 12)
1.5
0.3
V
POWER SUPPLY CHARACTERISTICS
PD = Low
PD = High
524
1.8
600
165
1.45
mA (max)
mA
IA
Analog Supply Current
Output Driver Supply Current
Power Consumption
PD = Low
PD = High
116
0.012
mA (max)
mA
IDR
PD = Low
PD = High
1.2
3.5
W (max)
mW
PD
Change in Full Scale Error with change
in VA from 1.8V to 2.0V
D.C. Power Supply Rejection
Ratio
PSRR1
PSRR2
30
51
dB
dB
A.C. Power Supply Rejection
Ratio
248 MHz, 50mVP-P riding on VA
AC ELECTRICAL CHARACTERISTICS
fCLK1
fCLK2
Maximum Input Clock Frequency
Minimum Input Clock Frequency
1.7
1.5
GHz (min)
MHz
200
20
80
% (min)
% (max)
200 MHz ≤ Input clock frequency ≤ 1.5
GHz (Note 12)
Input Clock Duty Cycle
50
tCL
tCH
Input Clock Low Time
Input Clock High Time
(Note 11)
(Note 11)
333
333
133
133
ps (min)
ps (min)
45
55
% (min)
% (max)
DCLK Duty Cycle
Reset Setup Time
(Note 11)
(Note 11)
50
tRS
150
ps
9
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Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
tRH
Parameter
Reset Hold Time
Conditions
(Note 11)
(Note 11)
250
ps
Synchronizing Edge to DCLK
Output Delay
tSD
tOD + tOSK
CLK± Cycles
(min)
tRPW
tLHT
tHLT
Reset Pulse Width
4
Differential Low to High Transition
Time
10% to 90%, CL = 2.5 pF
10% to 90%, CL = 2.5 pF
250
250
ps
ps
Differential High to Low Transition
Time
50% of DCLK transition to 50% of Data
transition, SDR Mode
tOSK
DCLK to Data Output Skew
±50
ps (max)
and DDR Mode, 0° DCLK (Note 11)
tSU
tH
tAD
tAJ
Data to DCLK Set-Up Time
DCLK to Data Hold Time
Sampling (Aperture) Delay
Aperture Jitter
DDR Mode, 90° DCLK (Note 11)
DDR Mode, 90° DCLK (Note 11)
Input CLK+ Fall to Acquisition of Data
400
560
1.3
ns
ns
ns
0.4
ps rms
Input Clock to Data Output Delay 50% of Input Clock transition to 50% of
tOD
3.1
ns
(in addition to Pipeline Delay)
Data transition
D Outputs
13
14
Pipeline Delay (Latency)
(Notes 11, 14)
Input CLK±
Cycles
Dd Outputs
Differential VIN step from ±1.2V to 0V to
get accurate conversion
Input CLK±
Cycle
Over Range Recovery Time
1
PD low to Rated Accuracy
Conversion (Wake-Up Time)
tWU
500
ns
fSCLK
tSSU
tSH
Serial Clock Frequency
(Note 11)
100
2.5
1
MHz
ns (min)
Data to Serial Clock Setup Time (Note 11)
Data to Serial Clock Hold Time
Serial Clock Low Time
(Note 11)
ns (min)
4
4
ns (min)
Serial Clock High Time
Calibration Cycle Time
ns (min)
tCAL
1.4 x 105
CLK± Cycles
CLK± Cycles
(min)
tCAL_L
CAL Pin Low Time
CAL Pin High Time
See Figure 9 (Note 11)
See Figure 9 (Note 11)
80
80
CLK± Cycles
(min)
tCAL_H
CalDly = Low
See Section 1.1.1, Figure 9,
(Note 11)
CLK± Cycles
(min)
225
Calibration delay determined by
pin 127
tCalDly
CalDly = High
See Section 1.1.1, Figure 9,
(Note 11)
CLK± Cycles
(max)
231
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
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10
20153104
Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to
ground are isolated from the die capacitances by lead and bond wire inductances.
Note 11: This parameter is guaranteed by design and is not tested in production.
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14: The ADC081500 converter has two LVDS output buses, which each clock data out at one half the sample rate. The second bus (D0 through D7) has
a pipeline latency that is one Input Clock cycle less than the latency of the first bus (Dd0 through Dd7).
Note 15: Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above. Tying VBG to the
supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).
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Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
nal and goes into the “hold” mode the aperture delay time
(tAD) after the input clock goes low.
APERTURE JITTER (tAJ) is the variation in aperture delay
from sample to sample. Aperture jitter shows up as input
noise.
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Bit Error Rate (B.E.R.) is the probability of error and is de-
fined as the probable number of errors per unit of time divided
by the number of bits seen in that amount of time. A B.E.R. of
10-18 corresponds to a statistical error in one bit about every
four (4) years.
FIGURE 1.
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint
between the D+ and D- pins output voltage; i.e., [(VD+) +
( VD-)]/2.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wave form is at a logic high to the total time of one clock pe-
riod.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes can-
not be reached with any input value.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at sample rate = ?? MSPS with a 1MHz input
sinewave.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of
how far the first code transition is from the ideal 1/2 LSB above
a differential −VIN /2. For the ADC081500 the reference volt-
age is assumed to be ideal, so this error is a combination of
full-scale error and reference voltage error.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD −
1.76) / 6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
OFFSET ERROR (VOFF) is a measure of how far the mid-
scale point is from the ideal zero voltage differential input.
FULL POWER BANDWIDTH (FPBW) is a measure of the
frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
Offset Error = Actual Input causing average of 8k samples to
result in an average code of 127.5.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and Full-
Scale Errors:
OUTPUT DELAY (tOD) is the time delay (in addition to
Pipeline Delay) after the falling edge of CLK+ before the data
update is present at the output pins.
Pos. Gain Error = Offset Error − Pos. Full-Scale Error
Neg. Gain Error = −(Offset Error − Neg. Full-Scale Error)
OVER-RANGE RECOVERY TIME is the time required after
the differential input voltages goes from ±1.2V to 0V for the
converter to recover and make a conversion with its rated ac-
curacy.
Gain Error = Neg. Full-Scale Error − Pos. Full-Scale Error
= Pos. Gain Error + Neg. Gain Error
INTEGRAL NON-LINEARITY (INL) is a measure of worst
case deviation of the ADC transfer function from an ideal
straight line drawn through the ADC transfer function. The
deviation of any given code from this straight line is measured
from the center of that code value step. The best fit method
is used.
PIPELINE DELAY (LATENCY) is the number of input clock
cycles between initiation of conversion and when that data is
presented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the tOD
.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of
how far the last code transition is from the ideal 1-1/2 LSB
below a differential + VIN. For the ADC081500 the reference
voltage is assumed to be ideal, so this error is a combination
of full-scale error and reference voltage error.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
it is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
POWER SUPPLY REJECTION RATIO (PSRR) can be one
of two specifications. PSRR1 (DC PSRR) is the ratio of the
change in full-scale error that results from a power supply
voltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is a
measure of how well an a.c. signal riding upon the power
supply is rejected from the output and is measured with a 248
MHz, 50 mVP-P signal riding upon the power supply. It is the
ratio of the output amplitude of that signal at the output to its
amplitude on the power supply pin. PSRR is expressed in dB.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is
VFS / 2n
where VFS is the differential full-scale amplitude VIN as set by
the FSR input and "n" is the ADC resolution in bits, which is
8 for the ADC081500.
LVDS DIFFERENTIAL OUTPUT VOLTAGE (VOD) is the ab-
solute value of the difference between the VD+ & VD- outputs;
each measured with respect to Ground.
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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the rms
value of the sum of all other spectral components below one-
half the sampling frequency, not including harmonics or d.c.
where Af1 is the RMS power of the fundamental (output) fre-
quency and Af2 through Af10 are the RMS power of the first 9
harmonic frequencies in the output spectrum.
– Second Harmonic Distortion (2nd Harm) is the differ-
ence, expressed in dB, between the RMS power in the input
frequency seen at the output and the power in its 2nd har-
monic level at the output.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
spectral components below half the input clock frequency, in-
cluding harmonics but excluding d.c.
– Third Harmonic Distortion (3rd Harm) is the difference
expressed in dB between the RMS power in the input fre-
quency seen at the output and the power in its 3rd harmonic
level at the output.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio ex-
pressed in dB, of the rms total of the first nine harmonic levels
at the output to the level of the fundamental at the output. THD
is calculated as
Transfer Characteristic
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FIGURE 2. Input / Output Transfer Characteristic
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Timing Diagrams
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FIGURE 3. ADC081500 Timing — SDR Clocking
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FIGURE 4. ADC081500 Timing — DDR Clocking
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FIGURE 5. Serial Interface Timing
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FIGURE 6. Clock Reset Timing in DDR Mode
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FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low
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20153124
FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High
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FIGURE 9. Self Calibration and On-Command Calibration Timing
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Typical Performance Characteristics VA = VDR = 1.9V, FCLK = 1500MHz, TA = 25°C unless otherwise
stated.
INL vs. CODE
INL vs. TEMPERATURE
DNL vs. TEMPERATURE
ENOB vs. TEMPERATURE
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DNL vs. CODE
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POWER DISSIPATION vs. SAMPLE RATE
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ENOB vs. SUPPLY VOLTAGE
ENOB vs. INPUT FREQUENCY
SNR vs. SUPPLY VOLTAGE
ENOB vs. SAMPLE RATE
SNR vs. TEMPERATURE
SNR vs. SAMPLE RATE
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SNR vs. INPUT FREQUENCY
THD vs. SUPPLY VOLTAGE
THD vs. INPUT FREQUENCY
THD vs. TEMPERATURE
THD vs. SAMPLE RATE
SFDR vs. TEMPERATURE
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20153173
20153175
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20153174
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SFDR vs. SUPPLY VOLTAGE
SFDR vs. SAMPLE RATE
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SFDR vs. INPUT FREQUENCY
Spectral Response at FIN = 373 MHz
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20153187
Spectral Response at FIN = 745 MHz
FULL POWER BANDWIDTH
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In normal operation, calibration is performed just after appli-
cation of power and whenever a valid calibration command is
given, which is holding the CAL pin low for at least tCAL_L clock
cycles, then hold it high for at least another tCAL_H clock cycles
as defined in the Converter Electrical Characteristics. The
time taken by the calibration procedure is specified as tCALin
Converter Electrical Characteristics. Holding the CAL pin high
upon power up will prevent the calibration process from run-
ning until the CAL pin experiences the above-mentioned
tCAL_L clock cycles followed by tCAL_H clock cycles.
1.0 Functional Description
The ADC081500 is a versatile A/D Converter with an innova-
tive architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is generally poor practice to allow an active pin to float,
pins 4 and 14 of the ADC081500 are designed to be left float-
ing without jeopardy. In all discussions throughout this data
sheet, whenever a function is called by allowing a control pin
to float, connecting that pin to a potential of one half the VA
supply voltage will have the same effect as allowing it to float.
CalDly (pin 127) is used to select one of two delay times after
the application of power to the start of calibration. This cali-
bration delay time is depedent on the setting of the CalDly pin
and is specified as tCalDly in the Converter Electrical Charac-
teristics. These delay values allow the power supply to come
up and stabilize before calibration takes place. If the PD pin
is high upon power-up, the calibration delay counter will be
disabled until the PD pin is brought low. Therefore, holding
the PD pin high during power up will further delay the start of
the power-up calibration cycle. The best setting of the CalDly
pin depends upon the power-on settling time of the power
supply.
1.1 OVERVIEW
The ADC081500 uses a calibrated folding and interpolating
architecture that achieves 7.4 effective bits. The use of folding
amplifiers greatly reduces the number of comparators and
power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter.
Calibration Operation Notes:
•
During the calibration cycle, the OR output may be active
as a result of the calibration algorithm. All data on the
output pins and the OR output are invalid during the
calibration cycle.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 200 MSPS
to 1.7 GSPS, typical. Differential input voltages below nega-
tive full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at the input will cause the OR (Out of Range)
output to be activated. That is, the single OR output indicates
the output code is below negative full scale or above positive
full scale.
•
During the power-up calibration and during the on-
command calibration, all clocks are halted on chip,
including internal clocks and DCLK, while the input
termination resistor is trimmed to a value that is equal to
REXT / 33. This is to reduce noise during the input resistor
calibration portion of the calibration cycle. See??2.4.2 for
information on maintaining DCLK operation during on-
command calibration.
The ADC081500 has a 1:2 demultiplexer that feeds two LVDS
output buses. The data on these buses provide an output
word rate on each bus at half the ADC sampling rate and must
be interleaved by the user to provide output words at the full
conversion rate.
This external resistor is located between pin 32 and
ground. REXT must be 3300 Ω ±0.1%. With this value, the
input termination resistor is trimmed to be 100 Ω. Because
REXT is also used to set the proper current for the Track
and Hold amplifier, for the preamplifiers and for the
comparators, other values of REXT should not be used.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erro-
neous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
•
The CalRun output is high whenever the calibration
procedure is running. This is true whether the calibration
is done at power-up or on-command.
1.1.1 Self-Calibration
A self-calibration is performed upon power-up and can also
be invoked by the user upon command. Calibration trims the
100Ω analog input differential termination resistor and mini-
mizes full-scale error, offset error, DNL and INL, resulting in
maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal
bias currents are also set with the calibration process. All of
this is true whether the calibration is performed upon power
up or is performed upon command. Running the self calibra-
tion is an important part of this chip's functionality and is
required in order to obtain adequate performance. In addition
to the requirement to be run at power-up, self calibration must
be re-run whenever the sense of the FSR pin is changed. For
best performance, we recommend that self calibration be run
20 seconds or more after application of power and whenever
the operating temperature changes significantly relative to the
specific system performance requirements. See Section
2.4.2.2 for more information. Calibration can not be initiated
or run while the device is in the power-down mode. See Sec-
tion 1.1.7 for information on the interaction between Power
Down and Calibration.
1.1.2 Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the
digital equivalent of that data is available at the digital outputs
13 input clock cycles later for the D output bus and 14 input
clock cycles later for the Dd output bus. There is an additional
internal delay called tOD before the data is available at the
outputs. See the Timing Diagram. The ADC081500 will con-
vert as long as the input clock signal is present. The fully
differential comparator design and the innovative design of
the sample-and-hold amplifier, together with self calibration,
enables a very flat SINAD/ENOB response beyond 1.5 GHz.
The ADC081500 output data signaling is LVDS and the output
format is offset binary.
1.1.3 Control Modes
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, power down mode and full scale range
setting. However, the ADC081500 also provides an Extended
Control mode whereby a serial interface is used to access
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register-based control of several advanced features. The Ex-
tended Control mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the Normal Control mode or the Extended Control
mode at all times. When the device is in the Extended Control
mode, pin-based control of several features is replaced with
register-based control and those pin-based controls are dis-
abled. These pins are OutV (pin 3), OutEdge/DDR (pin 4),
FSR (pin 14) and CalDly (pin 127). See Section 1.2 for details
on the Extended Control mode.
es. With double data rate the DCLK frequency is half the data
rate and data is sent to the outputs on both DCLK edges. DDR
clocking is enabled in Normal Control mode by allowing pin 4
to float.
1.1.6 The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are
LVDS. Output current sources provide 3 mA of output current
to a differential 100 Ohm load when the OutV input (pin 14) is
high or 2.2 mA when the OutV input is low. For short LVDS
lines and low noise systems, satisfactory performance may
be realized with the OutV input low, which results in lower
power consumption. If the LVDS lines are long and/or the
system in which the ADC081500 is used is noisy, it may be
necessary to tie the OutV pin high.
1.1.4 The Analog Inputs
The ADC081500 must be driven with a differential input sig-
nal. Operation with a single-ended signal is not recommend-
ed. It is important that the inputs either be a.c. coupled to the
inputs with the VCMO pin grounded, or d.c. coupled with the
VCMO pin left floating. An input common mode voltage equal
to the VCMO output must be provided when d.c. coupling is
used.
The LVDS data output have a typical common mode voltage
of 800mV when the VBG pin is unconnected and floating. This
common mode voltage can be increased to 1.2V by tying the
VBG pin to VA if a higher common mode is required.
The input full-scale range is programmable in the normal
mode by setting a level on pin 14 (FSR) as defined in by the
specification VIN in the Converter Electrical Characteristics.
The full-scale range setting operates equally on both ADCs.
IMPORTANT NOTE: Tying the VBG pin to VA will also in-
crease the differential LVDS output voltage by up to 40mV.
1.1.7 Power Down
The ADC081500 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
power down mode. In this power down mode the data output
pins (positive and negative) are put into a high impedance
state and the devices power consumption is reduced to a
minimal level. The DCLK+/- and OR +/- are not tri-stated, they
are weakly pulled down to ground internally. Therefore when
the device is powered down the DCLK +/- and OR +/- should
not be terminated to a DC voltage. Also note, that upon return
to normal operation after power down mode, the pipeline will
contain meaningless information.
In the Extended Control mode, programming the Input Full-
Scale Voltage Adjust register allows the input full-scale range
to be adjusted as described in Section 2.2 and Section
1.1.5 Clocking
The ADC081500 must be driven with an a.c. coupled, differ-
ential clock signal. Section 2.3 describes the use of the clock
input pins. A differential LVDS output clock is available for use
in latching the ADC output data into whatever device is used
to receive the data. The ADC081500 offers options for output
clocking. These options include a choice of which DCLK edge
the output data transitions on, and a choice of Single Data
Rate (SDR) or Double Data Rate (DDR) outputs.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state.
The ADC081500 also has the option to use a duty cycle cor-
rected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking. This circuitry allows the ADC to be clocked with a
signal source having a duty cycle ratio of 80 / 20 % (worst
case).
1.1.5.1 OutEdge Setting
1.2 NORMAL/EXTENDED CONTROL MODES
To help ease data capture in the SDR mode, the output data
may be caused to transition on either the positive or the neg-
ative edge of the output data clock (DCLK). This is chosen
with the OutEdge input (pin 4). A high on the OutEdge input
pin causes the output data to transition on the rising edge of
DCLK, while grounding this input causes the output to transi-
tion on the falling edge of DCLK. See Section 2.4.3.
The ADC081500 may be operated in one of two modes. In
the simpler Normal Control mode, the user affects available
configuration and control of the device through several control
pins. The Extended Control mode provides additional config-
uration and control options through a serial interface and a
set of 3 registers. The two control modes are selected with
pin 14 (FSR/ECE: Extended Control Enable). The choice of
control modes is required to be a fixed selection and is not
intended to be switched dynamically while the device is op-
erational.
1.1.5.2 Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the output clock DCLK
frequency is the same as the data rate of the two output bus-
Table 1 shows how several of the device features are affected
by the control mode chosen.
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TABLE 1. Features and modes
Normal Control Mode
Feature
Extended Control Mode
Selected with nDE in the Configuration
Register (1h; bit-10). When the device is
in DDR mode, address 1h, bit-8 must be
set to 0b.
DDR Clocking selected with pin 4
floating. SDR clocking selected when pin
4 not floating.
SDR or DDR Clocking
Selected with DCP in the Configuration
Register (1h; bit-11).
DDR Clock Phase
Not Selectable (0° Phase Only)
SDR Data transitions with rising edge of
DCLK+ when pin 4 is high and on falling
edge when low.
SDR Data transitions with rising or falling
DCLK edge
Selected with OE in the Configuration
Register (1h; bit-8).
Normal differential data and DCLK
amplitude selected when pin 3 is high
and reduced amplitude selected when Configuration Register (1h; bit-9).
low.
Selected with the OV in the
LVDS output level
Short delay selected when pin 127 is low
Short delay only.
Power-On Calibration Delay
Full-Scale Range
and longer delay selected when high.
Normal input full-scale range selected Up to 512 step adjustments over a
when pin 14 is high and reduced range nominal range specified in ??1.4.
when low. Selected range applies to both Selected using the Input Full-Scale
channels.
Adjust register (3h; bits-7 thru 15).
512 steps of adjustment using the Input
Offset register (2h; bits-7 thru 15) as
specified in ??1.4.
Input Offset Adjust
Not possible
The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 2.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
TABLE 2. Extended Control Mode Operation (Pin 14
Floating)
Each Register access consists of 32 bits, as shown in Figure
5 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 3.
Extended Control Mode
Feature
Default State
SDR or DDR Clocking
DDR Clock Phase
DDR Clocking
Data changes with DCLK
edge (0° phase)
Normal amplitude
LVDS Output Amplitude
(710 mVP-P
)
Refer to the Register Description (Section 1.4) for information
on the data to be written to the registers.
Calibration Delay
Full-Scale Range
Input Offset Adjust
Short Delay
700 mV nominal
No adjustment
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
1.3 THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the serial
interface, all 3 user registers must be written with desired or
default values. Once all registers have been written once,
other desired settings can be loaded.
IMPORTANT NOTE: The Serial Interface should not be used
when calibrating the ADC. Doing so will impair the perfor-
mance of the device until it is re-calibrated correctly. Pro-
gramming the serial registers will also reduce dynamic
performance of the ADC for the duration of the register access
time.
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS) Three write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted with the rising edge of
this signal. There is no minimum frequency requirement for
SCLK.
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TABLE 3. Register Addresses
4-Bit Address
Bit 10
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Double
Data Rate) mode whereby a data word is
output with each rising and falling edge of
DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate)
mode whereby each data word is output with
either the rising or falling edge of DCLK, as
determined by the OutEdge bit.
Loading Sequence:
A3 loaded after Fixed Header Pattern, A0 loaded last
A3
0
A2
0
A1
0
A0
0
Hex Register Addressed
0h
1h
2h
Reserved
Configuration
Input Offset
0
0
0
1
0
0
1
0
Input Full-Scale
Voltage Adjust
POR State: 0b
0
0
1
1
3h
Bit 9
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mVP-P is used. When this bit is set to 0b, the
reduced output amplitude of 510 mVP-P is
used.
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
POR State: 1b
Bit 8
OE: Output Edge. This bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as the
OutEdge pin in the normal control mode.
When this bit is 1, the data outputs change with
the rising edge of DCLK+. When this bit is 0,
the data output change with the falling edge of
DCLK+.
1.4 REGISTER DESCRIPTION
Three write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
POR State: 0b
Bits 7:0
Must be set to 1b.
Input Offset
Addr: 2h (0010b)
W only (0x007F)
Configuration Register
Addr: 1h (0001b)
W only (0xB2FF)
D15 D14 D13 D12 D11 D10
D9
D8
(MSB)
Offset Value
(LSB)
D15 D14 D13 D12 D11 D10
D9
DCS DCP nDE OV
D8
1
0
1
OE
D7
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Sign
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Bits 15:8 Input Offset Value. The input offset of the ADC
is adjusted linearly and monotonically by the
value in this field. 00h provides a nominal zero
offset, while FFh provides a nominal 45 mV of
offset. Thus, each code step provides 0.176
mV of offset.
Bit 15
Bit 14
Bit 13
Bit 12
Must be set to 1b
Must be set to 0b
Must be set to 1b
DCS: Duty Cycle Stabilizer. When this bit is set
to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
POR State: 1b
POR State: 0000 0000 b
Bit 7
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Bit 11
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to a 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase").
POR State: 0b
Bit 6:0
Must be set to 1b
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24
Input Full-Scale Voltage Adjust
Addr: 3h (0011b) W only (0x807F)
ADCs in a system to have their DCLK (and data) outputs
transition at the same time with respect to the shared CLK
input that all the ADCs use for sampling.
The DCLK_RST signal must observe some timing require-
ments that are shown in Figure 6, Figure 7 and Figure 8 of the
Timing Diagrams. The DCLK_RST pulse must be of a mini-
mum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. These
timing specifications are listed as tRH, tRS, and tRPW in the
Converter Electrical Characteristics.
D15
D14 D13 D12 D11 D10
Adjust Value
D9
D8
(MSB)
D7
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
(LSB)
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 6, Figure 7 and Figure 8 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, the next CLK falling edge synchronizes the
DCLK output with those of other ADC081500s in the system.
The DCLK output is enabled again after a constant delay (rel-
ative to the input clock frequency) which is equal to the CLK
input to DCLK output delay (tSD). The device always exhibits
this delay characteristic in normal operation.
Bit 15:7
Input Full Scale Voltage Adjust Value. The
input full-scale voltage or gain of the ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mVP-P differential value.
0000 0000 0
560mVP-P
700mVP-P
1000 0000 0
Default Value
1111 1111 1
840mVP-P
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
The DCLK_RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
POR State: 1000 0000 0b (no adjustment)
Bits 6:0 Must be set to 1b
2.0 Applications Information
1.4.1 Note Regarding Extended Mode Offset Correction
When using the Input Offset Adjust register, the following in-
formation should be noted.
Table 52.1 THE REFERENCE VOLTAGE
The voltage reference for the ADC081500 is derived from a
1.254V bandgap reference which is made available at pin 31,
VBG for user convenience. This output has an output current
capability of ±100 μA and should be buffered if more current
than this is required.
For offset values of +0000 0000 and -0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
The internal bandgap-derived reference voltage has a nomi-
nal value of VIN, as determined by the FSR pin and described
in Section 1.1.4.
There is no provision for the use of an external reference volt-
age, but the full-scale input voltage can be adjusted through
a Configuration Register in the Extended Control mode, as
explained in Section 1.2.
Differential input signals up to the chosen full-scale level will
be digitized to 8 bits. Signal excursions beyond the full-scale
range will be clipped at the output. These large signal excur-
sions will also activate the OR output for the time that the
signal is out of range. See Section 2.2.2.
One extra feature of the VBG pin is that it can be used to raise
the common mode voltage level of the LVDS outputs. The
output offset voltage (VOS) is typically 800 mV when the VBG
pin is used as an output or left unconnected. To raise the
LVDS offset voltage to a typical value of 1200 mV the VBG pin
can be connected directly to the supply rails.
20153130
2.2 THE ANALOG INPUT
FIGURE 10. Extended Mode Offset Behavior
1.5 MULTIPLE ADC SYNCHRONIZATION
The analog input is a differential one to which the signal
source may be a.c. coupled or d.c. coupled. In the normal
mode, the full-scale input range is selected using the FSR pin
as specified in the Converter Electrical Characteristics. In the
Extended Control mode, the full-scale input range is selected
by programming the Full-Scale Voltage Adjust register
The ADC081500 has the capability to precisely reset its sam-
pling clock input to DCLK output relationship as determined
by the user-supplied DCLK_RST pulse. This allows multiple
25
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through the Serial Interface. For best performance when ad-
justing the input full-scale range in the Extended Control, refer
to ?? 1.4 for guidelines on limiting the amount of adjustment.
single-ended signals is to convert them to differential signals
before presenting them to the ADC.
2.2.1.1 A.C. Coupled Input
Table 4 gives the input to output relationship with the FSR pin
high when the normal (non-extended) mode is used. With the
FSR pin grounded, the millivolt values inTable 4 are reduced
to 75% of the values indicated. In the Enhanced Control
Mode, these values will be determined by the full scale range
and offset settings in the Control Registers.
The easiest way to accomplish single-ended a.c. input to dif-
ferential a.c. signal is by using an appropriate balun, as shown
in Figure 12.
TABLE 4. DIFFERENTIAL INPUT TO OUTPUT
RELATIONSHIP (Normal Control Mode, FSR High)
VIN+
VIN−
Output Code
0000 0000
0100 0000
VCM − 217.5mV
VCM − 109 mV
VCM + 217.5mV
VCM + 109 mV
20153143
0111 1111 /
1000 0000
VCM
VCM
FIGURE 12. Single-Ended To Differential Signal
Conversion Using a Balun
VCM + 109 mV
VCM + 217.5mV
VCM −109 mV
1100 0000
1111 1111
Figure 12 is a generic depiction of a single-ended to differen-
tial signal conversion using a balun. The circuitry specific to
the balun will depend on the type of balun selected and the
overall board layout. It is recommended that the system de-
signer contact the manufacturer of the balun they have se-
lected to aid in designing the best performing single-ended to
differential conversion circuit using that particular balun.
VCM − 217.5mV
The buffered analog inputs simplify the task of driving these
inputs and the RC pole that is generally used at sampling ADC
inputs is not required. If it is desired to use an amplifier circuit
before the ADC, use care in choosing an amplifier with ade-
quate noise and distortion performance and adequate gain at
the frequencies used for the application.
When selecting a balun, it is important to understand the input
architecture of the ADC. There are specific balun parameters
of which the system designer should be mindful. They should
match the impedance of their analog source to the
ADC081500's on-chip 100 differential input termination resis-
tor. The range of this termination resistor is described in the
electrical table as the specification RIN.
Note that a precise d.c. common mode voltage must be
present at the ADC inputs. This common mode voltage,
VCMO, is provided on-chip when a.c. input coupling is used
and the input signal is a.c. coupled to the ADC.
When the inputs are a.c. coupled, the VCMO output must be
grounded, as shown in Figure 11. This causes the on-chip
VCMO voltage to be connected to the inputs through on-chip
50k-Ohm resistors.
Also, as a result of the ADC architecture, the phase and am-
plitude balance are important. The lowest possible phase and
amplitude imbalance is desired when selecting a balun. The
phase imbalance should be no more than ±2.5° and the am-
plitude imbalance should be limited to less than 1dB at the
desired input frequency range. Finally, when selecting a
balun, the VSWR (Voltage Standing Wave Ratio), bandwidth
and insertion loss of the balun should also be considered. The
VSWR aids in determining the overall transmission line ter-
mination capability of the balun when interfacing to the ADC
input. The insertion loss should be considered so that the sig-
nal at the balun output is within the specified input range of
the ADC as described in the Converter Electrical Character-
istics as the specification VIN.
20153144
2.2.1.2 D.C. Coupled Input
FIGURE 11. Differential Input Drive
When d.c. coupling to the ADC081500 analog inputs is re-
quired, single-ended to differential conversion may be easily
accomplished with the LMH6555. An example of this type of
circuit is shown in Figure 13. In such applications, the
LMH6555 performs the task of single-ended to differential
conversion while delivering low distortion and noise, as well
as output balance, that supports the operation of the
ADC081500. Connecting the ADC081500 VCMO pin to the
VCM_REF pin of the LMH6555, through the appropriate buffer,
will ensure that the common mode input voltage is as needed
for optimum performance of the ADC081500. The LMV321
was chosen to buffer VCMO for its low voltage operation and
reasonable offset voltage.
When the d.c. coupled mode is used, a common mode volt-
age must be provided at the differential inputs that should
track the VCMO output voltage. The VCMO output potential will
change with temperature and the common mode output of the
driving device should track this change. Full-scale distortion
performance falls off rapidly as the input common mode
voltage deviates from VCMO. This is a direct result of using
a very low supply voltage to minimize power. Keep the
input common voltage within 50 mV of VCMO. Performance
is as good in the d.c. coupled mode as in the a.c. coupled
mode, provided the input common mode voltage at both ana-
log inputs remain within 50 mV of VCMO
.
Be sure that the current drawn from the VCMO output does not
exceed 100 μA.
2.2.1 Handling Single-Ended Input Signals
There is no provision for the ADC081500 to adequately pro-
cess single-ended input signals. The best way to handle
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26
signal must be capacitively coupled to the clock pins, as in-
dicated in Figure 14.
Operation up to the sample rates indicated in the Converter
Electrical Characteristics is typically possible if the maximum
ambient temperatures indicated are not exceeded. Operating
at higher sample rates than indicated for the given ambient
temperature may result in reduced device reliability and prod-
uct lifetime. This is because of the higher power consumption
and die temperatures at high sample rates. Important also for
reliability is proper thermal management . See Section 2.6.2.
20153155
FIGURE 13. Example of Servoing the Analog Input with
VCMO
In Table 5, RADJ- and RADJ+ are used to adjust the differential
offset that can be measured at the ADC inputs VIN+ / VIN-. An
unadjusted positive offset with reference to VIN- greater than
|15mV| should be reduced with a resistor in the RADJ- position.
Likewise, an unadjusted negative offset with reference to
VIN- greater than |15mV| should be reduced with a resistor in
the RADJ+ position. Table 5 gives suggested RADJ- and RADJ+
values for various unadjusted differential offsets to bring the
VIN+ / VIN- offset back to within |15mV|.
20153147
FIGURE 14. Differential (LVDS) Input Clock Connection
The differential Clock line pair should have a characteristic
impedance of 100Ω and be terminated at the clock source in
that (100Ω) characteristic impedance. The clock line should
be as short and as direct as possible. The ADC081500 clock
input is internally terminated with an untrimmed 100Ω resis-
tor.
TABLE 5. D.C. Coupled Offset Adjustment
Unadjusted Offset
Reading
Resistor Value
0mV to 10mV
11mV to 30mV
31mV to 50mV
51mV to 70mV
71mV to 90mV
91mV to 110mV
no resistor needed
20.0kΩ
Insufficient clock levels will result in poor dynamic perfor-
mance. Excessively high clock levels could cause a change
in the analog input offset voltage. To avoid these problems,
keep the clock level within the range specified as VID in the
Converter Electrical Characteristics.
10.0kΩ
6.81kΩ
4.75kΩ
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC081500 features
a duty cycle clock correction circuit which can maintain per-
formance over temperature. The ADC will meet its perfor-
mance specification if the input clock high and low times are
maintained within the duty cycle range as specified in the
Converter Electrical Characteristics.
3.92kΩ
2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on the output bus
would be outside the range of 00h to FFh.
High speed, high performance ADCs such as the ADC081500
require a very stable input clock signal with minimum phase
noise or jitter. ADC jitter requirements are defined by the ADC
resolution (number of bits), maximum ADC input frequency
and the input signal amplitude relative to the ADC input full
scale range. The maximum jitter (the sum of the jitter from all
sources) allowed to prevent a jitter-induced reduction in SNR
is found to be
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC081500 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC081500 such that the differential full-scale
input range at the analog inputs is a normal amplitude with
the FSR pin high, or a reduced amplitude with FSR pin low as
defined by the specification VIN in the Converter Electrical
Characteristics. Best SNR is obtained with FSR high, but bet-
ter distortion and SFDR are obtained with the FSR pin low.
tJ(MAX) = (VINFSR / VIN(P-P)) x (1/(2(N+1) x π x fIN))
where tJ(MAX) is the rms total of all jitter sources in seconds,
VIN(P-P) is the peak-to-peak analog input signal, VINFSR is the
full-scale range of the ADC, "n" is the ADC resolution in bits
and fIN is the maximum input frequency, in Hertz, to the ADC
analog input.
2.3 THE CLOCK INPUTS
The ADC081500 has differential LVDS clock inputs, CLK+
and CLK-, which must be driven with an a.c. coupled, differ-
ential clock signal. Although the ADC081500 is tested and its
performance is guaranteed with a differential 1.5 GHz clock,
it typically will function well with input clock frequencies indi-
cated in the Converter Electrical Characteristics. The clock
inputs are internally terminated and biased. The input clock
Note that the maximum jitter described above is the arithmetic
sum of the jitter from all sources, including that in the ADC
input clock, that added by the system to the ADC input clock
and input signals and that added by the ADC itself. Since the
effective jitter added by the ADC is beyond user control, the
best the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
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Input clock amplitudes above those specified in the Converter
Electrical Characteristics may result in increased input offset
voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
2.4.2.2 for best performance, a self calibration should be per-
formed 20 seconds or more after power up and repeated
when the operating temperature changes significantly ac-
cording to the particular system performance requirements.
ENOB drops slightly as junction temperature increases and
executing a new self calibration cycle will essentially eliminate
the change.
2.4 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the
ADC081500 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Calibration, Calibration Delay,
Output Edge Synchronization choice, LVDS Output Level
choice and a Power Down feature.
During a Power-On calibration cycle, both the ADC and the
input termination resistor are calibrated. As ENOB changes
slightly with junction temperature, an On-Command calibra-
tion can be executed to bring the performance of the ADC in
line.
2.4.2.3 Calibration Delay
2.4.1 Full-Scale Input Range Setting
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in Section 1.1.1. The calibration delay values
allow the power supply to come up and stabilize before cali-
bration takes place. With no delay or insufficient delay, cali-
bration would begin before the power supply is stabilized at
its operating value and result in non-optimal calibration coef-
ficients. If the PD pin is high upon power-up, the calibration
delay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
The input full-scale range can be selected with the FSR con-
trol input (pin 14) in the normal mode of operation. The is
specified as VIN in the Converter Electrical Characteristics. In
the extended control mode, the input full-scale range may be
programmed using the Full-Scale Adjust Voltage register.
See Section 2.2 for more information.
2.4.2 Self Calibration
The ADC081500 self-calibration must be run to achieve spec-
ified performance. The calibration procedure is run upon pow-
er-up and can be run any time on command. The calibration
procedure is exactly the same whether there is an input clock
present upon power up or if the clock begins some time after
application of power. The CalRun output indicator is high
while a calibration is in progress. Note that DCLK outputs are
not active during a calibration cycle, therefore it is not recom-
mended as a system clock.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that DCLK signal can be used to latch the output data
into the receiving circuit.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC081500 will function with the CAL pin held high
at power up, but no calibration will be done and performance
will be impaired. A manual calibration, however, may be per-
formed after powering up with the CAL pin high. See On-
Command Calibration Section 2.4.2.2.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
At the very high speeds of which the ADC081500 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
2.4.2.2 On-Command Calibration
To initiate an on-command calibration, bring the CAL pin high
for a minimum of tCAL_H input clock cycles after it has been
low for a minimum of tCAL_L input clock cycles. Holding the
CAL pin high upon power up will prevent execution of power-
on calibration until the CAL pin is low for a minimum of
tCAL_L input clock cycles, then brought high for a minimum of
another tCAL_H input clock cycles. The calibration cycle will
begin tCAL_H input clock cycles after the CAL pin is thus
brought high. The CalRun signal should be monitored to de-
termine when the calibration cycle has completed.
For short LVDS lines and low noise systems, satisfactory per-
formance may be realized with the OutV input low. If the LVDS
lines are long and/or the system in which the ADC081500 is
used is noisy, it may be necessary to tie the OutV pin high.
2.4.5 Power Down Feature
The Power Down pin (PD) suspends device operation and
puts the ADC081500 into a minimum power dissipation state.
See Section 1.1.7 for details on the power down feature.
The digital data (+/-) output pins are put into a high impedance
state when the PD pin is high. Upon return to normal opera-
The minimum tCAL_H and tCAL_L input clock cycle sequences
are required to ensure that random noise does not cause a
calibration to begin when it is not desired. As mentioned in ??
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28
tion, the pipeline will contain meaningless information and
must be flushed.
2.6.1 Supply Voltage
The ADC081500 is specified to operate with a supply voltage
of 1.9V ±0.1V. It is very important to note that, while this de-
vice will function with slightly higher supply voltages, these
higher supply voltages may reduce product lifetime.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state.
No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground by more than 150 mV, not
even on a transient basis. This can be a problem upon appli-
cation of power and power shut-down. Be sure that the sup-
plies to circuits driving any of the input pins, analog or digital,
do not come up any faster than does the voltage at the
ADC081500 power pins.
2.5 THE DIGITAL OUTPUTS
The ADC081500 demultiplexes the converter output data into
two LVDS output buses. The results of successive conver-
sions started on the odd falling edges of the CLK+ pin are
available on one of the two LVDS buses, while the results of
conversions started on the even falling edges of the CLK+ pin
are available on the other LVDS bus. This means that, the
word rate at each LVDS bus is 1/2 the ADC081500 input clock
rate and the two buses must be multiplexed to obtain the en-
tire 1.5 GSPS conversion result.
The Absolute Maximum Ratings should be strictly observed,
even during power up and power down. A power supply that
produces a voltage spike at turn-on and/or turn-off of power
can destroy the ADC081500. The circuit of Figure 15 will pro-
vide supply overshoot protection.
Many linear regulators will produce output spiking at power-
on unless there is a minimum load provided. Active devices
draw very little current until their supply voltages reach a few
hundred millivolts. The result can be a turn-on spike that can
destroy the ADC081500, unless a minimum load is provided
for the supply. The 100Ω resistor at the regulator output pro-
vides a minimum output current during power-up to ensure
there is no turn-on spiking.
Since the minimum recommended input clock rate for this
device is 200 MHz, the effective data rate can be reduced to
as low as 100 MSPS by using the results available on just one
of the output buses with a 200 MHz input clock, decimating
the 200 MSPS data by two.
In the circuit of Figure 15, an LM317 linear regulator is satis-
factory if its input supply voltage is 4V to 5V . If a 3.3V supply
is used, an LM1086 linear regulator is recommended.
There is one LVDS output clock pair (DCLK+/-) available for
use to latch the LVDS outputs on all buses. Whether the data
is sent at the rising or falling edge of DCLK is determined by
the sense of the OutEdge pin, as described in Section 2.4.3.
DDR (Double Data Rate) clocking can also be used. In this
mode a word of data is presented with each edge of DCLK,
reducing the DCLK frequency to 1/4 the input clock frequency.
See the Timing Diagram section for details.
The OutV pin is used to set the LVDS differential output levels.
See Section 2.4.4.
The output format is Offset Binary. Accordingly, a full-scale
input level with VIN+ positive with respect to VIN− will produce
an output code of all ones, a full-scale input level with VIN−
positive with respect to VIN+ will produce an output code of all
zeros and when VIN+ and VIN− are equal, the output code will
vary between codes 127 and 128.
20153154
FIGURE 15. Non-Spiking Power Supply
The output drivers should have a supply voltage, VDR, that is
within the range specified in the Operating Ratings table. This
voltage should not exceed the VA supply voltage.
2.6 POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A 33 µF
capacitor should be placed within an inch (2.5 cm) of the A/D
converter power pins. A 0.1 µF capacitor should be placed as
close as possible to each VA pin, preferably within one-half
centimeter. Leadless chip capacitors are preferred because
they have low lead inductance.
If the power is applied to the device without an input clock
signal present, the current drawn by the device might be be-
low 200 mA. This is because the ADC081500 gets reset
through clocked logic and its initial state is unknown. If the
reset logic comes up in the "on" state, it will cause most of the
analog circuitry to be powered down, resulting in less than
100 mA of current draw. This current is greater than the power
down current because not all of the ADC is powered down.
The device current will be normal after the input clock is es-
tablished.
The VA and VDR supply pins should be isolated from each
other to prevent any digital noise from being coupled into the
analog portions of the ADC. A ferrite choke, such as the JW
Miller FB20009-3B, is recommended between these supply
lines when a common source is used for them.
2.6.2 Thermal Management
The ADC081500 is capable of impressive speeds and per-
formance at very low power levels for its speed. However, the
power consumption is still high enough to require attention to
thermal management. For reliability reasons, the die temper-
ature should be kept to a maximum of 130°C. That is, TA
(ambient temperature) plus ADC power consumption times
θJA (junction to ambient thermal resistance) should not ex-
ceed 130°C. This is not a problem if the ambient temperature
is kept to a maximum of +85°C as specified in the Operating
Ratings section.
As is the case with all high speed converters, the ADC081500
should be assumed to have little power supply noise rejection.
Any power supply used for digital circuitry in a system where
a lot of digital power is being consumed should not be used
to supply power to the ADC081500. The ADC supplies should
be the same supply used for other analog circuitry, if not a
dedicated supply.
29
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As a convenience to the user, the ADC081500 incorporates
a thermal diode to aid in temperature measurement. Howev-
er, this diode has not been characterized and National Semi-
conductor has no information to provide regarding its
characteristics. Hence, no information is available as to the
temperature accuracy attainable when using this diode.
be barrel plated to avoid solder wicking into the vias during
the soldering process as this wicking could cause voids in the
solder between the package exposed pad and the thermal
land on the PCB. Such voids could increase the thermal re-
sistance between the device and the thermal land on the
board, which would cause the device to run hotter.
Please note that the following are general recommendations
for mounting exposed pad devices onto a PCB. This should
be considered the starting point in PCB and assembly pro-
cess development. It is recommended that the process be
developed based upon past experience in package mounting.
If it is desired to monitor die temperature, a temperature sen-
sor may be mounted on the heat sink area of the board near
the thermal vias. Allow for a thermal gradient between the
temperature sensor and the ADC081500 die of θJ-PAD times
typical power consumption = 2.8 x 1.2 = 3.4°C. Allowing for a
5°C temperature drop (including an extra 1.6°C margin) from
the die to the temperature sensor, then, would mean that
maintaining a maximum pad temperature reading of 125°C
will ensure that the die temperature does not exceed 130°C,
assuming that the exposed pad of the ADC081500 is properly
soldered down and the thermal vias are adequate. (The in-
accuracy of the temperature sensor is in addition to the above
calculation).
The package of the ADC081500 has an exposed pad on its
back that provides the primary heat removal path as well as
excellent electrical grounding to the printed circuit board. The
land pattern design for lead attachment to the PCB should be
the same as for a conventional LQFP, but the exposed pad
must be attached to the board to remove the maximum
amount of heat from the package, as well as to ensure best
product parametric performance.
To maximize the removal of heat from the package, a thermal
land pattern must be incorporated on the PC board within the
footprint of the package. The exposed pad of the device must
be soldered down to ensure adequate heat conduction out of
the package. The land pattern for this exposed pad should be
at least as large as the 5 x 5 mm of the exposed pad of the
package and be located such that the exposed pad of the
device is entirely over that thermal land pattern. This thermal
land pattern should be electrically connected to ground. A
clearance of at least 0.5 mm should separate this land pattern
from the mounting pads for the package pins.
2.7 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. A single ground plane
should be used, instead of splitting the ground plane into ana-
log and digital areas.
Since digital switching transients are composed largely of
high frequency components, the skin effect tells us that total
ground plane copper weight will have little effect upon the
logic-generated noise. Total surface area is more important
than is total ground plane volume. Coupling between the typ-
ically noisy digital circuitry and the sensitive analog circuitry
can lead to poor performance that may seem impossible to
isolate and remedy. The solution is to keep the analog cir-
cuitry well separated from the digital circuitry.
High power digital components should not be located on or
near any linear component or power supply trace or plane that
services analog or mixed signal components as the resulting
common return current path could cause fluctuation in the
analog input “ground” return of the ADC, causing excessive
noise in the conversion result.
Generally, we assume that analog and digital lines should
cross each other at 90° to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid
crossing analog and digital lines altogether. The input clock
lines should be isolated from ALL other lines, analog AND
digital. The generally accepted 90° crossing should be avoid-
ed as even a little coupling can cause problems at high
frequencies. Best performance at high frequencies is ob-
tained with a straight signal path.
20153121
FIGURE 16. Recommended Package Land Pattern
Since a large aperture opening may result in poor release, the
aperture opening should be subdivided into an array of small-
er openings, similar to the land pattern of Figure 16.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. This is
especially important with the low level drive required of the
ADC081500. Any external component (e.g., a filter capacitor)
connected between the converter's input and ground should
be connected to a very clean point in the analog ground plane.
All analog circuitry (input amplifiers, filters, etc.) should be
separated from any digital components.
To minimize junction temperature, it is recommended that a
simple heat sink be built into the PCB. This is done by includ-
ing a copper area of about 2 square inches (6.5 square cm)
on the opposite side of the PCB. This copper area may be
plated or solder coated to prevent corrosion, but should not
have a conformal coating, which could provide some thermal
insulation. Thermal vias should be used to connect these top
and bottom copper areas. These thermal vias act as "heat
pipes" to carry the thermal energy from the device side of the
board to the opposite side of the board where it can be more
effectively dissipated. The use of 9 to 16 thermal vias is rec-
ommended.
2.8 DYNAMIC PERFORMANCE
The ADC081500 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications and avoid
jitter-induced noise, the clock source driving the CLK input
must exhibit low rms jitter. The allowable jitter is a function of
the input frequency and the input signal level, as described in
Section 2.3.
The thermal vias should be placed on a 1.2 mm grid spacing
and have a diameter of 0.30 to 0.33 mm. These vias should
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30
It is good practice to keep the ADC input clock line as short
as possible, to keep it well away from any other signals and
to treat it as a transmission line. Other signals can introduce
jitter into the input clock signal. The clock signal can also in-
troduce noise into the analog path if not isolated from that
path.
2.10 COMMON APPLICATION PITFALLS
Failure to write all register locations when using extend-
ed control mode. When using the serial interface, all 3 user
registers must be written at least once with the default or de-
sired values before calibration and subsequent use of the
ADC. Once all registers have been written once, other desired
settings can be loaded.
Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than offered by the package pins.
Driving the inputs (analog or digital) beyond the power
supply rails.For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
2.9 USING THE SERIAL INTERFACE
The ADC081500 may be operated in the Normal control mode
(using control pins) or in the Extended control mode (using a
serial interface and register set). Table 6 and Table 7 describe
the functions of pins 3, 4, 14 and 127 in the Normal control
mode and the Extended control mode, respectively.
Care should be taken not to overdrive the inputs of the
ADC081500. Such practice may lead to conversion inaccu-
racies and even to device damage.
2.9.1 Normal Control Mode Operation
Normal control mode operation means that the Serial Inter-
face is not active and all controllable functions are controlled
with various pin settings. That is, the full-scale range, the
power on calibration delay, the output voltage and the input
coupling (a.c. or d.c.). The Normal control mode is used by
setting pin 14 high or low, as opposed to letting it float. Table
6 indicates the pin functions of the ADC081500 in the Normal
control mode.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in section 1.3 and 3.0, the Input
common mode voltage must remain within 50 mV of the VCMO
output, which has a variability with temperature that must also
be tracked. Distortion performance will be degraded if the in-
put common mode voltage is more than 50 mV from VCMO
.
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC081500 as many high speed amplifiers will have
higher distortion than will the ADC081500, resulting in overall
system performance degradation.
TABLE 6. Normal Control Mode Operation
(Pin 14 High or Low)
Pin
Low
High
Floating
Reduced
VOD
Normal VOD
3
n/a
Driving the VBG pin to change the reference voltage. As
mentioned in Section 2.1, the reference voltage is intended to
be fixed by FSR pin or Full-Scale Voltage Adjust register set-
tings. Over driving this pin will not change the full scale value,
but can otherwise upset operation.
OutEdge =
Neg
OutEdge =
Pos
4
DDR
n/a
127
14
CalDly Short CalDly Long
Driving the clock input with an excessively high level
signal. The ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change.
Extended
Control Mode
Reduced VIN Normal VIN
Pin 3 can be either high or low in the Normal control mode.
Pin 14 must not be left floating to select this mode. See Sec-
tion 1.2 for more information.
Inadequate input clock levels. As described in Section 2.3,
insufficient input clock levels can result in poor performance.
Excessive input clock levels could result in the introduction of
an input offset.
Pin 4 can be high or low or can be left floating in the Normal
control mode. In the Normal control mode, pin 4 high or low
defines the edge at which the output data transitions. See
Section 2.4.3 for more information. If this pin is floating, the
output clock (DCLK) is a DDR (Double Data Rate) clock (see
Section 1.1.5.3) and the output edge synchronization is irrel-
evant since data is clocked out on both DCLK edges.
Using a clock source with excessive jitter, using an ex-
cessively long input clock signal trace, or having other
signals coupled to the input clock signal trace. This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Pin 127 in the non-extended control mode sets the calibration
delay. Pin 127 is not designed to remain floating.
Failure to provide adequate heat removal. As described in
Section 2.6.2, it is important to provide adequate heat removal
to ensure device reliability. This can be done either with ad-
equate air flow or the use of a simple heat sink built into the
board. The backside pad should be grounded for best perfor-
mance.
TABLE 7. Extended Control Mode Operation
(Pin 14 Floating)
Pin
3
Function
SCLK (Serial Clock)
4
SDATA (Serial Data)
127
SCS (Serial Interface Chip Select)
31
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Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB.
128-Lead Exposed Pad LQFP
Order Number ADC081500CIYB
NS Package Number VNX128A
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Notes
33
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