54FCT273PCX [NSC]
Octal D Flip-Flop; 八路D触发器
| 型号： | 54FCT273PCX |
| 厂家： | 
National Semiconductor |
| 描述： | Octal D Flip-Flop |
| 文件： | 总8页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1993
54FCT/74FCT273
Octal D Flip-Flop
General Description
Features
Y
CC
I
reduced to 40.0 mA
The ’FCT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
Y
Y
Y
Y
Y
Y
Y
Y
Ideal buffer for MOS microprocessor or memory
Eight edge-triggered D flip-flops
Buffered common clock
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put.
Buffered, asynchronous master reset
TTL input and output level compatible
TTL levels accept CMOS levels
e
I
48 mA (Com), 32 mA (Mil)
OL
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
NSC 54/74FCT273 is pin and functionally equivalent to
IDT 54/74FCT273
Y
Military product compliant to MIL-STD-883 and
Ý
Standard Military Drawing 5962-87656
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
TL/F/10146–1
TL/F/10146–2
TL/F/10146–3
Pin Names
Description
Pin Assignment
for LCC
D –D
0
Data Inputs
7
MR
CP
Master Reset
Clock Pulse Input
Data Outputs
Q –Q
0
7
TL/F/10146–4
FACTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/10146
RRD-B30M105/Printed in U. S. A.
Mode Select-Function Table
Inputs
Outputs
Operating Mode
MR
L
CP
X
D
Q
n
n
e
e
e
Reset (Clear)
Load ‘1’
X
L
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
H
L
L
H
L
H
L
X
e
L
LOW-to-HIGH Transition
Load ‘0’
H
Logic Diagram
TL/F/10146–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
54FCT
74FCT
)
CC
4.5V to 5.5V
4.75 to 5.25V
Terminal Voltage with Respect to GND
)
(V
TERM
54FCT
74FCT
Input Voltage
0V to V
CC
CC
b
b
a
0.5 to 7.0V
a
0.5 to 7.0V
Output Voltage
0V to V
Operating Temperature (T )
A
54FCT
74FCT
Temperature Under Bias (T
74FCT
54FCT
)
BIAS
b
a
55 C to 125 C
§
0 C to 70 C
§
b
b
a
55 C to 125 C
§
§
a
§
§
a
65 C to 135 C
§
§
Junction Temperature (T )
J
Storage Temperature (T
74FCT
54FCT
)
STG
CDIP
PDIP
175 C
§
b
b
a
55 C to 125 C
§
§
§
140 C
§
Note: All commercial packaging is not recommended for applications requir-
a
65 C to 150 C
§
120 mA
DC Output Current (I
OUT
)
b
a
ing greater than 2000 temperature cycles from 40 C to 125 C.
§
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM FCT circuits outside databook specifications.
DC Characteristics for ’FCT Family Devices
CC
e
specified for the appropriate device type: Com: V
Typical values are at V
5.0V, 25 C ambient and maximum loading. For test conditions shown as Max, use the value
§
e
e
a
0 C to 70 C; Mil: V
e
e b
5.0V 10%, T 55 C
A
g
5.0V 5%, T
g
§
§
§
CC
A
CC
a
to 125 C, V
e
b
V
CC
0.2V
§
HC
54FCT/74FCT
Typ
Symbol
Parameter
Units
Conditions
Min
Max
V
Minimum High Level
Input Voltage
IH
IL
2.0
V
V
V
Maximum Low Level
Input Voltage
0.8
e
e
e
e
I
I
Input High Current
5.0
5.0
V
V
Max
V
V
V
CC
IH
CC
I
mA
mA
2.7V (Note 2)
I
b
b
e
e
Input Low Current
5.0
5.0
Max
V
V
0.5V (Note 2)
GND
IL
CC
I
I
b
b
e
e
e
e b
Min; I 18 mA
N
V
Clamp Diode Voltage
Short Circuit Current
0.7
1.2
V
V
V
V
IK
CC
CC
CC
b
b
e
Max (Note 1); V GND
O
I
60
120
mA
OS
e
V
OH
Minimum High Level
Output Voltage
2.8
3.0
3V; V
0.2V or V ;
HC
IN
e b
I
32 mA
OL
V
e
e b
e b
e b
V
V
V
V
Min
I
I
I
300 mA
HC
CC
CC
OH
OH
OH
e
2.4
2.4
4.3
V
or V
IL
12 mA (Mil)
15 mA (Com)
IN
IH
4.3
3
DC Characteristics for ’FCT Family Devices (Continued)
e
specified for the appropriate device type: Com: V
Typical values are at V
5.0V, 25 C ambient and maximum loading. For test conditions shown as Max, use the value
e
§
CC
e
e
a
0 C to 70 C; Mil: V
e b
55 C
g
5.0V 5%, T
g
5.0V 10%, T
§
§
§
CC
A
CC
A
a
to 125 C, V
e
b
V
CC
0.2V
§
HC
54FCT/74FCT
Symbol
Parameter
Units
Conditions
Min
Typ
Max
e
CC
e
0.2V or V
HC
V
OL
Maximum Low Level
Output Voltage
GND
0.2
V
3V; V
IN
;
e
I
300 mA
OL
V
e
e
e
e
GND
0.3
0.2
0.5
0.5
V
V
Min
I
I
I
300 mA
CC
OL
OL
OL
e
V
or V
IL
48 mA (Mil)
IN
IH
0.3
32 mA (Com)
e
I
Maximum Quiescent
Supply Current
V
V
Max
CC
CC
t
s
0.2V
1.0
0.5
40.0
2.0
mA
V
, V
HC IN
IN
e
f
I
0
e
DI
Quiescent Supply Current;
TTL Inputs HIGH
V
V
Max
CC
CC
mA
e
3.4V (Note 3)
IN
t
s
I
Dynamic Power
V
Max
V
V
V
HC
0.2V
CCD
CC
IN
Supply Current (Note 4)
Outputs Open
IN
e
V
CC
0.25
0.40
mA/MHz
mV
MR
One Input Toggling
50% Duty Cycle
V
H
Input Hysteresis
on Clock Only
200
1.5
t
s
e
Outputs Open
I
Total Power
V
CC
Max
V
V
V
HC
C
IN
Supply Current (Note 6)
4.0
6.0
7.8
0.2V
IN
e
MR
V
CC
e
e
e
f
I
10 MHz
V
V
3.4V
GND
IN
1.8
3.0
One Bit Toggling
50% Duty Cycle
IN
mA
t
s
(Note 5)
e
Outputs Open
V
V
V
HC
IN
V
Max
0.2V
CC
IN
e
MR
V
CC
e
e
e
f
I
2.5 MHz
V
V
3.4V
GND
IN
5.0
16.8
Eight Bits Toggling
50% Duty Cycle
IN
V
H
Input Hysteresis on Clock Only
200
mV
Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time.
Note 2: This parameter guaranteed but not tested.
e
Note 3: Per TTL driven input (V
3.4V); all other inputs at V
or GND.
CC
IN
Note 4: This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Note 5: Values for these conditions are examples of the I formula. These limits are guaranteed but not tested.
CC
e
e
a
a
I
INPUTS DYNAMIC
Note 6: I
I
I
C
QUIESCENT
a
a
a
I (f /2 f
CCD CP I
I
I
I
DI
D
H
N
N )
I
C
CC
CC
T
e
Quiescent Current
CC
e
e
3.4V)
DI
CC
Power Supply Curent for a TTL High Input (V
IN
e
e
D
Duty Cycle for TTL inputs High
H
T
N
Number of Inputs at D
H
e
I
Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
Clock Frequency for Register Devices (Zero for Non-Register Devices)
CCD
e
f
CP
e
f
I
Input Frequency
e
N
Number of Inputs at f
I
I
All currents are in milliamps and all frequencies are in megahertz.
4
AC Electrical Characteristics
54FCT/74FCT
74FCT
54FCT
e
e
Mil
T
, V
Com
T , V
A CC
A
CC
e
e
e a
e
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
R
500X
R
500X
Units
L
L
L
V
CC
C
50 pF
C
50 pF
L
Typ
Min
Max
Min
Max
t
t
Propagation Delay
Clock to Output
PHL
7.0
2.0
13.0
13.0
1.5
1.5
3.5
2.0
5.0
5.0
9.5
ns
ns
ns
ns
ns
ns
PLH
t
t
Propagation Delay
MR to Output
PLH
8.0
1.5
1.0
4.0
4.0
3.0
2.0
3.0
2.0
7.0
7.0
4.0
10.5
PHL
t
t
t
t
t
f
Setup Time HIGH
or LOW Data to CP
SU
Hold Time HIGH
h
or LOW Data to CP
Clock Pulse Width
HIGH or LOW
w
MR Pulse Width
HIGH or LOW
w
Recovery Time
MR to CP
rec
4.0
90
ns
Maximum Clock Frequency
MHz
max
Note 1: Minimum limits are guaranteed but not tested on Propagation Delays.
e
e
Capacitance T
25 C, f
§
1.0 MHz
A
Symbol
Parameter
Conditions Typ Max Unit
e
C
C
Input Capacitance
Output Capacitance
V
V
0V
6
8
10
12
pF
pF
IN
IN
e
0V
OUT
OUT
Note: This parameter is guaranteed by characterization data and not tested.
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74FCT 273
P
C
QR
Temperature Range Family
Special Variations
e
e
e
e
74FCT
54FCT
Commercial TTL-Compatible
Military TTL-Compatible
X
QR
Devices shipped in 13 reels
×
Commercial grade device with
burn-in
Military grade with
Device Type
e
QB
environmental and burn-in
processing shipped in tubes.
Package Code
e
e
e
e
e
P
D
F
L
Plastic DIP
Ceramic DIP
Flatpak
Leadless Ceramic Chip Carrier (LCC)
Small Outline (SOIC)
Temperature Range
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
S
5
Physical Dimensions inches (millimeters)
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
6
Physical Dimensions inches (millimeters) (Continued)
20-Lead Small Outline Integrated Circuit (S)
NS Package Number M20B
20-Lead Plastic Dual-In-Line Package (P)
NS Package Number N20B
7
Ý
Lit. 114706
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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