54F648SDM [NSC]
Octal Transceiver/Register with TRI-STATE Outputs; 八路收发器/寄存器具有三态输出型号: | 54F648SDM |
厂家: | National Semiconductor |
描述: | Octal Transceiver/Register with TRI-STATE Outputs |
文件: | 总12页 (文件大小:204K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
December 1994
54F/74F646 74F646B 54F/74F648
#
#
Octal Transceiver/Register with TRI-STATE Outputs
É
General Description
Features
Y
Independent registers for A and B buses
These devices consist of bus transceiver circuits with TRI-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control G and direction pins are provid-
ed to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus will
receive data when the enable control G is Active LOW. In
the isolation mode (control G HIGH), A data may be stored
in the B register and/or B data may be stored in the A regis-
ter.
Y
Multiplexed real-time and stored data
Y
’F648 has inverting data paths
Y
’F646/’F646B have non-inverting data paths
Y
’F646B is a faster version of the ’F646
Y
TRI-STATE outputs
Y
300 mil slim DIP
Y
Guaranteed 4000V minimum ESD protection
Package
Number
Commercial
74F646SPC
Military
Package Description
N24C
J24F
24-Lead (0.300 Wide) Molded Dual-In-Line
×
54F646DM (Note 2)
24-Lead (0.300 Wide) Ceramic Dual-In-Line
×
74F646SC (Note 1)
74F646MSA (Note 1)
M24B
MSA24
W24C
E28A
N24C
M24B
N24C
J24F
24-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
24-Lead Molded Shrink Small Outline, EIAJ, Type II
54F646FM (Note 2)
54F646LM (Note 2)
24-Lead Cerpack
28-Lead Ceramic Leadless Chip Carrier, Type C
74F646BSPC
24-Lead (0.300 Wide) Molded Dual-In-Line
×
74F646BSC (Note 1)
74F648SPC
24-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
24-Lead (0.300 Wide) Molded Dual-In-Line
×
54F648SDM (Note 2)
24-Lead (0.300 Wide) Ceramic Dual-In-Line
×
74F648SC (Note 1)
M24B
W24C
E28A
24-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
54F648FM (Note 2)
54F648LM (Note 2)
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
SCX.
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
’F646/’F646B
’F648
TL/F/9580–1
TL/F/9580–7
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9580
RRD-B30M75/Printed in U. S. A.
Logic Symbols (Continued)
IEEE/IEC
’F646/’F646B
IEEE/IEC
’F648
TL/F/9580–9
TL/F/9580–4
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
’F646/’F646B
Pin Assignment
for DIP, SOIC and Flatpak
’F648
TL/F/9580–2
TL/F/9580–8
Pin Assignment
for LCC
’F646/’F646B
Pin Assignment
for LCC
’F648
TL/F/9580–3
TL/F/9580–10
2
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
A –A
0
Data Register A Inputs/
TRI-STATE Outputs
Data Register B Inputs/
TRI-STATE Outputs
3.5/1.083
600/106.6 (80)
3.5/1.083
600/106.6 (80)
1.0/1.0
70 mA/ 650 mA
7
b
b
12 mA/64 mA (48 mA)
b
B –B
0
70 mA/ 650 mA
7
12 mA/64 mA (48 mA)
b
20 mA/ 0.6 mA
CPAB, CPBA Clock Pulse Inputs
b
20 mA/ 0.6 mA
SAB, SBA
Select Inputs
1.0/1.0
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
G
Output Enable Input
Direction Control Input
1.0/1.0
DIR
1.0/1.0
Function Table
Inputs
Data I/O*
Function
G
DIR
CPAB
CPBA
SAB
SBA
A –A
0
B –B
0 7
7
H
H
H
X
X
X
H or L
L
X
H or L
X
X
X
X
X
X
X
Isolation
Input
Input
Input
Clock A Data into A Register
n
L
Clock B Data into B Register
n
L
L
L
L
H
H
H
H
X
X
X
X
X
L
L
X
X
X
X
A to B ÐReal Time (Transparent Mode)
n n
L
H or L
Clock A Data into A Register
n
Output
H
H
A Register to B (Stored Mode)
n
L
Clock A Data into A Register and Output to B
n
n
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
B to A ÐReal Time (Transparent Mode)
n n
L
H or L
Clock B Data into B Register
n
Output
Input
H
H
B Register to A (Stored Mode)
n
L
Clock B Data into B Register and Output to A
n
n
*The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus
pins will be stored on every LOW-to-HIGH transition of the clock inputs.
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Irrelevant
X
e
L
LOW-to-HIGH Transition
3
Logic Diagrams (Continued)
’F646/’F646B
TL/F/9580–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
4
Logic Diagrams (Continued)
’F648
TL/F/9580–6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Typ
Symbol
Parameter
Units
V
CC
Conditions
Min
Max
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
V
V
V
Input LOW Voltage
0.8
IL
b
e b
18 mA (Non I/O Pins)
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
Output HIGH
Voltage
54F 10% V
2.0
2.0
I
I
12 mA (A , B )
n n
CC
OH
OH
V
V
74F 10% V
15 mA (A , B )
n n
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
0.55
0.55
I
I
48 mA (A , B )
n n
64 mA (A , B )
OL
CC
OL
Min
Max
Max
Max
Max
0.0
CC
OL
n
n
e
e
e
I
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
V
2.7V (Non I/O Pins)
7.0V (Non I/O Pins)
IH
IN
IN
IN
mA
mA
mA
mA
V
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
BVI
Input HIGH Current
Breakdown (I/O)
54F
74F
1.0
0.5
5.5V (A , B )
n n
BVIT
CEX
e
V
CC
Output HIGH
54F
74F
250
50
OUT
Leakage Current
e
All Other Pins Grounded
V
Input Leakage
Test
I
ID
1.9 mA
ID
OD
IL
74F
74F
4.75
e
All Other Pins Grounded
I
Output Leakage
Circuit Current
V
IOD
150 mV
3.75
mA
0.0
b
e
0.5V (Non I/O Pins)
I
I
I
I
I
I
I
I
Input LOW Current
0.6
mA
mA
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
0.0V
Max
Max
Max
V
V
V
V
V
V
V
V
IN
a
e
2.7V (A , B )
I
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
70
IH
IL
OZH
OUT
OUT
OUT
OUT
n
n
a
b
b
e
e
e
I
650
225
0.5V (A , B )
n n
OZL
b
100
0V
OS
500
5.25V
ZZ
e
Power Supply Current
Power Supply Current
Power Supply Current
135
150
150
HIGH
LOW
CCH
CCL
CCZ
O
e
O
e
HIGH Z
O
6
’F646/’F648
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
T
, V
CC
e
Mil
T
, V
Com
e
50 pF
A
A CC
e a
Symbol
Parameter
V
Units
CC
C
C
L
L
e
C
Min
90
50 pF
L
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
75
90
MHz
ns
max
t
t
Propagation Delay
Clock to Bus
2.0
2.0
7.0
8.0
2.0
2.0
8.5
9.5
2.0
2.0
8.0
9.0
PLH
PHL
t
t
Propagation Delay
Bus to Bus (’F646)
1.0
1.0
7.0
6.5
1.0
1.0
8.0
8.0
1.0
1.0
7.5
7.0
PLH
ns
ns
ns
ns
ns
ns
ns
PHL
t
t
Propagation Delay
Bus to Bus (’F648)
2.0
1.0
8.5
7.5
1.0
1.0
10.0
9.0
2.0
1.0
9.0
8.0
PLH
PHL
t
t
Propagation Delay
2.0
2.0
8.5
8.0
2.0
2.0
11.0
10.0
2.0
2.0
9.5
9.0
PLH
SBA or SAB to A or B
PHL
t
t
Enable Time
OE to A or B
2.0
2.0
8.5
2.0
2.0
10.0
13.5
2.0
2.0
9.0
PZH
12.0
12.5
PZL
t
t
Disable Time
OE to A or B
1.0
2.0
7.5
9.0
1.0
2.0
9.0
1.0
2.0
8.5
9.5
PHZ
11.0
PLZ
t
t
Enable Time
DIR to A or B
2.0
2.0
14.0
13.0
2.0
2.0
16.0
15.0
2.0
2.0
15.0
14.0
PZH
PZL
t
t
Disable Time
DIR to A or B
1.0
2.0
9.0
1.0
2.0
10.0
12.0
1.0
2.0
9.5
PHZ
11.0
11.5
PLZ
’F646/’F648
AC Operating Requirements
74F
54F
74F
e a
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
T
, V
A CC
Com
Max
Units
A
V
CC
Min
Max
Min
Max
Min
t (H)
s
Setup Time, HIGH or LOW
Bus to Clock
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
t (L)
s
t (H)
h
Hold Time, HIGH or LOW
Bus to Clock
2.0
2.0
2.5
2.5
2.0
2.0
t (L)
h
t
t
(H)
(L)
Clock Pulse Width
HIGH or LOW
5.0
5.0
5.0
5.0
5.0
5.0
w
w
7
’F646B
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
A
e
50 pF
e
T
, V
CC
e
Mil
T
, V
Com
e
50 pF
A
A CC
e a
5.0V
50 pF
Symbol
Parameter
V
Units
CC
C
C
L
L
e
C
Min
165
L
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
150
MHz
ns
max
t
t
Propagation Delay
Clock to Bus
2.5
3.0
7.0
7.5
2.5
3.0
8.0
8.0
PLH
PHL
t
t
Propagation Delay
Bus to Bus
2.0
2.0
6.0
6.0
2.0
2.0
7.0
7.0
PLH
ns
ns
ns
ns
ns
ns
PHL
t
t
Propagation Delay
2.5
2.5
7.5
7.5
2.5
2.5
8.5
8.5
PLH
SBA or SAB to A or B
PHL
t
t
Enable Time
OE to A or B
2.5
2.5
6.5
9.0
2.5
2.5
8.0
PZH
10.0
PZL
t
t
Disable Time
OE to A or B
1.5
2.0
6.5
7.0
1.5
2.0
7.5
8.5
PHZ
PLZ
t
t
Enable Time
DIR to A or B
2.0
3.0
7.0
9.5
2.0
3.0
8.5
PZH
10.0
PZL
t
t
Disable Time
DIR to A or B
1.5
2.5
7.5
8.5
1.5
2.5
8.5
9.5
PHZ
PLZ
’F646B
AC Operating Requirements
74F
54F
74F
e a
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
A CC
Com
Max
Units
A
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
Bus to Clock
5.0
5.0
4.0
4.0
ns
ns
ns
t (L)
s
t (H)
h
Hold Time, HIGH or LOW
Bus to Clock
1.5
1.5
1.5
1.5
t (L)
h
t
t
(H)
(L)
Clock Pulse Width
HIGH or LOW
5.0
5.0
5.0
5.0
w
w
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 646/646B/648
S
C
X
Temperature Range Family
Special Variations
e
e
e
74F
54F
Commercial
Military
QB
Military grade device with
environmental and burn-in
processing
Device Type
e
X
Devices shipped in 13 reel
×
Package Code
Temperature Range
e
e
e
e
e
e
e
SP
SD
S
MSA
L
Slim Plastic DIP
C
Commercial
Slim Ceramic DIP
Small Outline (SOIC)
Shrink Small Outline SOIC EIAJ Type II (M646 only)
Leadless Chip Carrier
Flatpak
a
(0 C to 70 C)
§
Military
§
e
M
b
a
55 C to 125 C)
§
(
§
F
8
Physical Dimensions inches (millimeters)
28-Lead Ceramic Leadless Chip Carrier, Type C
NS Package Number E28A
24-Lead (0.300 Wide) Ceramic Dual-In-Line Package (SD)
×
NS Package Number J24F
9
Physical Dimensions inches (millimeters) (Continued)
24-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M24B
10
Physical Dimensions inches (millimeters) (Continued)
24-Lead Molded Shrink Small Outline Package, EIAJ, Type II
NS Package Number MSA24
24-Lead (0.300 Wide) Molded Dual-In-Line Package (SP)
×
NS Package Number N24C
11
Physical Dimensions inches (millimeters) (Continued)
24-Lead Cerpack
NS Package Number W24C
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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