54F377LM [NSC]
Octal D Flip-Flop with Clock Enable; 八路D触发器与时钟使能
| 型号： | 54F377LM |
| 厂家： | 
National Semiconductor |
| 描述： | Octal D Flip-Flop with Clock Enable |
| 文件： | 总8页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1995
54F/74F377
Octal D Flip-Flop with Clock Enable
General Description
Features
Y
Ideal for addressable register applications
The ’F377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
Y
Clock enable for address and data synchronization
applications
Y
Y
Y
Y
Y
Y
Eight edge-triggered D flip-flops
Buffered common clock
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put. The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable opera-
tion.
See ’F273 for master reset version
See ’F373 for transparent latch version
See ’F374 for TRI-STATE version
É
Guaranteed 4000V minimum ESD protection
Package
Commercial
74F377PC
Military
Package Description
Number
N20A
J20A
20-Lead (0.300 Wide) Molded Dual-In-Line
×
54F377DM (QB)
20-Lead Ceramic Dual-In-Line
74F377SC (Note 1)
74F377SJ (Note 1)
M20B
M20D
W20A
E20A
20-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
54F377FM (QB)
54F377LM (QB)
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
×
SCX and SJX.
Logic Symbols
IEEE/IEC
TL/F/9525–1
TL/F/9525–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9525
RRD-B30M75/Printed in U. S. A.
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9525–3
TL/F/9525–2
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
7
CE
CP
Clock Enable (Active LOW)
Clock Pulse Input
b
20 mA/ 0.6 mA
b
Q –Q
0
Data Outputs
1 mA/20 mA
7
Mode Select-Function Table
e
e
Inputs
Output
H
h
HIGH Voltage Level
Operating Mode
HIGH Voltage Level one setup time prior to
CP
L
L
CE
D
Q
n
n
the LOW-to-HIGH Clock Transition
e
e
L
I
LOW Voltage Level
Load ‘‘1’’
Load ‘‘0’’
I
I
h
H
LOW Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
e
L
I
L
X
Immaterial
e
LOW-to-HIGH Clock Transition
Hold
L
X
h
X
X
No Change
No Change
(Do Nothing)
H
Logic Diagram
TL/F/9525–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I (mA)
OL
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Typ
Symbol
Parameter
Units
V
CC
Conditions
Min
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
IN
CD
OH
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.5
2.5
2.7
I
I
I
1 mA
1 mA
1 mA
CC
OH
OH
OH
74F 10% V
74F 5% V
V
CC
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
0.5
I
I
20 mA
20 mA
OL
CC
OL
V
Min
Max
Max
0.5
CC
OL
e
e
I
I
Input HIGH Current
5.0
mA
mA
V
2.7V
7.0V
IH
IN
IN
Input HIGH Current
Breakdown Test
V
BVI
7.0
b
e
I
I
I
Input LOW Current
0.6
mA
mA
mA
Max
Max
Max
V
V
V
0.5V
IL
IN
b
b
e
e
Output Short-Circuit Current
Output HIGH Leakage Current
Input Leakage Test
60
150
0V
OS
CEX
OUT
50
V
CC
OUT
e
All Other Pins Grounded
V
I
ID
1.9 mA
ID
4.75
V
0.0
0.0
e
IOD
I
Output Leakage Circuit Current
Power Supply Current
V
150 mV
OD
3.75
mA
mA
All Other Pins Grounded
e
e
I
I
35
44
46
56
CP
L
MR
CCH
CCL
Max
e
HIGH
D
n
3
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
Propagation Delay
130
85
105
MHz
ns
Max
t
t
3.0
4.0
7.0
9.0
2.0
3.0
8.5
2.5
3.5
7.5
9.0
PLH
CP to Q
10.5
PHL
n
AC Operating Requirements
74F
54F
74F
e a
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
A CC
Com
Max
Units
A
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
3.0
3.5
3.5
4.0
3.0
3.5
ns
ns
ns
ns
ns
t (L)
s
D to CP
n
t (H)
h
Hold Time, HIGH or LOW
D to CP
n
0.5
1.0
1.0
1.0
0.5
1.0
t (L)
h
t (H)
s
Setup Time, HIGH or LOW
CE to CP
4.1
3.5
4.0
5.0
4.1
4.0
t (L)
s
t (H)
h
Hold Time, HIGH to LOW
CE to CP
0.5
2.0
1.5
2.5
0.5
2.0
t (L)
h
t
t
(H)
(L)
Clock Pulse Width,
HIGH or LOW
6.0
6.0
5.0
5.0
6.0
6.0
w
w
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
74F 377
S
C
X
Temperature Range Family
Special Variations
e
e
e
e
74F
54F
Commercial
Military
X
QB
Devices shipped in 13 reels
×
Military grade with environmental
and burn-in processing shipped
in tubes
Device Type
Package Code
Temperature Range
e
e
e
P
D
S
Plastic DIP
Ceramic DIP
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
e
SJ
4
5
Physical Dimensions inches (millimeters)
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M20B
6
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)
×
NS Package Number M20D
7
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N20A
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