54F378 [TI]

54F378 74F378 Parallel D Register with Enable; 54F378 74F378并行D寄存器使能
54F378
型号: 54F378
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

54F378 74F378 Parallel D Register with Enable
54F378 74F378并行D寄存器使能

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54F378,74F378  
54F378 74F378 Parallel D Register with Enable  
Literature Number: SNOS192A  
January 1995  
54F/74F378  
Parallel D Register with Enable  
General Description  
The ’F378 is a 6-bit register with a buffered common En-  
able. This device is similar to the ’F174, but with common  
Enable rather than common Master Reset.  
Features  
Y
Y
Y
Y
Y
6-bit high-speed parallel register  
Positive edge-triggered D-type inputs  
Fully buffered common clock and enable inputs  
Input clamp diodes limit high-speed termination effects  
Full TTL and CMOS compatible  
Package  
Commercial  
74F378PC  
Military  
Package Decription  
Number  
N16E  
J16A  
16-Lead (0.300 Wide) Molded l-In-Line  
×
54F378DM (QB)  
16-Lead Ceramic Dual-In-Line  
74F378SC (Note 1)  
74F378SJ (Note 1)  
M16A  
M16D  
W16A  
E20A  
16-Lead (0.150 Widmall OuEDEC  
×
16-Lead (0.300 WSmaOutline, EIAJ  
×
54F378FM (QB)  
54F378LM (QB)  
16-Lead pack  
20-Lead Cerac LeadChip rrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
×
SCX and SJX.  
Logic Symbols  
on Diagrams  
Pin Assignm
DIP, SOIC and
Pin Assignment  
for LCC  
TL/F/95
IEE
TL/F/9526–2  
TL/F/9526–3  
TL/F/9526–4  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9526  
RRD-B30M75/Printed in U. S. A.  
Unit Loading/Fan Out  
54F/74F  
Pin Names  
Description  
U.L.  
Input I /I  
IH IL  
HIGH/LOW Output I /I  
OH OL  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
E
Enable Input (Active LOW)  
Data Inputs  
1.0/1.0  
1.0/1.0  
1.0/1.0  
50/33.3  
D D  
0
5
CP  
Clock Pulse Input (Active Rising Edge)  
Outputs  
b
Q Q  
0
1 mA/20 mA  
5
Functional Description  
Truth Table  
The ’F378 consists of six edge-triggered D-type flip-flops  
with individual D inputs and Q inputs. The Clock (CP) and  
Enable (E) inputs are common to all flip-flops.  
Inputs  
Output  
E
CP  
D
Q
n
n
When the E input is LOW, new data is entered into the  
register on the LOW-to-HIGH transition of the CP input.  
When the E input is HIGH the register will retain the present  
data independent of the CP input.  
H
L
L
L
L
L
X
No Change  
H
L
H
e
e
e
H
L
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
X
e
L
LOW-to-HIGH Clock Transition  
Logic Diagram  
TL/F/9526–5  
Please note that this diagram is provided only for the urstanding of logic operats and should not be used to estimate propagation delays.  
2
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales  
Office/Distributors for availability and specifications.  
Recommended Operating  
Conditions  
Free Air Ambient Temperature  
Military  
Commercial  
b
a
55 C to 125 C  
§
0 C to 70 C  
§
§
b
b
a
65 C to 150 C  
Storage Temperature  
§
§
§
§
§
a
§
a
55 C to 125 C  
Ambient Temperature under Bias  
§
Supply Voltage  
Military  
Commercial  
b
b
a
a a  
4.5V to 5.5V  
a a  
4.5V to 5.5V  
Junction Temperature under Bias  
Plastic  
55 C to 175 C  
§
§
a
55 C to 150 C  
V
Pin Potential to  
CC  
Ground Pin  
b
a
0.5V to 7.0V  
b
a
0.5V to 7.0V  
Input Voltage (Note 2)  
Input Current (Note 2)  
Voltage Applied to Output  
b
a
30 mA to 5.0 mA  
e
in HIGH State (with V  
Standard Output  
0V)  
CC  
b
0.5V to 5.5V  
0.5V to V  
CC  
b
a
TRI-STATE Output  
É
Current Applied to Output  
in LOW State (Max)  
twice the rated I (mA)  
OL  
Note 1: Absolute maximum ratings are values beyond which the device may  
be damaged or have its useful life impaired. Functional operation under  
these conditions is not implied.  
Note 2: Either voltage limit or current limit is sufficient to protect inputs.  
DC Electrical Characteristics  
54F/74F  
Symbol  
Parameter  
C  
Conditions  
Min  
Typ  
Max  
V
V
V
V
Input HIGH Voltage  
2.0  
V
Recognized as a HIGH Signal  
Recognized as a LOW Signal  
IH  
Input LOW Voltage  
0.8  
IL  
e b  
18 mA  
Input Clamp Diode Voltage  
1.2  
Min  
Min  
I
IN  
CD  
OH  
e b  
e b  
e b  
Output HIGH  
Voltage  
54F 10% V  
2.5  
2.5  
2.7  
I
I
I
1 mA  
1 mA  
1 mA  
CC  
OH  
OH  
OH  
74F 10% V  
74F 5% V  
V
CC  
CC  
e
e
V
Output LOW  
Voltage  
54F 10% V  
74F 10% V  
I
I
20 mA  
20 mA  
OL  
CC  
OL  
OL  
V
Min  
Max  
Max  
Max  
0.0  
0.5  
C
e
I
I
I
Input HIGH  
Current  
54F  
74F  
20.0  
5.0  
V
V
V
2.7V  
IH  
IN  
mA  
mA  
mA  
V
e
Input HIGH Curre
Breakdown Test  
54
7
100  
7.0  
7.0V  
BVI  
IN  
e
V
CC  
Output HIGH  
5
74F  
250  
50  
CEX  
OUT  
Leak
e
All Other Pins Grounded  
V
ID  
In
T
I
1.9 mA  
ID  
F  
F  
4.75  
e
IOD  
I
O
Cir
V
150 mV  
OD  
3.75  
mA  
0.0  
All Other Pins Grounded  
b
e
0.5V  
I
I
I
Input L
0.6  
mA  
mA  
mA  
Max  
Max  
Max  
V
V
V
IL  
IN  
b
b
e
0V  
OUT  
Output Short-Circuit Current  
Power Supply Current  
60  
150  
OS  
CCL  
e
30  
45  
LOW  
O
3
AC Electrical Characteristics  
74F  
54F  
74F  
e a  
T
25 C  
§
5.0V  
A
e
50 pF  
e
50 pF  
T
, V  
CC  
e
Mil  
T
, V  
A CC  
Com  
A
e a  
Symbol  
Parameter  
V
Units  
CC  
e
C
C
L
L
e
C
50 pF  
L
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
f
Maximum Input Frequency  
Propagation Delay  
80  
100  
70  
80  
MHz  
ns  
max  
t
t
3.0  
3.5  
5.5  
6.0  
7.5  
8.5  
3.0  
3.5  
10.0  
10.5  
3.0  
3.5  
8.5  
9.5  
PLH  
CP to Q  
PHL  
n
AC Operating Requirements  
74F  
54F  
74F  
e a  
e a  
T
25 C  
§
5.0V  
A
e
e
Symbol  
Parameter  
T
, V  
CC  
Mil  
Max  
T
, V  
A CC  
Com  
Units  
A
V
CC  
Min  
Max  
Min  
Min  
t (H)  
s
Setup Time, HIGH or LOW  
4.0  
4.0  
5.0  
5.0  
.0  
4
t (L)  
s
D to CP  
n
n
t (H)  
h
Hold Time, HIGH or LOW  
D to CP  
n
0
0
2.0  
2.0  
0
0
t (L)  
h
t (H)  
s
Setup Time, HIGH or LOW  
E to CP  
6.0  
4.5  
t (L)  
s
10.0  
13.0  
0  
ns  
ns  
t (H)  
h
Hold Time, HIGH or LOW  
E to CP  
0
0
0
0
0
0
t (L)  
h
t
t
(H)  
(L)  
CP Pulse Width  
HIGH or LOW  
4.0  
6.0  
5.0  
7.
4.0  
6.0  
w
w
Ordering Information  
The device number is used to form part of a simplified purchasing cockage type and temperature range are  
defined as follows:  
74F 78  
S
X
Temperature Range Family  
Special Variations  
e
e
e
74F  
54F  
Commercial  
Military  
QB  
Military grade device with  
environmental and burn-in  
processing  
Device Type  
e
X
Devices shipped in 13 reel  
×
Package Code  
Temperature Range  
e
e
e
e
e
P
D
F
L
Plastic DI
Ceramic
Flatpa
Leadle
Small O
Small O
e
e
a
C
M
Commercial (0 C to 70 C)  
§
§
b a  
Military ( 55 C to 125 C)  
§
§
S
e
SJ  
4
Physical Dimensions inches (millimeters)  
20-Lead Ceramic Leadlep CarriL)  
NS Package A  
16-Lead Ceramic Dual-In-Line Package (D)  
NS Package Number J16A  
5
Physical Dimensions inches (millimeters) (Continued)  
16-Lead (0.150 Wide) Molded Small Outline ackage, J
×
NS Package Number M16A  
16-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)  
×
NS Package Number M16D  
6
Physical Dimensions inches (millimeters) (Continued)  
16-Lead (0.300 Wide) Molded Dual-In-Line Package (P)  
×
NS Package Number N16E  
7
Physical Dimensions inches (millimeters) (Continued)  
16-Lead Ceramic FlatpaF)  
NS Package Number W16
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