54F273DM [NSC]
Octal D Flip-Flop; 八路D触发器
| 型号： | 54F273DM |
| 厂家： | 
National Semiconductor |
| 描述： | Octal D Flip-Flop |
| 文件： | 总8页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1995
54F/74F273
Octal D Flip-Flop
General Description
Features
Y
Ideal buffer for MOS microprocessor or memory
Eight edge-triggered D flip-flops
The ’F273 has eight edge-triggered D-type flip-flops with in-
dividual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
Y
Y
Y
Y
Y
Y
Y
Buffered common clock
Buffered, asynchronous Master Reset
See ’F377 for clock enable version
See ’F373 for transparent latch version
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put.
See ’F374 for TRI-STATE version
É
Guaranteed 4000V minimum ESD protection
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
Package
Commercial
74F273PC
Military
Package Description
Number
N20A
J20A
20-Lead (0.300 Wide) Molded Dual-In-Line
×
54F273DM (Note 2)
20-Lead Ceramic Dual-In-Line
74F273SC (Note 1)
74F273SJ (Note 1)
M20B
M20D
W20A
E20A
20-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
54F273FM (Note 2)
54F273LM (Note 2)
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
SCX and SJX.
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
IEEE/IEC
TL/F/9511–3
TL/F/9511–5
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9511
RRD-B30M75/Printed in U. S. A.
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9511–2
TL/F/9511–1
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
HIGH/LOW Output I /I
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
7
MR
CP
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
b
20 mA/ 0.6 mA
b
Q –Q
0
1 mA/20 mA
7
Mode Select-Function Table
e
e
H
HIGH Voltage Level steady state
Inputs
CP
Output
h
HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock
transition
Operating Mode
MR
L
D
Q
n
n
e
e
L
I
LOW Voltage Level steady state
LOW Voltage Level one setup time prior to the LOW-to-HIGH clock
Reset (Clear)
Load ‘1’
X
X
L
transition
e
H
L
L
h
l
H
L
X
Immaterial
e
L
LOW-to-HIGH clock transition
Load ‘0’
H
Logic Diagram
TL/F/9511–4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
ESD Last Passing Voltage (min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Typ
Symbol
Parameter
Units
V
CC
Conditions
Min
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.2
Min
Min
I
I
CD
OH
IN
e b
Output HIGH
Voltage
Mil
2.5
2.5
2.7
1 mA
OH
10% V
V
V
CC
CC
5% V
CC
e
V
OL
Output LOW
Voltage
Mil
0.5
I
20 mA
OL
10% V
0.5
0.5
Min
5% V
CC
e
e
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
2.7V
7.0V
IH
IN
mA
mA
mA
V
Max
Max
Max
0.0
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
BVI
IN
e
V
CC
Output HIGH
54F
74F
250
50
CEX
OUT
Leakage Current
e
All other pins grounded
V
Input Leakage
Test
I
ID
1.9 mA
ID
74F
74F
4.75
e
IOD
I
Output Leakage
Circuit Current
V
150 mV
OD
3.75
mA
0.0
All other pins grounded
b
e
0.5V
I
I
Input LOW Current
0.6
mA
mA
Max
Max
V
IL
IN
b
b
e
0V
OUT
Output Short-Circuit Current
Power Supply Current
60
150
V
OS
e
e
I
I
44
56
CP
L
MR
CCH
CCL
mA
Max
e
HIGH
D
n
3
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
160
95
130
MHz
ns
max
t
t
Propagation Delay
Clock to Output
3.0
4.0
7.0
2.5
3.0
9.5
2.5
3.5
7.5
9.0
PLH
9.00
11.0
PHL
t
t
Propagation Delay
MR to Output
PLH
4.5
9.5
3.0
11.0
4.0
10.0
ns
PHL
AC Operating Requirements
74F
54F
74F
e a
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
, V
A CC
Com
Max
Units
A
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
Data to CP
3.0
3.5
3.5
4.0
3.0
3.5
t (L)
s
ns
t (H)
h
Hold Time, HIGH or LOW
Data to CP
0.5
1.0
1.0
1.0
0.5
1.0
t (L)
h
t
(L)
MR Pulse Width, LOW
6.0
4.0
6.0
ns
ns
ns
w
t
t
(H)
(L)
CP Pulse Width
HIGH or LOW
6.0
6.0
5.0
5.0
6.0
6.0
w
w
t
Recovery Time, MR to CP
3.0
4.5
3.5
rec
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
74F 273
S
C
X
Temperature Range Family
e
e
54F Military
Special Variations
e
e
74F Commercial
X
QB
Devices shipped in 13 reels
×
Military grade with environmental
and burn-in processing shipped
in tubes
Device Type
Package Code
Temperature Range
e
e
e
e
e
e
P
D
S
SJ
F
L
Plastic DIP
Ceramic DIP
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
Flatpak
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
Leadless Chip Carrier (LCC)
4
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (LCC)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
5
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M20B
20-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)
×
NS Package Number M20D
6
Ý
Lit. 114645
Physical Dimensions inches (millimeters) (Continued)
20-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N20A
7
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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effectiveness.
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