54ACTQ373L [NSC]
Quiet Series Octal Transparent Latch with TRI-STATE Outputs; 宁静系列八路透明锁存器与三态输出
| 型号： | 54ACTQ373L |
| 厂家： | 
National Semiconductor |
| 描述： | Quiet Series Octal Transparent Latch with TRI-STATE Outputs |
| 文件： | 总8页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1998
54ACQ373 • 54ACTQ373
Quiet Series Octal Transparent Latch with TRI-STATE®
Outputs
General Description
Features
n ICC and IOZ reduced by 50%
The ’ACQ/’ACTQ373 consists of eight latches with
TRI-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch En-
able (LE) is HIGH. When LE is low, the data satisfying the in-
put timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch up immunity
n Eight latches in a single package
n TRI-STATE outputs drive bus lines or buffer memory
address registers
The ’ACQ/’ACTQ373 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT373
n 4 kV minimum ESD immunity (’ACQ)
n Standard Military Drawing (SMD)
— ’ACTQ373: 5962-92188
™
threshold performance. FACT Quiet Series
features
™
GTO output control and undershoot corrector in addition to
a split ground bus for superior performance.
— ’ACQ373: 5962-92178
Logic Symbols
IEEE/IEC
DS100238-1
DS100238-2
Pin Names
Description
D0–D7
LE
Data Inputs
Latch Enable Input
OE
Output Enable Input
O0–O7
TRI-STATE Latch Outputs
™
GTO is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
™
FACT Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100238
www.national.com
Connection Diagrams
Pin Assignment for
DIP and Flatpak
Pin Assignment
for LCC
DS100238-4
DS100238-3
Functional Description
Truth Table
The ’ACQ/’ACTQ373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Inputs
Outputs
LE
X
OE
H
L
Dn
On
Z
X
L
H
H
L
L
L
H
X
H
L
O0
=
=
=
=
H
L
Z
X
O
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
=
Previous O before HIGH to Low transition of Latch Enable
0
0
Logic Diagram
DS100238-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’ACQ
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACTQ
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
0V to VCC
=
VI VCC + 0.5V
Operating Temperature (TA)
54ACQ/ACTQ
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
DC Output Diode Current (IOK
)
Minimum Input Edge Rate ∆V/∆t
’ACQ Devices
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
% to 70% of V
VIN from 30
CC
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
@
VCC 3.0V, 4.5V, 5.5V
125 mV/ns
125 mV/ns
Minimum Input Edge Rate ∆V/∆t
±
±
or Sink Current (IO
)
50 mA
’ACTQ Devices
VIN from 0.8V to 2.0V
DC VCC or Ground Current
per Output Pin (ICC or IGND
@
VCC 4.5V, 5.5V
)
50 mA
Note: All commercial packaging is not recommended for applications requir-
ing greater than 2000 temperature cycles from −40˚C to +125˚C.
Storage Temperature (TSTG
DC Latchup Source
or Sink Current
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
±
300 mA
175˚C
Junction Temperature (TJ)
CDIP
DC Characteristics for ’ACQ Family Devices
54ACQ
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
4.4
5.4
(Note 2)
=
VIN VIL or VIH
=
IOH −12 mA
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
=
IOH −24 mA
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 2)
=
VIN VIL or VIH
=
IOL 12 mA
3.0
4.5
5.5
5.5
0.50
0.50
0.50
=
IOL 24 mA
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
1.0
µA
VI VCC, GND
(Note 4)
3
www.national.com
DC Characteristics for ’ACQ Family Devices (Continued)
54ACQ
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
50
=
VOLD 1.65V Max
IOLD
Minimum Dynamic
(Note 3)
5.5
mA
=
VOHD 3.85V Min
IOHD
ICC
Output Current
5.5
5.5
−50
mA
µA
=
Maximum Quiescent
Supply Current
80.0
VIN VCC
or GND (Note 4)
=
IOZ
Maximum TRI-STATE
Leakage Current
VI(OE) VIL, VIH
=
±
5.5
5.0
5.0
5.0
µA
V
VI VCC, GND
=
VO VCC, GND
VOLP
Quiet Output
1.5
Maximum Dynamic VOL
Quiet Output
(Notes 5, 6)
(Notes 5, 6)
VOLV
−1.2
V
Maximum Dynamic VOL
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54ACQ 25˚C is identical to 74ACQ 25˚C.
CC
Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output GND.
Note 7: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (’ACQ). Input-under-test switching: 5V to threshold (V ), 0V to threshold (V ),
@
ILD IHD
=
f
1 MHz.
DC Characteristics for ’ACTQ Family Devices
54ACTQ
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
VIL
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 8)
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 8)
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.50
0.50
V
=
IOL 24 mA
=
±
IIN
Maximum Input
1.0
µA
µA
VI VCC, GND
Leakage Current
Maximum TRI-STATE
Leakage Current
=
±
IOZ
5.5
5.0
VI VIL, VIH
=
VO VCC, GND
www.national.com
4
DC Characteristics for ’ACTQ Family Devices (Continued)
54ACTQ
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
1.6
=
VI VCC − 2.1V
ICCT
Maximum
CC/Input
5.5
mA
I
=
VOLD 1.65V Max
IOLD
IOHD
Minimum Dynamic
5.5
5.5
50
mA
mA
=
VOHD 3.85V Min
Output Current
(Note 9)
−50
=
ICC
Maximum Quiescent
Supply Current
5.5
5.0
5.0
80.0
1.5
µA
V
VIN VCC
or GND (Note 10)
(Notes 11, 12)
(Notes 11, 12)
VOLP
Quiet Output
Maximum Dynamic VOL
Quiet Output
VOLV
−1.2
V
Minimum Dynamic VOL
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACTQ 25˚C is identical to 74ACTQ 25˚C.
Note 10:
I
CC
Note 11: Plastic DIP package.
@
Note 12: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output GND.
AC Electrical Characteristics
54ACQ
=
TA −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
Units
(Note 13)
=
CL 50 pF
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
t
t
PHL, tPLH
Propagation Delay
Dn to On
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
15.0
9.5
ns
ns
ns
ns
PHL, tPLH
Propagation Delay
LE to On
16.0
9.5
t
t
PZL, tPZH
Output Enable Time
14.5
10.5
12.0
10.5
PHZ, tPLZ
Output Disable Time
±
Note 13: Voltage Range 5.0 is 5.0V 0.5V.
±
Voltage Range 3.3 is 3.3V 0.3V.
5
www.national.com
AC Operating Requirements
54ACQ
=
TA −55˚C
VCC
(V)
Symbol
Parameter
to +125˚C
Units
(Note 14)
=
CL 50 pF
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to LE
3.3
5.0
3.3
5.0
3.3
5.0
3.0
3.0
1.5
1,5
5.0
5.0
ns
ns
ns
th
Hold Time, HIGH or LOW
Dn to LE
tw
LE Pulse Width, HIGH
±
Note 14: Voltage Range 5.0 is 5.0V 0.5V.
±
Voltage Range 3.3 is 3.3V 0.3V.
AC Electrical Characteristics
54ACTQ
=
TA −55˚C
VCC
(V)
Symbol
Parameter
to +125˚C
Units
(Note 15)
=
CL 50 pF
Min
Max
t
PHL, tPLH
Propagation Delay
Dn to On
5.0
1.5
10.5
ns
ns
tPHL, tPLH
Propagation Delay
LE to On
5.0
1.5
11.5
tPZL, tPZH
PHZ, tPLZ
Output Enable Time
Output Disable Time
5.0
5.0
1.5
1.5
11.0
10.5
ns
ns
t
±
Note 15: Voltage Range 5.0 is 5.0V 0.5V.
AC Operating Requirements
54ACTQ
=
TA −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
Units
(Note 16)
=
CL 50 pF
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to LE
5.0
5.0
5.0
3.5
ns
ns
ns
th
Hold Time, HIGH or LOW
Dn to LE
1.5
5.0
tw
LE Pulse Width, HIGH
±
Note 16: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
=
VCC 5.0V
CPD
44.0
pF
www.national.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明