54ACTQ374D [NSC]
Quiet Series Octal D Flip-Flop with TRI-STATE Outputs; 宁静系列八D触发器具有三态输出
| 型号： | 54ACTQ374D |
| 厂家： | 
National Semiconductor |
| 描述： | Quiet Series Octal D Flip-Flop with TRI-STATE Outputs |
| 文件： | 总8页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54ACQ374 • 54ACTQ374
Quiet Series Octal D Flip-Flop with TRI-STATE® Outputs
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Buffered positive edge-triggered clock
n TRI-STATE outputs drive bus lines or buffer memory
address registers
General Description
The ’ACQ/’ACTQ374 is
a high-speed, low-power octal
D-type flip-flop featuring separate D-type inputs for each
flip-flop and TRI-STATE outputs for bus-oriented applica-
tions. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
n Outputs source/sink 24 mA
The ’ACQ/’ACTQ374 utilizes Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series
n Faster prop delays than the standard ’AC/’ACT374
n 4 kV minimum ESD immunity
n Standard Military Drawing (SMD)
— ’ACTQ374: 5962-92189
™
features
™
GTO output control and undershoot corrector in addition to
a split ground bus for superior performance.
— ’ACQ374: 5962-92179
Features
n ICC and IOZ reduced by 50%
Logic Symbols
Connection Diagrams
Pin Assignment for DIP
and Flatpak
DS100239-1
IEEE/IEC
DS100239-3
Pin Assignment for LCC
DS100239-2
DS100239-4
™
GTO is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
™
FACT Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100239
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Connection Diagrams (Continued)
Pin Names
D0–D7
CP
Description
Data Inputs
Clock Pulse Input
OE
TRI-STATE Output Enable Input
TRI-STATE Outputs
O0–O7
Functional Description
Truth Table
The ’ACQ/’ACTQ374 consists of eight edge-triggered
flip-flops with individual D-type inputs and TRI-STATE true
outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Operation
of the OE input does not affect the state of the flip-flops.
Inputs
CP
Outputs
Dn
H
L
OE
L
On
H
L
N
N
L
X
X
H
Z
=
=
=
=
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
N =
LOW-to-HIGH Transition
Logic Diagram
DS100239-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’ACQ
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACTQ
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
0V to VCC
=
VI VCC + 0.5V
Operating Temperature (TA)
54ACQ/ACTQ
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate ∆V/∆t
’ACQ Devices
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
% to 70% of V
VIN from 30
CC
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
@
VCC 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate ∆V/∆t
’ACTQ devices
±
±
or Sink Current (IO
)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
Storage Temperature (TSTG
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
±
DC Latch-Up Source or Sink Current
Junction Temperature (TJ)
CDIP
300 mA
175˚C
Note 2: All commercial packaging is not recommended for applications re-
quiring greater than 2000 temperature cycles from −40˚C to +125˚C.
DC Characteristics for ’ACQ Family Devices
54ACQ
=
Symbol
Parameter
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
4.4
5.4
(Note 3)
=
VIN VIL or VIH
=
IOH −12 mA
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
=
IOH −24 mA
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 3)
=
IOL 12 mA
3.0
4.5
5.5
5.5
0.50
0.50
0.50
=
IOL 24 mA
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
1.0
µA
VI VCC, GND
(Note 5)
(Note 4)
Minimum Dynamic
Output Current
=
VOLD 1.65V Max
IOLD
IOHD
5.5
5.5
50
mA
mA
=
VOHD 3.85V Min
−50
3
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DC Characteristics for ’ACQ Family Devices (Continued)
54ACQ
=
Symbol
Parameter
VCC
(V)
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
ICC
Maximum Quiescent
Supply Current
5.5
80.0
µA
VIN VCC
or GND (Note 5)
=
IOZ
Maximum TRI-STATE
Leakage Current
VI(OE) VIL, VIH
=
±
5.5
5.0
5.0
5.0
µA
V
VI VCC, GND
=
VO VCC, GND
VOLP
Quiet Output
1.5
Maximum Dynamic VOL
Quiet Output
(Notes 6, 7)
(Notes 6, 7)
VOLV
−1.2
V
Minimum Dynamic VOL
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 5:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54ACQ 25˚C is identical to 74ACQ 25˚C.
CC
Note 6: Plastic DIP Package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output GND.
Note 8: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (’ACQ). Input-under-test switching: 5V to threshold (V ), 0V to threshold (V ),
@
ILD IHD
=
f
1 MHz.
DC Characteristics for ’ACTQ Family Devices
54ACTQ
=
Symbol
Parameter
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 9)
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 9)
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.50
0.50
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum TRI-STATE
Current
1.0
µA
µA
mA
VI VCC, GND
=
±
IOZ
5.5
5.5
5.0
VI VIL, VIH
=
VO VCC, GND
=
VI VCC − 2.1V
ICCT
Maximum ICC/Input
(Note 9)
1.6
=
VOLD 1.65V Max
IOLD
IOHD
Minimum Dynamic
Output Current
5.5
5.5
50
mA
mA
=
VOHD 3.85V Min
−50
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4
DC Characteristics for ’ACTQ Family Devices (Continued)
54ACTQ
=
Symbol
Parameter
VCC
(V)
TA −55˚C to +125˚C
Units
µA
V
Conditions
Guaranteed Limits
=
ICC
Maximum Quiescent
Supply Current
5.5
80.0
VIN VCC
or GND (Note 11)
VOLP
Quiet Output
5.0
5.0
1.5
Maximum Dynamic VOL
Quiet Output
(Notes 12, 13)
(Notes 12, 13)
VOLV
−1.2
V
Minimum Dynamic VOL
Note 9: All outputs loaded; thresholds on input associated with output under test.
Note 10: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACTQ 25˚C is identical to 74ACTQ 25˚C.
Note 11:
I
CC
Note 12: Plastic DIP package.
Note 13: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output GND
@
Note 14: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (V ), 0V to threshold (V ),
ILD
IHD
=
f
1 MHz.
AC Electrical Characteristics
54ACQ
=
VCC
(V)
TA −55˚C
Fig.
Symbol
Parameter
to +125˚C
Units
No.
=
CL 50 pF
(Note 15)
Min
Max
fmax
Maximum Clock
Frequency
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
95
95
MHz
ns
t
t
t
PLH, tPHL
PZL, tPZH
PHZ, tPLZ
Propagation Delay
CP to On
1.0
1.0
1.0
1.0
1.0
1.0
16.5
11.0
16.5
11.5
12.0
10.5
Output Enable Time
ns
Output Disable Time
ns
±
Note 15: Voltage Range 5.0 is 5.0V 0.5V
±
Voltage Range 3.3 is 3.3V 0.3V
AC Operating Requirements
54ACQ
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note 16)
CL 50 pF
Guaranteed
Minimum
3.0
ts
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
3.3
5.0
3.3
5.0
ns
ns
ns
3.0
th
Hold Time, HIGH or LOW
Dn to CP
2.0
1.5
tw
CP Pulse Width,
HIGH or LOW
5.0
5.0
±
Note 16: Voltage Range 5.0 is 5.0V 0.5V
±
Voltage Range 3.3 is 3.3V 0.3V
5
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AC Electrical Characteristics
54ACTQ
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note 17)
Min
Max
fmax
Maximum Clock
Frequency
5.0
5.0
95
MHz
ns
t
PLH, tPHL
Propagation Delay
CP to On
2.0
11.5
tPZL, tPZH
PHZ, tPLZ
Output Enable Time
Output Disable Time
5.0
5.0
2.0
1.5
11.5
10.5
ns
ns
t
±
Note 17: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACTQ
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note 18)
CL 50 pF
Guaranteed
Minimum
3.5
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
ns
ns
ns
th
Hold Time, HIGH or LOW
Dn to CP
2.0
5.0
tw
CP Pulse Width,
HIGH or LOW
±
Note 18: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
Input Capacitance
=
VCC 5.0V
CPD
Power Dissipation Capacitance
42.0
pF
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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