SM5837AF [NPC]
Variable-length 1H Delay Line LSI; 可变长度1H延迟线的LSI
| 型号： | SM5837AF |
| 厂家： | 
NIPPON PRECISION CIRCUITS INC |
| 描述： | Variable-length 1H Delay Line LSI |
| 文件： | 总8页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM5837AF
Variable-length 1H Delay Line LSI
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
PINOUT
The SM5837AF is a variable-length delay line LSI.
It has 12-bit input/output signal which can be set to
undergo a delay in the range of 31 to 2078 delay bits.
Maximum operating frequency is 40 MHz, making it
ideal for use in video signal processing applications.
TOP VIEW
DL0/SDI
DL1/SICK
DL2/LEN
DL3
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
DI8
DI9
FEATURES
DI10
DI11
OE
■ Variable-length 1H delay
■ 12-bit input/output signal width
■ 31 to 2078- bit delay length range
■ 40 MHz maximum operating frequency
■ Selectable delay setting method
• 11-bit parallel input
DL4
VSS1
CLK
VDD
DO11
DO10
DO9
DO8
DL5
DL6
DL7
DL8 10
DL9 11
• 3-line serial input
■ TTL-compatible input/outputs
■ Tristate outputs
■ 4.75 to 5.25 V operating voltage
■ 44-pin QFP
■ Molybenum-gate CMOS process
APPLICATIONS
■ Video signal image processing
PACKAGE DIMENSIONS
Unit: mm
44-pin QFP
+
12.80 0.30
-
10.00
+
0.60 0.20
-
+
0.35 0.10
0.80
-
NIPPON PRECISION CIRCUITS—1
SM5837AF
BLOCK DIAGRAM
12
12
12
Variable-length
DO0 - 11
DI0 - 11
12-bit
1H Delay
CLK
OE
Delay Length Control
RSTN
PARA
11
Parallel/Serial Select
11
VDD
SDI
SICK
LEN
VSS2
VSS1
SIPO
11
DL0 - 10
PIN DESCRIPTION
(1)
Number
1
Name
DL0/SDI
DL1/SICK
DL2/LEN
DL3
I/O
Function
Ip
Delay length set parallel data bit DL0 (LSB) when PARA is HIGH, and SDI serial data input when PARA is LOW.
2
Ip
Ip
Ip
Ip
–
Delay length set parallel data bit DL1 (bit 1) when PARA is HIGH, and SICK shift clock when PARA is LOW.
3
Delay length set parallel data bit DL2 (bit 2) when PARA is HIGH, and LEN latch clock when PARA is LOW.
4
Delay length set data bit 3
Delay length set data bit 4
Ground (0 V) pin 1
5
DL4
6
VSS1
DL5
7
Ip
Ip
Ip
Ip
Ip
Ip
O
O
O
O
–
Delay length set data bit 5
Delay length set data bit 6
Delay length set data bit 7
Delay length set data bit 8
Delay length set data bit 9
Delay length set data bit 10
Signal output data bit 0
Signal output data bit 1
Signal output data bit 2
Signal output data bit 3
Ground (0 V) pin 2
8
DL6
9
DL7
10
11
12
13
14
15
16
17
18
19
20
21
DL8
DL9
DL10
DO0
DO1
DO2
DO3
VSS2
DO4
O
O
O
O
Signal output data bit 4
Signal output data bit 5
Signal output data bit 6
Signal output data bit 7
DO5
DO6
DO7
NIPPON PRECISION CIRCUITS—2
SM5837AF
(1)
Number
22
Name
NC
I/O
Function
–
No connection
23
DO8
DO9
DO10
DO11
VDD
CLK
OE
O
O
O
O
–
Signal output data bit 8
Signal output data bit 9
Signal output data bit 10
Signal output data bit 11
Supply (5 V) pin
24
25
26
27
28
I
Clock input
29
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Tristate output enable. Enable when HIGH, and disable when LOW.
Signal input data bit 11
30
DI11
DI10
DI9
31
Signal input data bit 10
32
Signal input data bit 9
33
DI8
Signal input data bit 8
34
DI7
Signal input data bit 7
35
DI6
Signal input data bit 6
36
DI5
Signal input data bit 5
37
DI4
Signal input data bit 4
38
DI3
Signal input data bit 3
39
DI2
Signal input data bit 2
40
DI1
Signal input data bit 1
41
DI0
Signal input data bit 0
42
RSTN
Reset pin. Normal operation when HIGH, and reset operation when LOW.
Delay length setting method select.
Parallel data (DL0 to DL10) when HIGH, and serial input (SDI, SICK, LEN) when LOW.
43
44
PARA
NC
Ip
–
No connection
1. Ip = input pin with built-in pull-up resistor, O = output.
SPECIFICATIONS
Absolute Maximum Ratings
V
= V
= V
= 0 V
SS
SS1
Parameter
SS2
Symbol
Condition
Rating
Unit
V
Supply voltage range
Input voltage range
V
−0.3 to 7.0
DD
V
V
− 0.3 to V + 0.3
V
IN
SS
DD
Storage temperature range
Power dissipation
T
−40 to 125
450
°C
mW
°C
s
stg
P
D
Soldering temperature
Soldering time
T
255
sld
t
10
sld
Recommended Operating Conditions
V
= 0 V
SS
Parameter
Symbol
Condition
Rating
Unit
V
Supply voltage range
Operating temperature
V
4.75 to 5.25
−20 to 70
DD
T
°C
opr
NIPPON PRECISION CIRCUITS—3
SM5837AF
DC Characteristics
V
= 4.75 to 5.25 V, V = 0 V, T = −20 to 70 °C unless otherwise specified
DD
SS
a
Rating
typ
Parameter
Symbol
Condition
Unit
min
max
V
= 5.0V, CLK frequency
DD
Current consumption
I
–
–
85
mA
DD
f = 40 MHz, OE = 0 V
C
V
2.4
–
–
–
–
0.5
–
V
V
V
V
IH
(1) (2)
Input voltage
V
IL
V
I
= −0.4 mA
= 1.6 mA
= 0 V
4.0
–
–
OH
OH
(3)
Output voltage
V
I
–
0.4
20
1
OL
OL
(2)
Input current
I
V
–
10
–
µ
µ
µ
µ
µ
A
A
A
A
A
IL
IN
(1) (2)
Input leakage current
I
V
= V
DD
–
LH
IN
(1)
Input leakage current
I
V
= 0 V
–
–
1
LL
IN
I
V
= V
DD
–
–
5
ZH
OUT
Output high-impedance leakage
(3)
current
I
V
= 0 V
–
–
5
ZL
OUT
1. Pin CLK.
2. Pins DI0 to DI11, PARA, DL0/SDI, DL1/SICK, DL2/LEN, DL3 to DL10, OE and RSTN.
3. Pins DO0 to DO11.
AC Characteristics
V
= 4.75 to 5.25 V, V = 0 V, T = −20 to 70 °C unless otherwise specified
DD
SS
a
Rating
Parameter
CLK clock cycle
Symbol
Condition
Unit
min
25
10
10
50
20
20
–
typ
–
max
–
t
ns
ns
ns
ns
ns
ns
ns
ns
CP1
CLK clock HIGH-level pulsewidth
CLK clock LOW-level pulsewidth
SICK clock cycle
t
–
–
CH1
t
–
–
CL1
t
–
–
CP2
SICK clock HIGH-level pulsewidth
SICK clock LOW-level pulsewidth
CLK, SICK and LEN rise time
CLK, SICK and LEN fall time
t
–
–
CH2
t
–
–
CL2
t
1.0 to 2.0 V
–
10
10
CR
t
1.0 to 2.0 V
–
–
CF
DI0 to DI11, DL0 to DL10 and RSTN
setup time
t
10
0
–
–
–
–
ns
ns
S1
DI0 to DI11, DL0 to DL10 and RSTN
hold time
t
H1
SDI setup time
t
25
25
25
25
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
S2
SD1 hold time
t
H2
SICK rising edge → LEN rising edge
LEN rising edge → SICK rising edge
CLK → DO0 to D011 output delay
CLK → DO0 to D011 output hold time
OE HIGH-level pulsewidth
OE LOW-level pulsewidth
t
–
CE
t
–
EC
t
20
–
PD
See “Load conditions 1”.
t
5
OH
t
t
50
50
–
OEH
OEL
–
NIPPON PRECISION CIRCUITS—4
SM5837AF
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
–
max
25
t
ns
ns
ns
ns
pF
pF
PZL
OE → DO0 to DO11 output enable
delay
t
–
–
25
PZH
See “Load conditions 2”.
f = 1 MHz
t
–
–
25
PLZ
OE → DO0 to DO11 output disable
delay
t
–
–
25
PHZ
Input capacitance
Output capacitance
C
–
–
10
IN
C
f = 1 MHz, OE = V
–
–
15
OUT
IL
Load conditions 1
Load conditions 2
500
OUTPUT
OUTPUT
Ω
,
0V(
)
)
tPHZ tPZH
40pF
40pF
,
2.6V(tPLZ tPZL
tCR
tCF
2.4V Min
1.5V
0.5V Max
2.0V
CLK
1.0V
tCH1
tCL1
tCP1
CLK
DI0 - 11
DL0 - 10
RSTN
1.5V
1.5V
1.5V
1.5V
tS1
tS1
tS1
tH1
tH1
tH1
CLK
1.5V
1.5V
tPD
tOH
VALID
VALID
DO0 - 11
NIPPON PRECISION CIRCUITS—5
SM5837AF
tOEH
tOEL
OE
1.5V
1.5V
1.5V
tPZH
tPHZ
0.5V
0.5V
Hi-Z
Hi-Z
tPZL
tPLZ
DO0 - 11
tCP2
tCL2
tCH2
SICK
SDI
1.5V
tS2
tH2
1.5V
1.5V
tCE
tEC
LEN
FUNCTIONAL DESCRIPTION
Parallel Input Set Method
(PARA, DL0 to DL10)
The SM5837AF provides a built-in 1H delay for
video signal processing. The delay can be set to a
length of 31 to 2078 clock delay bits. The delay
When PARA is HIGH, parallel input data is used to
set the delay length. The delay length (L ) is deter-
mined by the input data on DL0 to DL10 as shown in
equation 1 and table 1.
H
length (L ) can be set using 2 methods, selected by
H
the state of PARA. When PARA is HIGH, the delay
length is set by parallel input data on DL0 to DL10.
When PARA is LOW, the delay length is set by serial
input data using SDI, SICK and LEN. Accordingly,
the function of DL0/SDI, DL1/SICK and DL2/LEN
is determined by PARA.
10
k
L
= 31 +
{DLk × 2 }
(1)
∑
H
k = 0
Table 1. Delay bit length setting
DL10
DL9
0
DL8
0
DL7
0
DL6
0
DL5
0
DL4
0
DL3
DL2
0
DL1
DL0
Delay length
0
0
0
0
0
↓
0
0
0
0
0
0
↓
0
0
0
1
0
1
0
↓
1
31
32
33
34
35
↓
0
0
0
0
0
0
0
0
1
1
0
↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
↓
↓
↓
↓
↓
↓
↓
0
1
1
1
1
0
0
512
NIPPON PRECISION CIRCUITS—6
SM5837AF
Table 1. Delay bit length setting
DL10
DL9
0
DL8
1
DL7
1
DL6
1
DL5
1
DL4
0
DL3
0
DL2
0
DL1
DL0
Delay length
0
↓
0
0
↓
1
1
↓
1
1
1
0
513
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
0
1
↓
0
1
↓
1
1
↓
1
0
↓
1
0
↓
0
1
1
1
1
1
1
0
0
0
1024
1025
↓
1
1
1
1
1
0
0
0
↓
↓
↓
↓
↓
↓
↓
↓
1
1
1
1
1
0
0
0
2048
2049
↓
1
1
1
1
1
0
0
0
↓
↓
↓
↓
↓
↓
↓
↓
1
1
1
1
1
1
1
1
2077
2078
1
1
1
1
1
1
1
1
Serial Input Set Method
(PARA, SDI, SICK, LEN)
the serial-to-parallel converter shift register on the
rising edge of SICK, and 11-bit parallel data is then
latched into the delay length set register on the rising
edge of LEN.
When PARA goes LOW, 3-input serial data set
method is used to set the delay length. Inputs DL3 to
DL10 are ignored. SDI, SICK and LEN function as
the serial data input, serial data shift clock and latch
clock enable, respectively.
The delay length (L ) is determined by the input
H
data S0 to S10 (just as for parallel input data DL0 to
DL10) as shown in equation 2. See also table 1.
The serial input data format, shown in figure XREF,
comprises 11-bit serial data (S0 to S10) input on SDI
in sync with SICK. The data on SDI is clocked into
Note that SICK and CLK can be asynchronous.
10
k
L
= 31 +
{Sk × 2 }
(2)
∑
H
k = 0
SDI
SICK
LEN
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Dotted lines indicate possible SICK and LEN states.
Figure 1. Serial input data format
Delay Clock Input (CLK)
Output Data (DO0 to DO11,OE)
All 1H delay registers operate in sync with the delay
clock CLK. The maximum clock frequency is 40
MHz.
DO0 to DO11 are the 12-bit data outputs. They are
tristate outputs, with the output state selected by OE.
When OE is HIGH, the outputs are enabled. When
OE is LOW, the outputs are disabled (high-imped-
ance state).
Input Data (DI0 to DI11)
DI0 to DI11 are the 12-bit data inputs.
Reset (RSTN)
At power-ON, the internal timing generator circuits
must be initialized by a LOW-level input on RSTN.
After RSTN goes HIGH, the set delay length
becomes active.
NIPPON PRECISION CIRCUITS—7
SM5837AF
Parallel Set Data (Delay Length = 31)
TIMING DIAGRAMS
0
1
2
3
4
5
31
32
33
34
35
CLK
RSTN
DI0 - 11
D1
D2
D3
D4
D5
D31 D32 D33 D34 D35
OE
DO0 - 11
UNKNOWN
D1
D2
D3
D5
Hi-Z
PARA=H , DL0-10=L
Serial Set Data (Delay Length = 32)
DL0/SDI
0
1
2
3
4
5
6
7
8
9
10
DL1/SICK
DL2/LEN
RSTN
1
2
3
32
33
34
CLK
DI0 - 11
DO0 - 11
INVALID
D1
D2
D3
UNKNOWN
D1
D2
D3
PARA=L , DL3-10=Don't Care , OE=H
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, 2-chome Fukuzumi
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
NIPPON PRECISION CIRCUITS INC.
Facsimile: 03-3642-6698
NC9408AE 1996.01
NIPPON PRECISION CIRCUITS—8
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