SM5838AS [NPC]
5120 X 8-bit Synchronous FIFO; 5120 ×8位同步FIFO
| 型号： | SM5838AS |
| 厂家： | 
NIPPON PRECISION CIRCUITS INC |
| 描述： | 5120 X 8-bit Synchronous FIFO |
| 文件： | 总14页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM5838AS
5120 × 8-bit Synchronous FIFO
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
PINOUT
The SM5838AS is a 5120 × 8-bit synchronous FIFO
(first in, first out) high-speed line buffer. Internally, it
employs static CMOS circuits which mean that it
effectively has limitless data hold times. It can oper-
ate at speeds up to 33.3 MHz (normal-voltage speci-
fication).
(TOP VIEW)
1
2
3
4
24 DIN0
DOUT0
DOUT1
DOUT2
DOUT3
OE
23
DIN1
DIN2
22
21
DIN3
The SM5838AS can be used to easily realize a 1-line
delay in high-speed facsimile machines and digital
copiers.
5
6
7
20 WE
19
RR
RW
18 VDD
VSS
RE
CLK
8
9
17
16
FEATURES
DOUT4
DIN4
■ 5120 × 8-bit structure
DOUT5 10
DOUT6 11
DOUT7 12
15 DIN5
14
■ Variable-length delay (21 to 5120 bits)
■ 33.3 MHz high-speed operation (normal-voltage
specification)
DIN6
13 DIN7
■ All input/outputs TTL compatible
■ Independent read enable and output enable pins,
allowing read address pointer increment in output
data hold and output high-impedance states
■ Supply voltage
• 4.5 to 5.5 V (normal-voltage specification)
• 3.0 to 4.5 V (low-voltage specification)
■ 24-pin SOP package
■ Molybdenum-gate CMOS process
■ A3-paper 1-line (16 dots/mm) compatible
PACKAGE DIMENSIONS
24-pin SOP (Unit: mm)
15.8TYP
0
10
1.0 0.2
+ 0.10
+ 0.08
0.915
0.4
0.17
- 0.07
1.27 0.1
- 0.05
NIPPON PRECISION CIRCUITS—1
SM5838AS
BLOCK DIAGRAM
8
32
32
8
SRAM
DOUT
DIN
8
8
OE
Decoder
RE
RR
WE
RW
Write address pointer
Read address pointer
CLK
PIN DESCRIPTION
Number
1
Name
DOUT0
DOUT1
DOUT2
DOUT3
OE
I/O
Function
O
Read data output bit 0
Read data output bit 1
Read data output bit 2
Read data output bit 3
Output enable input
Reset read input
2
O
O
O
I
3
4
5
6
RR
I
7
VSS
–
I
Ground (0 V) pin
8
RE
Read enable input (read address pointer)
Read data output bit 4
Read data output bit 5
Read data output bit 6
Read data output bit 7
Write data input bit 7
Write data input bit 6
Write data input bit 5
Write data input bit 4
Clock input
9
DOUT4
DOUT5
DOUT6
DOUT7
DIN7
DIN6
DIN5
DIN4
CLK
O
O
O
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
I
I
I
VDD
–
I
Supply pin
RW
Reset write input
WE
I
Write enable input (write address pointer)
Write data input bit 3
Write data input bit 2
Write data input bit 1
Write data input bit 0
DIN3
DIN2
DIN1
DIN0
I
I
I
I
NIPPON PRECISION CIRCUITS—2
SM5838AS
SPECIFICATIONS
Absolute Maximum Ratings
V
= 0 V
SS
Parameter
Symbol
Condition
Rating
Unit
V
Supply voltage range
Input voltage range
Storage temperature range
Power dissipation
V
−0.3 to 7.0
DD
V
V
− 0.3 to V + 0.3
V
IN
SS
DD
T
−40 to 125
500
°C
mW
°C
s
stg
P
D
Soldering temperature
Soldering time
T
255
sld
t
10
sld
Recommended Operating Conditions
V
= 0 V
SS
Rating
typ
5.0
Parameter
Symbol
Condition
Unit
min
4.5
max
5.5
4.5
70
Normal-voltage specification
Low-voltage specification
V
V
Supply voltage range
Operating temperature
V
DD
3.0
3.3
T
−20
–
°C
opr
DC Characteristics
5 V supply
typ
3 V supply
typ
Parameter
Symbol
Condition
Unit
min
max
min
max
Operating current
consumption
1
I
No output load
–
75
–
90
–
22
–
30
mA
DD
Standby current
consumption
I
–
50
–
50
µ
A
ST
2
Input leakage current
I
V
= V
DD
–
–
–
–
–
–
–
–
–
–
1
1
–
–
–
–
–
–
–
–
–
–
1
1
µ
µ
A
A
LH
IN
3
Input leakage current
I
V =0V
IN
LL
2
Input voltage
V
2.4
–
–
2.0
–
–
V
IH
3
Input voltage
V
0.5
5
0.5
5
V
IL
I
OE = HIGH, V
= V
DD
–
–
ZH
OUT
Output high-impedance
µ
A
4
leakage current
I
OE = HIGH, V
=0V
–
5
–
5
ZL
OUT
V
I
= −1 mA
2.5
–
–
2.0
–
–
OH
OH
4
Output voltage
V
V
I
= 2 mA
0.4
0.8
OL
OH
1. Normal-voltage specification (CLK = 33.3 MHz); Low-voltage specification (CLK = 20 MHz, V = 3.3± 0.3 V)
DD
2. Pins CLK, RR and RE.
3. Pins DIN0 to DIN7, RW, WE and OE.
4. Pins DOUT0 to DOUT7.
Input/Outputs
Ta = 25°C, f = 1 MHz
Rating
Parameter
Symbol
Condition
Unit
min
–
typ
–
max
10
Input capacitance
Output capacitance
C
pF
pF
I
C
–
–
10
O
NIPPON PRECISION CIRCUITS—3
SM5838AS
AC Characteristics
Input timing
5 V supply
3 V supply
Parameter
Symbol
Condition
Unit
min
30
13
7
typ
–
max
–
min
50
23
10
4
typ
–
max
–
Clock cycle time
Clock pulsewidth
Input data setup time
Input data hold time
RW and RR setup time
RW and RR hold time
WE setup time
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
t
–
–
–
–
CKW
t
–
–
–
–
DS
t
3
–
–
–
–
DH
t
10
0
–
–
17
0
–
–
RS
t
–
–
–
–
RH
t
13
0
–
–
23
0
–
–
WES
WE hold time
t
–
–
–
–
WEH
RE setup time
t
13
0
–
–
23
0
–
–
RES
RE hold time
t
–
–
–
–
REH
OE setup time
t
10
0
–
–
17
0
–
–
OES
OE hold time
t
–
–
–
–
OEH
Rise and fall transition times
t
–
–
30
–
–
30
T
1. All voltages measured with relative to V .
SS
2. Input timing input voltage levels are V = 0 V and V = 3.0/2.5 V (5/3 V supply). Transition time is measured between V and V .
IL
IH
IH
IL
3. Input signal reference level is V = 1.5 V.
TH
4. Input timing ratings measured with t = 5 ns.
T
Normal-voltage (5 V) specification
Low-voltage (3 V) specification
3.0V
2.5V
0V
0V
5ns
5ns
5ns
5ns
tCK
tCKW
CLK
tCKW
tRS
tRW
tRH
RW
tRH
tRS
tRS
tRR
tRH
RR
tRS
tRH
tWEH
tWES
tWEH
tREH
tOEH
tWES
tRES
tOES
tDS
WE
RE
tREH
tRES
tOES
tOEH
OE
tDS
tDH
tDH
DIN
NIPPON PRECISION CIRCUITS—4
SM5838AS
Output timing
5 V supply
3 V supply
Parameter
Symbol
Condition
Unit
min
–
typ
–
max
20
–
min
–
typ
–
max
40
–
Access time
t
ns
ns
ns
ns
A
“Load circuit 1”
Output hold time
Output enable delay time
t
5
–
5
–
OH
1
1
t
5
–
27
27
5
–
40
40
ZO
“Load circuit 2”
Output disable delay time
t
5
–
5
–
OZ
1. t and t are measured with ±200 mV tolerance.
ZO
OZ
Normal-voltage (5 V) specification
Low-voltage (3 V) specification
2.0V
1.8V
0.8V
1.0V
tCK
t CKW
CLK
t CKW
tOEH
tOES
tOES
tOEH
OE
tA
tA
Hi-Z
DOUT
t OZ
t OH
tZO
RR="H" ,RE="L"
Load circuit 1
Load circuit 2
VDD
1.8k
VDD
Ω
1.8k
Ω
DOUT
DOUT
1.1kΩ
1.1k
Ω
30pF
5pF
NIPPON PRECISION CIRCUITS—5
SM5838AS
FUNCTIONAL DESCRIPTION
At power-ON reset, device operation can become
irregular during the interval when the control circuits
are being reset. After power-ON reset is released,
this can take up to several 10s of ms in some cases.
Write Reset Cycle, Read Reset Cycle
After power-ON, the write address pointer and read
address pointer positions are undefined. Accordingly,
it is necessary to initialize the pointers using a write
reset cycle and read reset cycle, respectively.
both the CLK rising edge setup time (t ) and hold
RS
time (t ). Note that a write reset cycle (read reset
RH
cycle) can occur simultaneously with a write cycle
(read cycle). If the cycles are not simultaneous, then
the write reset cycle (read reset cycle) is completed
at the start of the next write cycle (read cycle).
A write reset cycle (read reset cycle) is valid when
RW (RR) goes LOW for an interval that satisfies
Write reset cycle
n cycle
reset cycle
0 cycle
1 cycle
tCKW
CLK
RW
tCKW
tRW
tRS
tRH
tRH
tRS
tDS
tDS
tDH
tDH
(n-1)
(n)
(0)
(1)
DIN
WE="L"
Read reset cycle
n cycle
reset cycle
0 cycle
1 cycle
tCKW
CLK
tCKW
tRS
tRR
tRH
RR
tRH
tA
tRS
tA
tA
tA
(n-1)
(n)
(0)
(0)
(1)
DOUT
tOH
tOH
tOH
RE="L" , OE="L"
Note the even if a reset period (t , t ) is zero
RW RR
length in the write reset and read reset cycles, the
reset operation does take place.
NIPPON PRECISION CIRCUITS—6
SM5838AS
Write Cycle
Data input occurs on the rising edge of CLK at the
end of the write cycle.
The input data address is determined by the write
address pointer position. The write address pointer is
reset by RW (write reset cycle), and is incremented
on the rising edge of CLK whenever WE is LOW.
When WE goes HIGH, write operation is disabled
and the write address pointer stops.
n cycle
n+1 cycle
disable cycle
n+2 cycle
tCKW
CLK
tCKW
tWEH
tWES
tWEH
tWES
WE
tDS
tDS
DIN (n-1)
(n)
(n+1)
(n+2)
tDH
tDH
RW="H"
Read Cycle
When RE goes HIGH, read operation is disabled and
the read address pointer stops.
The output data address is determined by the read
address pointer position. The read address pointer is
reset by RR (read reset cycle), and is incremented on
the rising edge of CLK whenever RE is LOW. Data
Note that data being read was written at least 20
write cycles previously (FIFO minimum delay).
Therefore, if (write address pointer) − (read address
pointer) = 1 to 19, then a possibility exists that data
from the preceding line is output instead.
output starts t (max) after the rising edge of CLK at
A
the start of the read cycle and continues until t
(min) after the next rising edge of CLK.
OH
n cycle
n+1 cycle
disable cycle
n+2 cycle
tCKW
CLK
tCKW
tREH
tRES
tREH
tRES
RE
tA
tA
tA
DOUT (n-1)
(n)
(n+1)
(n+2)
tOH
tOH
RR="H" , OE="L"
NIPPON PRECISION CIRCUITS—7
SM5838AS
Output Enable
When OE is HIGH, DOUT0 to DOUT7 become high
impedance. Note that because RE operation is inde-
pendent of OE operation, the read address pointer
can be incremented even when the outputs are high
impedance.
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
t CKW
CLK
OE
t CKW
tOEH
tOES
tOES
tOEH
tA
tA
Hi-Z
(n-1)
DOUT
(n)
(n+3)
t OZ
tZO
RR="H" ,RE="L"
TYPICAL APPLICATIONS
Note that at power-ON, the write address pointer and
read address pointer positions are undefined.
Accordingly, RW and RR reset cycles are required.
1H Delay Line
A 5120-word delay line can be realized by perform-
ing simultaneous write reset and read reset at power-
ON.
1. Perform reset in sync with desired delay length.
2. Stagger RW and RR timing to desired delay
length.
3. Manipulate the write or read address pointer
using WE or RE to disable incrementing to
maintain sync with desired delay length.
An n-word delay line (21 to 5210-word) can be real-
ized using any of the following methods.
1H (5120-word) delay line timing
1H
2H
5119
cycle
5120+0
cycle
5120+1
cycle
5120+2
cycle
5120+3
cycle
0 cycle
1 cycle
2 cycle
CLK
tRS
tRH
RW
RR
t
DS tDH
2
DIN
0
1
5118
5119
0
0
1
1
2
2
3
3
tOH
tA
5120 cycle
DOUT
WE="L" , RE="L" , OE="L"
NIPPON PRECISION CIRCUITS—8
SM5838AS
n-word delay line timing 1
1H
2H
n-1
cycle
n+0
cycle
n+1
cycle
n+2
cycle
n+3
cycle
0 cycle
1 cycle
2 cycle
CLK
tRS
tRH
RW
RR
t
DS tDH
2
DIN
0
1
n-2
n-1
0
0
1
1
2
2
3
3
tOH
tA
n cycle
DOUT
WE="L" , RE="L" , OE="L"
n-word delay line timing 2
1H
2H
n-1
cycle
n+0
cycle
n+1
cycle
n+2
cycle
n+3
cycle
0 cycle
1 cycle
2 cycle
CLK
RW
tRS
tRH
tRS
tRH
RR
t
DS tDH
n-1
DIN
0
1
2
n-2
0
1
2
2
3
3
tOH
tA
n cycle
DOUT
0
1
WE="L" , RE="L" , OE="L"
2H
n-word delay line timing 3
1H
n-1
cycle
n+0
cycle
n+1
cycle
n+2
cycle
n+3
cycle
0 cycle
1 cycle
2 cycle
CLK
tRS
tRH
RW
RR
tRES
RE
DIN
t
DS tDH
0
1
2
n-2
n-1
0
1
2
2
3
3
tOH
tA
n cycle
DOUT
0
1
WE="L" , RE="L" , OE="L"
NIPPON PRECISION CIRCUITS—9
SM5838AS
High-speed Conversion
line by alternating between 2 SM5838AS devices (1
line/device).
For example, an NTSC signal interlace-to-noninter-
lace conversion. If interpolated line data can be
assumed to be similar to the preceding line data and
In reality, however, double the number of devices are
required for luminance signal (Y) and color differ-
ence signal (C) systems. And triple the number of
devices are required for RGB signal systems.
the write data rate is 14.3 MHz (4f ), then conver-
SC
sion can be realized by reading twice at 28.6 MHz
(8f ).
SC
Furthermore, interpolated line data, with appropriate
signal processing separation, can be read out line-by-
Preceding line data used as interpolated line
1819
0
1
2
3
4
5
0 1 2
CLK
WE
RW
nH
nH+1H
DIN
RE
0
1
2
909
0
1
2
909
OE
RR
nH-1H
nH
nH
nH+1H
DOUT
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1 2 3 4 5
909
909 *
909
909 *
*Output data 867 to 909 forms the preceding 1H data.
Interpolated data used as interpolated line
1819
0
1
2
3
4
5
0
1
2
CLK
WE
RW
nH
nH+1H
nH'+1H
(A)DIN
0
0
1
1
2
2
909
909
0
0
1
1
2
2
909
909
nH'
(B)DIN
(A)RE
(A)OE
(A)RR
nH
nH+1H
(A)DOUT
0
1
2
3
4
5
0
1 2 3 4 5
909 *
909 *
(B)RE
(B)OE
(B)RR
nH'-1H
nH'
(B)DOUT
0
1
2
3
4
5
0 1 2 3 4 5
909
909
*Output data 867 to 909 forms the preceding 1H data.
NIPPON PRECISION CIRCUITS—10
SM5838AS
1/2 Data Reduction
Input data rate reduction by half can be realized by
taking WE and RE simultaneously HIGH only once
every two clock cycles.
Noninterlace-to-interlace conversions line extraction
can be realized by switching WE LOW/HIGH in line
units and RE LOW/HIGH in word units.
1/2 data reduction
5119
0
1
2
3
4
5
0 1 2
CLK
WE
RW
nH
nH+1H
0 1 2 3 4 5 6 7 8 9
DIN
0
1
2
3
4
5
6
7
8
9
5119
5119
RE
OE
RR
nH-1H
10
nH
DOUT
0
2
4
6
8
12
14
5118
0
2
4
6
8
10
12
14
5118
1/2 line extraction (noninterlace-to-interlace conversion)
1819
0
1
2
3
4
5
0 1 2
CLK
WE
RW
nH-1H
nH
nH+1H
nH+2H
DIN
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0 1 2 3 4 5
909
909
909
909
RE
OE
RR
nH-2H
nH
DOUT
0
1
2
909
0
1
2
909
NIPPON PRECISION CIRCUITS—11
SM5838AS
1/2n data reduction (n × n pixel reduction)
Screen resolution reduction, or 2 × 2 pixel reduction,
can be realized by combining both 1/2 data reduction
and 1/2 line extraction schemes. Furthermore, n × n
pixel reduction (for integer n) can be realized by
changing the WE and RE disable intervals and the
RW and RR reset timing.
Also, if the same data is repeatedly read out in place
of other data that has been discarded, the screen reso-
lution can be reduced without changing the data rate
to realize a mosaic filter function.
2 × 2 pixel reduction (1/4 reduction)
2 pixels
Valid Invalid
2 pixels
Invalid Invalid
909
0
1 2 3 4 5
CLK
WE
RW
nH-1H
nH
nH+1H
nH+2H
DIN
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0 1 2 3 4 5
909
909
909
909
RE
OE
RR
nH-2H
nH
DOUT
0
2
908
0
2
908
2 × 2 pixel reduction (mosaic)
2 pixels
Valid
2 pixels
909
0
1 2 3 4 5
CLK
WE
RW
nH-1H
nH
nH+1H
nH+2H
DIN
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0 1 2 3 4 5
909
909
909
909
RE
OE
RR
nH
nH-2H
nH-2H
nH
DOUT
0
2
4
908*
0
2
4
908
0
2
4
908*
0
2
4
908
*Output date 902 to 908 forms the preceding 1H data.
NIPPON PRECISION CIRCUITS—12
SM5838AS
Wipe Function (Screen Switching)
Because RE and OE operate independently, a screen
wipe function can be realized using 2 SM5838AS
devices by switching OE LOW/HIGH in field units.
Screen wipe (OE changes in field units)
909
0
1 2 3 4 5
CLK
WE
RW
nH-1H
nH
nH+1H
nH+2H
(A)DIN
(B)DIN
0
0
1
1
2
2
3
3
4
5
0
0
1
1
2
2
3
3
4
5
0
0
1
1
2
2
3
3
4
5
0
0
1
1
2
2
3
3
4 5
909
909
909
909
909
909
909
909
nH'-1H
nH'
nH'+1H
5
nH'+2H
4
5
4
5
4
4 5
(A)RE
(A)OE
(A)RR
nH-2H
nH-1H
nH
5
nH+1H
(A)DOUT
4
5
4
5
4
4 5
909
909
909
909
(B)RE
(B)OE
(B)RR
nH'-2H
nH'-1H
nH'
nH'+1H
(B)DOUT
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Screen wipe image (left to right)
(B)
(A)
NIPPON PRECISION CIRCUITS—13
SM5838AS
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, 2-chome Fukuzumi
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
NIPPON PRECISION CIRCUITS INC.
Facsimile: 03-3642-6698
NC9411AE 1996.09
NIPPON PRECISION CIRCUITS—14
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