NJW1109D [NJRC]
Headphone Amplifier with Electronic Volume; 耳机放大器，具有电子音量
| 型号： | NJW1109D |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | Headphone Amplifier with Electronic Volume |
| 文件： | 总14页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW1109
Headphone Amplifier with Electronic Volume
■ PACKAGE OUTLINE
■ GENERAL DESCRIPTION
The NJW1109 is a headphone amplifier with electronic volume. It
includes widely gain adjustable volume, +20 to –80 dB, and mute
function. These are controlled by I2C bus. The NJW1109 is
suitable for headphone output on TV set.
NJW1109D NJW1109M
NJW1109V
■ FEATURES
■ Operating Voltage
■ Electronic Volume
■ I2C Bus Interface
■ Bi-CMOS Technology
■ Package Outline
7.5 to 10 V
+20dB to -80dB / 0.5dB step, Mute
DIP14, DMP14, SSOP14
■ BLOCK DIAGRAM
CAPa
SDA SCL
I2C
ADR
Interface
VOL
VOL
IN a
IN b
OUTa
OUTb
Vref
Bias
CAPb
V+ GND
■ PIN FUNCTION
SYMBOL
V+
SYMBOL
SCL
No.
FUNCTION
Power Supply
No.
8
FUNCTION
1
2
3
4
I2C Bus Clock Input
1
14
OUTb
N.C.
Bch Output
No Connect
9
Vref
INa
Reference voltage stabilized
capacitor connect terminal
10
11
Ach Input
CAPb
Balance control click noise
absorbing capacitor connect
terminal
CAPa
Volume control click noise
absorbing capacitor connect
terminal
5
6
7
INb
ADR
SDA
Bch Input
12
13
14
N.C.
OUTa
GND
No Connect
7
8
I2C Bus Slave Address
Select
I2C Bus Data Input
Ach Output
Ground
– 1 –
NJW1109
■ ABSOLUTE MAXIMUM RATING (Ta=25°C)
PARAMETER
Supply Voltage
SYMBOL
RATING
UNIT
V+
12
V
500 (DIP14)
500* (DMP14)
440* (SSOP14)
Power Dissipation
PD
mW
Operating Temperature Range
Storage Temperature Range
Topr
Tstg
-20 to +75
-40 to +125
°C
°C
*(Note) EIA/JEDEC STANDARD Test board(76.2 x 114.3 x 1.6mm, 2layers, FR-4)mounting
■ ELECTRICAL CHARACTERISTICS
(V+=9V, VIN=-20dBV, f=1kHz, RL=100Ω, VOL = 0dB , Ta=25°C
■POWER SUPPLY
)
PARAMETER
SYMBOL
V+
TEST CONDITION
MIN.
7.5
-
TYP.
9
5
MAX.
10
8
UNIT
V
mA
V
Operating Voltage
Operating Current
Reference Voltage
ICC
VREF
No Signal
4.0
4.5
5.0
■AMPLIFIER
PARAMETER
SYMBOL
GVMAX
GVMIN
TEST CONDITION
VOL = +20dB setting
VOL = -80dB setting
VOL = 0dB setting
MIN.
TYP.
20
-80
0
MAX.
UNIT
Volume Maximum Gain
Volume Minimum Gain
Voltage Gain Channel Balance
18
22
dB
∆Gv
-1.5
1.5
-
dB
VOL = -10dB setting
THD=3%
8.9
9.5
dBV
Maximum Input Voltage
VIM
(2.8)
(3.0)
(Vrms)
Output Power
PO
THD
CS
VOL = 10dB, THD=10%
70
-
70
-
100
0.1
80
-100
-
1
-
mW
%
dB
dB
VOL = 0dB setting
Total Harmonic Distortion
Channel Separation
Mute Level
Rg=600Ω, Vin = 0dBV
VOL = Mute, Vin = 0dBV
Mute
-90
-95
(18)
-105
(5.6)
-85
(56)
-95
dBV
(µVrms)
dBV
Output Noise Voltage 1
Output Noise Voltage 2
VNO1
Rg=0Ω, A-Weighted
-
VOL = Mute
Rg=0Ω, A-Weighted
Vripple=-20dBV, Rg=0Ω
VNO2
-
-
(18)
(µVrms)
Power Supply Ripple Rejection
■CONTROL
PSRR
70
-
dB
PARAMETER
SYMBOL
VADRH
TEST CONDITION
High : Slave Address 84H
Low : Slave Address 80H
MIN.
V+/2
-
TYP.
MAX.
-
1.0
UNIT
V
V
High Level Input Voltage
Low Level Input Voltage
-
-
VADRL
– 2 –
NJW1109
■ I2C BUS CHARACTERISTICS (SDA, SCL)
I2C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
SYMBOL
MIN.
0.0
2.5
0.25
0
TYP.
MAX.
1.5
5.0
-
UNIT
Low Level Input Voltage
High Level Input Voltage
Hysteresis of Schmitt trigger inputs
LOW level output voltage (3mA at SDA pin)
VIL
VIH
Vhys
VOL
-
-
-
-
V
V
V
V
0.4
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
tof
tSP
Ii
20+0.1Cb
-
-
-
250
50
ns
ns
µA
Pulse width of spikes which must be suppressed by the input filter
0
Input current each I/O pin with an input voltage between 0.1VDD
and 0.9VDDmax
-10
10
Capacitance for each I/O pin
SCL clock frequency
Ci
fSCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
400
-
-
-
-
0.9
-
300
300
-
-
pF
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
pF
V
Hold time (repeated) START condition.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
0.6
1.3
0.6
0.6
0
100
-
-
0.6
1.3
-
0.5
1
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the LOW level
Noise margin at the HIGH level
tf
tSU:STO
tBUF
Cb
VnL
VnH
400
-
-
V
Cb ; total capacitance of one bus line in pF.
SDA
tf
tBUF
tHD:STA
tSP
tr
tf
tr
tSU:DAT
SCL
tHD:STA
tSU:STA
tSU:STO
tLOW
tHD:DAT
tHIGH
S
Sr
P
S
– 3 –
NJW1109
■TERMINAL DESCRIPTION
No.
SYMBOL
FUNCTION
EQUIVALENT CIRCUIT
VOLTAGE
17k
5
INb
INa
Bch Input
Ach Input
V+/2
10
2
OUTb
OUTa
Bch Output
Ach Output
V+/2
3.8V
3.1V
13
12k
Balance control click noise
absorbing capacitor connect
terminal
8k
4
CAPb
8k
Volume control click noise
absorbing capacitor connect
terminal
11
CAPa
– 4 –
NJW1109
■TERMINAL DESCRIPTION
No.
SYMBOL
FUNCTION
EQUIVALENT CIRCUIT
VOLTAGE
4k
I2C Bus Slave Address
Select
6
ADR
-
12k
4k
7
8
SDA
SCL
I2C Bus Data Input
I2C Bus Clock Input
-
12k
200k
1.3k
Reference voltage stabilized
capacitor connect terminal
9
Vref
V+/2
200k
1
V+
Power Supply
Ground
-
-
-
-
14
GND
– 5 –
NJW1109
■ TEST CIRCUIT
TEST CIRCUIT 1 (GVMAX, GVMIN, ∆Gv, VIM, P , THD, Mute)
O
Input B
Output B
100Ω
100µF
VADRL VADRH
BPF:400Hz to 30KHz
0.47µF
1µF
V+
10µF
7
6
5
4
3
2
1
SDA ADR
INb CAPb NC OUTb V+
VOL
VOL
I2C Bus
Interface
Bias
SCL
8
Vref
9
INa CAPa NC OUTa GND
10
11
12
13
14
10µF
100µF
0.47µF
1µF
Output A
100 Ω
BPF:400Hz to 30KHz
Input A
– 6 –
NJW1109
TEST CIRCUIT 2 (Icc, VREF, VNO1,VNO2
)
Input B
Output B
100Ω
100µF
VADRL VADRH
A-Weighted
0.47µF
1µF
V+
[Icc]
10µF
7
6
5
4
3
2
1
SDA ADR
INb CAPb NC OUTb V+
VOL
VOL
I2C Bus
Interface
Bias
SCL
8
Vref
9
INa CAPa NC OUTa GND
10
11
12
13
14
[VREF
]
100µF
10µF 0.47µF
Output A
1µF
100 Ω
A-Weighted
Input A
– 7 –
NJW1109
TEST CIRCUIT 3 (CS)
Input B
Output B
Rg=600 Ω
VADRL VADRH
100 Ω
100µF
BPF:400Hz to 30KHz
1µF
V+
0.47µF
7
6
5
4
3
2
1
10µF
SDA ADR
INb CAPb NC OUTb V+
VOL
VOL
Rg=600 Ω
I2C Bus
Interface
Bias
SCL
8
Vref
9
INa CAPa NC OUTa GND
10 11 12 13 14
0.47µF
100µF
10µF
Output A
1µF
BPF:400Hz to 30KHz
100 Ω
Input A
Rg=600 Ω
– 8 –
NJW1109
TEST CIRCUIT 4 (PSRR)
Input B
Output B
BPF:400Hz to 30KHz
100 Ω
100µF
VADRL VADRH
Rg=0 Ω
1µF
0.47µF
7
6
5
4
3
2
1
10µF
V+
SDA ADR
INb CAPb NC OUTb V+
VOL
VOL
I2C Bus
Interface
Bias
SCL
8
Vref
9
INa CAPa NC OUTa GND
10
11
12
13
14
0.47µF
100µF
10µF
Output A
1µF
Rg=0 Ω
BPF:400Hz to 30KHz
100 Ω
Input A
– 9 –
NJW1109
■ APPLICATION CIRCUIT
Input B
30Ω
30Ω
Output B
0.47µF
100µF
1µF
V+
1
10µF
7
6
5
4
3
2
SDA ADR
INb CAPb NC OUTb V+
VOL
VOL
I2C Bus
Interface
Bias
SCL
8
Vref
9
INa CAPa NC OUTa GND
10
11
12
13
14
10µF
100µF
0.47µF
1µF
30 Ω
30 Ω
Output A
Input A
Mute
Mute
– 10 –
NJW1109
■ DEFINITION OF I2C REGISTER
■ I2C BUS FORMAT
MSB
LSB MSB
LSB MSB
LSB
S
Slave Address
A
Select Address
A
Data
A
P
1bit
8bit
1bit
8bit
1bit
8bit
1bit 1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
■ SLAVE ADDRESS
MSB
LSB
80H (ADR = Low)
84H (ADR = High)
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
■ SELECT ADDRESS
The auto-increment function cycles the select address as follows.
00H→01H→00H
BIT
Select
Address
D4
D3
D2
D1
D0
D7
D6
D5
00H
01H
VOL
CHS
BAL
Don’t Care
!CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
BIT
Select
Address
D4
D3
D2
D1
D0
D7
0
D6
0
D5
0
00H
01H
0
0
0
0
0
0
0
0
0
0
0
0
0
!CONTROL COMMAND TABLE
a) Master Volume
BIT
Select
Address
D4
D3
D2
D1
D0
D7
D6
D5
00H
•VOL : Master Volume
VOL
Attenuation level : +20 to –80dB(0.5dB/step), MUTE
b) Balance
BIT
Select
Address
D4
D3
D2
D1
D0
D7
D6
D5
01H
CHS
BAL
Don’t Care
•CHS : Balance channel select
“0” : Ach “Bch is attenuated”
“1” : Bch “Ach is attenuated”
•BAL : Ach and Bch Ach and Bch Balance
Balance Level : 0 to –30dB (1dB/Step) , MUTE
– 11 –
NJW1109
!CONTROL COMMAND TABLE
a) Master Volume (Select Address: 00H) Volume level : +20 to –80dB(0.5dB/step), MUTE
VOL
Gain(dB)
HEX
D7
D6
D5
D4
D3
D2
D1
D0
20
19.5
19
18.5
18
17.5
17
16.5
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
EE
ED
EC
EB
EA
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
DF
DE
DD
・・・
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
・・・
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
・・・
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
・・・
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
・・・
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
・・・
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
・・・
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
・・・
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
・・・
3.5
3
･･･
-79.5
-80
38
37
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
･･･
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
Mute
00
0
0
0
0
0
0
0
0
– 12 –
NJW1109
b) Balance (Select Address: 01H) Balance level : 0 to –30dB(1dB/step), MUTE
Channel Setting (CHS)
D7
Attenuated Bch Gain
Attenuated Ach Gain
0
1
BAL
D4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
Gain(dB)
D6
D5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
-1
-2
-3
-4
-5
-6
-7
-8
0
0
0
0
0
0
0
0
0
0
-9
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
-22
-23
-24
-25
-26
-27
-28
-29
-30
MUTE
1
– 13 –
NJW1109
[CAUTION]
The specifications on this data book are only
given for information, without any guarantee
as regards either mistakes or omissions. The
application circuits in this data book are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
– 14 –
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