NJW1111V [NJRC]
9-IN 3-OUT STEREO AUDIO SELECTOR; 9 -IN 3 -OUT立体声音频选择器
| 型号： | NJW1111V |
| 厂家： | 
NEW JAPAN RADIO |
| 描述： | 9-IN 3-OUT STEREO AUDIO SELECTOR |
| 文件： | 总8页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW1111
9-IN 3-OUT STEREO AUDIO SELECTOR
! GENERAL DESCRIPTION
! PACKAGE OUTLINE
The NJW1111 is a 9-input 3-output stereo audio selector.
It includes three independent 9input-1output stereo audio selectors
and adjustable gain buffers.
The NJW1111 performs superior audio characteristics such as low
distortion, low output noise and low crosstalk.
All of internal status and variables are controlled by three-wired
serial bus. Selectable two Chip address is available for using two
chips on same serial bus line. It is suitable for AV amplifier and
receiver system and others.
NJW1111V
! FEATURES
• Operating Voltage
±4.5 to ±7.5V
• 9-Input, 3-Output Stereo Audio Selector
• Operating Current
8mA typ.
• Low Distortion
• Low Output Noise
• Low Crosstalk
0.0007% typ.
-116dBV typ.
110dB typ.
• Channel Separation
• Variable Gain Buffer
• 3-Wired Serial Control
• Bi-CMOS Technology
• Package Outline
110dB typ.
0, 3 to 8dB/0.5dB step
SSOP32
! BLOCK DIAGRAM
InB1
InB2
InB3
InB4
InB6
InB7
InB8
InB9
OutB1
OutB2
OutB3
InB5
ADR
V+
V-
+
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
µ
F
µ
µ
µ
µ
µ
µ
µ
µ
10
F
10
F
10 F
µ
+
µ
µ
+
+
+
+
+
+
+
+
+
+
+
+
100
F
µ
100
F
µ
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
Gain
Gain
Gain
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
50K
ΩX１８
Gain
Gain
Gain
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
Control Logic
GND
10
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
+
+
+
+
+
+
+
+
+
+
+
+
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10 F
µ
µ
µ
µ
µ
µ
µ
µ
µ
10
F
10
F
10 F
µ
µ
µ
InA1
InA2
InA3
InA4
InA6
InA7
InA8
InA9
InA5
OutA1
OutA2
OutA3
LATCH
DATA
CLOCK
Ver.4.0
– 1 –
NJW1111
!PIN CONFIGURATION
32
InB2 31
30
1
2
InA1
InA2
InA3
InA4
InA5
InA6
InB1
3
InB3
4
InB4 29
InB5 28
InB6 27
5
6
26
7
InA7
InA8
InB7
InB8 25
InB9 24
GND 23
OutB1 22
8
InA9
9
GND
10
11
12
13
OutA1
OutA2
OutA3
21
20
OutB2
OutB3
19
18
ADR
V+
14 LATCH
DATA
15
CLOCK
16
17
V-
No. Symbol
Function
No. Symbol
Function
1
InA1
Ach Input 1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V-
V- Power Supply Terminal
2
InA2
Ach Input 2
Ach Input 3
Ach Input 4
Ach Input 5
Ach Input 6
Ach Input 7
Ach Input 8
Ach Input 9
V+
V+ Power Supply Terminal
Chip address setting terminal
Bch Output 3
Bch Output 2
Bch Output 1
Ground Terminal
Bch Input 9
3
InA3
ADR
OutB3
OutB2
OutB1
GND
InB9
InB8
InB7
InB6
InB5
InB4
InB3
InB2
InB1
4
InA4
5
InA5
6
InA6
7
InA7
8
InA8
9
InA9
Bch Input 8
10
11
12
13
14
15
16
GND
Ground Terminal
Ach Output 1
Ach Output 2
Ach Output 3
LATCH
Bch Input 7
OutA1
OutA2
OutA3
LATCH
DATA
CLOCK
Bch Input 6
Bch Input 5
Bch Input 4
Bch Input 3
DATA
Bch Input 2
CLOCK
Bch Input 1
Ver.4.0
– 2 –
NJW1111
! ABSOLUTE MAXIMUM RATING (Ta=25°C)
PARAMETER
Power Supply Voltage
SYMBOL
V+
RATING
UNIT
V
+8/-8
Maximum Input Voltage
Power Dissipation
VIM
V+/V-
V
800
PD
mW
NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting
Operating Temperature Range
Storage Temperature Range
Topr
Tstg
-40 to +85
°C
°C
-40 to +125
! RECOMMENDED OPERATING CONDITIONS (Ta=25°C)
PARAMETER
SYMBOL
V+/V-
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
V
Operating Voltage
-
±4.5
±7.0
±7.5
! ELECTRICAL CHARACTERISTICS
♦ Power Supply (Ta=25°C, V+/V-=±7V)
PARAMETER
Supply Current 1
Supply Current 2
SYMBOL
TEST CONDITION
MIN.
4.0
TYP.
8.0
MAX.
12.0
12.0
UNIT
MA
ICC
V+, No Signal
V-No Signal
IEE
4.0
8.0
MA
♦ AC CHARACTERISTICS (Ta=25°C, V+/V-=±7V, VIN=1Vrms,f=1kHz,RL=47k
Ω)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
-
UNIT
10.6
(3.4)
12.9
(4.4)
dBV
(Vrms)
Maximum Output Voltage
VOM
THD=1%
Voltage Gain 1
GV1
GV2
-
-0.5
0
0.5
dB
Voltage Gain 2
VIN=200mVrms, Gain=6dB
BW=400Hz-30kHz
5.0
6.0
7.0
Total Harmonic Distortion 1
Total Harmonic Distortion 2
Total Harmonic Distortion 3
Mute Level
THD1
THD2
THD3
ATT
-
-
-
-
-
-
-
-
-
0.0007
0.001
0.001
-110
0.02
Vin=2Vrms,
%
-
-
-
BW=400Hz-30kHz
f=10kHz, BW=400Hz-30kHz
Selector=Mute, A-weighted
Rg=0Ω, A-Weighted
Rg=0Ω, A-Weighted
Rg=0Ω, f=20kHz
dB
-116
(1.6)
-106
(5.0)
dBV
(µVrms)
Output Noise
VNO
Cross Talk 1
CT1
CT2
CS1
CS2
-110
-96
-
-
dB
Cross Talk 2
Channel Separation 1
Channel Separation 2
Rg=0Ω, A-Weighted
Rg=0Ω, f=20kHz
-110
-96
-90
-
dB
BW: Band Width
♦ Logic Control Characteristics (Ta=25°C, V+/V-=±7V)
PARAMETER
High Level Input Voltage
Low Level Input Voltage
SYMBOL
TEST CONDITION
ADR Terminal
ADR Terminal
MIN.
2.5
0
TYP.
MAX.
V+
UNIT
V
VADRH
-
-
VADRL
1.5
Ver.4.0
– 3 –
NJW1111
! TERMINAL DESCRIPTION
TERMINAL
DC
PIN NO.
SYMBOL
FUNCTION
EQUIVALENT CIRCUIT
VOLTAGE
V+
1 to 9
32 to 24
InA1 to 9
InB1 to 9
Ach Input 1 to 9
Bch Input 1 to 9
0V
200
Ω
50k
Ω
GND
V-(sub)
V+
V+
50
Ω
11 to 13 OutA1 to 3
22 to 20 OutB1 to 3
Ach Output 1 to 3
Bch Output 1 to 3
0V
50
Ω
200
Ω
V-(sub)
18
V+
V+ Power Supply Terminal
V+
V-(sub)
V+
10
23
GND
Ground Terminal
0V
V-(sub)
V+
14
15
16
19
LATCH
DATA
CLOCK
ADR
LATCH
DATA
CLOCK
4k
8k
Ω
Ω
0V
Chip address setting terminal
V-(sub)
Ver.4.0
– 4 –
NJW1111
! CONTROL DATA FORMAT
t7
t1
t4
t8
LATCH
t2 t3
CLOCK
DATA
MSB
D15 D14 D13 D12 D11 D10 D9
LSB
D0
D8
D7
D6
D5
D4
D3
D2
D1
t5 t6
(
✴
) MSB First
SYMBOL
PARAMETER
CLOCK Clock Width
CLOCK Pulse Width (High)
CLOCK Pulse Width (Low)
LATCH Rise Hold Time
DATA Setup Time
DATA Hold Time
CLOCK Setup Time
LATCH High Pulse Width
MIN
4
2
2
4
1.6
1.6
1.6
1.6
TYP
MAX
UNIT
µsec
µsec
µsec
µsec
µsec
µsec
µsec
µsec
t1
t2
t3
t4
t5
t6
t7
t8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Ver.4.0
– 5 –
NJW1111
! CONTROL DATA
NJW1111 control data is constructed with 16bits.
MSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Setting DATA
Select Address
Chip Address
MSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
0
D5
0
D4
0
D3
*
D2
*
D1
*
D0
*
Gain1
Selector1
0
0
0
Gain2
Gain3
Selector2
Selector3
0
0
1
*
*
*
*
0
1
0
*
*
*
*
* Chip address is set by chip address select terminal (ADR) status.
Chip address select
Chip Address
terminal
Low
D3
1
D2
0
D1
1
D0
0
High
1
0
1
1
!INITIAL CONDITION
MSB
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
D8
0
D7
0
D6
0
D5
0
D4
0
D3
*
D2
*
D1
*
D0
*
0
0
0
0
0
0
0
0
0
0
0
0
0
1
*
*
*
*
0
0
0
0
0
0
0
0
0
1
0
*
*
*
*
* Chip address is set by chip address select terminal (ADR) status.
Ver.4.0
– 6 –
NJW1111
! CONTROL DATA
D15
D14
D13
D12
D11
D10
D9
D8
D7
0
D6
0
D5
0
D4
0
D3
*
D2
*
D1
*
D0
*
Gain1
Selector1
Gain2
Gain3
Selector2
Selector3
0
0
0
1
*
*
*
*
0
0
1
0
*
*
*
*
a)Gain
DATA
D14
Setting
D15
0
D13
0
D2
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0dB
0
0
+3.0 dB
+3.5 dB
+4.0 dB
+4.5 dB
+5.0 dB
+5.5 dB
+6.0 dB
+6.5 dB
+7.0 dB
+7.5 dB
+8.0 dB
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
b)Input Selector
DATA
Setting
D11
0
D10
0
D9
0
D8
0
)
Mute(✴
0
0
0
1
InA1/B1
InA2/B2
InA3/B3
InA4/B4
InA5/B5
InA6/B6
InA7/B7
InA8/B8
InA9/B9
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
Ver.4.0
– 7 –
NJW1111
! APPLICATION CIRCUIT
InB1
InB2
InB3
InB4
InB6
InB7
InB8
InB9
OutB1
OutB2
OutB3
InB5
ADR
V+
V-
+
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
µ
F
µ
µ
µ
µ
µ
µ
µ
µ
10
F
10
F
10
F
+
µ
µ
µ
+
+
+
+
+
+
+
+
+
+
+
+
100
F
µ
100 F
µ
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
Gain
Gain
Gain
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
50K
ΩX１８
Gain
Gain
Gain
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
8dB to 3dB
/ 0.5dBstep
Control Logic
GND
10
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
+
+
+
+
+
+
+
+
+
+
+
+
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
F
10
µ
F
µ
µ
µ
µ
µ
µ
µ
µ
10
F
10
F
10 F
µ
µ
µ
InA1
InA2
InA3
InA4
InA6
InA7
InA8
InA9
InA5
OutA1
OutA2
OutA3
LATCH
DATA
CLOCK
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.4.0
– 8 –
相关型号：
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